drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                           \
  10         (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]    \
  11                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]  \
  12                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]      \
  13                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
  14                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]    \
  15                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]       \
  16                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
  17
  18 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                           \
  19         (enq_op =                                                              \
  20                  enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]     \
  21                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]       \
  22                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]          \
  23                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]    \
  24                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]    \
  25                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
  26                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
  27
  28 static uint32_t
  29 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  30 {
  31         uint32_t wdata = BIT(16) | 1;
  32
  33         switch (dev->gw_mode) {
  34         case CN10K_GW_MODE_NONE:
  35         default:
  36                 break;
  37         case CN10K_GW_MODE_PREF:
  38                 wdata |= BIT(19);
  39                 break;
  40         case CN10K_GW_MODE_PREF_WFE:
  41                 wdata |= BIT(20) | BIT(19);
  42                 break;
  43         }
  44
  45         return wdata;
  46 }
  47
  48 static void *
  49 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  50 {
  51         struct cnxk_sso_evdev *dev = arg;
  52         struct cn10k_sso_hws *ws;
  53
  54         /* Allocate event port memory */
  55         ws = rte_zmalloc("cn10k_ws",
  56                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  57                          RTE_CACHE_LINE_SIZE);
  58         if (ws == NULL) {
  59                 plt_err("Failed to alloc memory for port=%d", port_id);
  60                 return NULL;
  61         }
  62
  63         /* First cache line is reserved for cookie */
  64         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  65         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  66         ws->tx_base = ws->base;
  67         ws->hws_id = port_id;
  68         ws->swtag_req = 0;
  69         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  70         ws->lmt_base = dev->sso.lmt_base;
  71
  72         return ws;
  73 }
  74
  75 static int
  76 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  77 {
  78         struct cnxk_sso_evdev *dev = arg;
  79         struct cn10k_sso_hws *ws = port;
  80
  81         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  82 }
  83
  84 static int
  85 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  86 {
  87         struct cnxk_sso_evdev *dev = arg;
  88         struct cn10k_sso_hws *ws = port;
  89
  90         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  91 }
  92
  93 static void
  94 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
  95 {
  96         struct cnxk_sso_evdev *dev = arg;
  97         struct cn10k_sso_hws *ws = hws;
  98         uint64_t val;
  99
 100         rte_memcpy(ws->grps_base, grps_base,
 101                    sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
 102         ws->fc_mem = dev->fc_mem;
 103         ws->xaq_lmt = dev->xaq_lmt;
 104
 105         /* Set get_work timeout for HWS */
 106         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
 107         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
 108 }
 109
 110 static void
 111 cn10k_sso_hws_release(void *arg, void *hws)
 112 {
 113         struct cnxk_sso_evdev *dev = arg;
 114         struct cn10k_sso_hws *ws = hws;
 115         int i;
 116
 117         for (i = 0; i < dev->nb_event_queues; i++)
 118                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
 119         memset(ws, 0, sizeof(*ws));
 120 }
 121
 122 static void
 123 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 124                            cnxk_handle_event_t fn, void *arg)
 125 {
 126         struct cn10k_sso_hws *ws = hws;
 127         uint64_t cq_ds_cnt = 1;
 128         uint64_t aq_cnt = 1;
 129         uint64_t ds_cnt = 1;
 130         struct rte_event ev;
 131         uint64_t val, req;
 132
 133         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 134
 135         req = queue_id;     /* GGRP ID */
 136         req |= BIT_ULL(18); /* Grouped */
 137         req |= BIT_ULL(16); /* WAIT */
 138
 139         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 140         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 141         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 142         cq_ds_cnt &= 0x3FFF3FFF0000;
 143
 144         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 145                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 146                 cn10k_sso_hws_get_work_empty(ws, &ev);
 147                 if (fn != NULL && ev.u64 != 0)
 148                         fn(arg, ev);
 149                 if (ev.sched_type != SSO_TT_EMPTY)
 150                         cnxk_sso_hws_swtag_flush(
 151                                 ws->base + SSOW_LF_GWS_WQE0,
 152                                 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
 153                 do {
 154                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 155                 } while (val & BIT_ULL(56));
 156                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 157                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 158                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 159                 /* Extract cq and ds count */
 160                 cq_ds_cnt &= 0x3FFF3FFF0000;
 161         }
 162
 163         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 164         rte_mb();
 165 }
 166
 167 static void
 168 cn10k_sso_hws_reset(void *arg, void *hws)
 169 {
 170         struct cnxk_sso_evdev *dev = arg;
 171         struct cn10k_sso_hws *ws = hws;
 172         uintptr_t base = ws->base;
 173         uint64_t pend_state;
 174         union {
 175                 __uint128_t wdata;
 176                 uint64_t u64[2];
 177         } gw;
 178         uint8_t pend_tt;
 179
 180         /* Wait till getwork/swtp/waitw/desched completes. */
 181         do {
 182                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 183         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 184                                BIT_ULL(56) | BIT_ULL(54)));
 185         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 186         if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 187                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 188                         cnxk_sso_hws_swtag_untag(base +
 189                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 190                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 191         }
 192
 193         /* Wait for desched to complete. */
 194         do {
 195                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 196         } while (pend_state & BIT_ULL(58));
 197
 198         switch (dev->gw_mode) {
 199         case CN10K_GW_MODE_PREF:
 200                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 201                         ;
 202                 break;
 203         case CN10K_GW_MODE_PREF_WFE:
 204                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
 205                        SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
 206                         continue;
 207                 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 208                 break;
 209         case CN10K_GW_MODE_NONE:
 210         default:
 211                 break;
 212         }
 213
 214         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 215             SSO_TT_EMPTY) {
 216                 plt_write64(BIT_ULL(16) | 1,
 217                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 218                 do {
 219                         roc_load_pair(gw.u64[0], gw.u64[1],
 220                                       ws->base + SSOW_LF_GWS_WQE0);
 221                 } while (gw.u64[0] & BIT_ULL(63));
 222                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 223                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 224                         if (pend_tt == SSO_TT_ATOMIC ||
 225                             pend_tt == SSO_TT_ORDERED)
 226                                 cnxk_sso_hws_swtag_untag(
 227                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 228                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 229                 }
 230         }
 231
 232         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 233         rte_mb();
 234 }
 235
 236 static void
 237 cn10k_sso_set_rsrc(void *arg)
 238 {
 239         struct cnxk_sso_evdev *dev = arg;
 240
 241         dev->max_event_ports = dev->sso.max_hws;
 242         dev->max_event_queues =
 243                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 244                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 245                               dev->sso.max_hwgrp;
 246 }
 247
 248 static int
 249 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 250 {
 251         struct cnxk_sso_evdev *dev = arg;
 252
 253         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 254 }
 255
 256 static int
 257 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 258 {
 259         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 260         int i;
 261
 262         if (dev->tx_adptr_data == NULL)
 263                 return 0;
 264
 265         for (i = 0; i < dev->nb_event_ports; i++) {
 266                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 267                 void *ws_cookie;
 268
 269                 ws_cookie = cnxk_sso_hws_get_cookie(ws);
 270                 ws_cookie = rte_realloc_socket(
 271                         ws_cookie,
 272                         sizeof(struct cnxk_sso_hws_cookie) +
 273                                 sizeof(struct cn10k_sso_hws) +
 274                                 (sizeof(uint64_t) * (dev->max_port_id + 1) *
 275                                  RTE_MAX_QUEUES_PER_PORT),
 276                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 277                 if (ws_cookie == NULL)
 278                         return -ENOMEM;
 279                 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
 280                 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 281                        sizeof(uint64_t) * (dev->max_port_id + 1) *
 282                                RTE_MAX_QUEUES_PER_PORT);
 283                 event_dev->data->ports[i] = ws;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static void
 290 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 291 {
 292         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 293         const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {
 294 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                            \
 295         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,
 296                 NIX_RX_FASTPATH_MODES
 297 #undef R
 298         };
 299
 300         const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {
 301 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 302         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,
 303                 NIX_RX_FASTPATH_MODES
 304 #undef R
 305         };
 306
 307         const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {
 308 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 309         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,
 310                 NIX_RX_FASTPATH_MODES
 311 #undef R
 312         };
 313
 314         const event_dequeue_burst_t
 315                 sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {
 316 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 317         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,
 318                 NIX_RX_FASTPATH_MODES
 319 #undef R
 320         };
 321
 322         const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {
 323 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 324         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,
 325                 NIX_RX_FASTPATH_MODES
 326 #undef R
 327         };
 328
 329         const event_dequeue_burst_t
 330                 sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {
 331 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 332         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,
 333                 NIX_RX_FASTPATH_MODES
 334 #undef R
 335         };
 336
 337         const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {
 338 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 339         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
 340                 NIX_RX_FASTPATH_MODES
 341 #undef R
 342         };
 343
 344         const event_dequeue_burst_t
 345                 sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {
 346 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 347         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,
 348                 NIX_RX_FASTPATH_MODES
 349 #undef R
 350         };
 351
 352         const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {
 353 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 354         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,
 355                 NIX_RX_FASTPATH_MODES
 356 #undef R
 357         };
 358
 359         const event_dequeue_burst_t
 360                 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
 361 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 362         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 363                         NIX_RX_FASTPATH_MODES
 364 #undef R
 365                 };
 366
 367         const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {
 368 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 369         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,
 370                 NIX_RX_FASTPATH_MODES
 371 #undef R
 372         };
 373
 374         const event_dequeue_burst_t
 375                 sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
 376 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 377         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,
 378                         NIX_RX_FASTPATH_MODES
 379 #undef R
 380         };
 381
 382         /* Tx modes */
 383         const event_tx_adapter_enqueue_t
 384                 sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
 385 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
 386         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
 387                         NIX_TX_FASTPATH_MODES
 388 #undef T
 389                 };
 390
 391         const event_tx_adapter_enqueue_t
 392                 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 393 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
 394         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
 395                         NIX_TX_FASTPATH_MODES
 396 #undef T
 397                 };
 398
 399         event_dev->enqueue = cn10k_sso_hws_enq;
 400         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 401         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 402         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 403         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 404                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 405                                        sso_hws_deq_seg);
 406                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 407                                        sso_hws_deq_seg_burst);
 408                 if (dev->is_timeout_deq) {
 409                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 410                                                sso_hws_deq_tmo_seg);
 411                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 412                                                sso_hws_deq_tmo_seg_burst);
 413                 }
 414                 if (dev->is_ca_internal_port) {
 415                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 416                                                sso_hws_deq_ca_seg);
 417                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 418                                                sso_hws_deq_ca_seg_burst);
 419                 }
 420         } else {
 421                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
 422                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 423                                        sso_hws_deq_burst);
 424                 if (dev->is_timeout_deq) {
 425                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 426                                                sso_hws_deq_tmo);
 427                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 428                                                sso_hws_deq_tmo_burst);
 429                 }
 430                 if (dev->is_ca_internal_port) {
 431                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 432                                                sso_hws_deq_ca);
 433                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 434                                                sso_hws_deq_ca_burst);
 435                 }
 436         }
 437         event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 438
 439         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
 440                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 441                                        sso_hws_tx_adptr_enq_seg);
 442         else
 443                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 444                                        sso_hws_tx_adptr_enq);
 445
 446         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 447 }
 448
 449 static void
 450 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 451                    struct rte_event_dev_info *dev_info)
 452 {
 453         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 454
 455         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 456         cnxk_sso_info_get(dev, dev_info);
 457 }
 458
 459 static int
 460 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 461 {
 462         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 463         int rc;
 464
 465         rc = cnxk_sso_dev_validate(event_dev);
 466         if (rc < 0) {
 467                 plt_err("Invalid event device configuration");
 468                 return -EINVAL;
 469         }
 470
 471         roc_sso_rsrc_fini(&dev->sso);
 472
 473         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 474                                  dev->nb_event_queues);
 475         if (rc < 0) {
 476                 plt_err("Failed to initialize SSO resources");
 477                 return -ENODEV;
 478         }
 479
 480         rc = cnxk_sso_xaq_allocate(dev);
 481         if (rc < 0)
 482                 goto cnxk_rsrc_fini;
 483
 484         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 485                                     cn10k_sso_hws_setup);
 486         if (rc < 0)
 487                 goto cnxk_rsrc_fini;
 488
 489         /* Restore any prior port-queue mapping. */
 490         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 491
 492         dev->configured = 1;
 493         rte_mb();
 494
 495         return 0;
 496 cnxk_rsrc_fini:
 497         roc_sso_rsrc_fini(&dev->sso);
 498         dev->nb_event_ports = 0;
 499         return rc;
 500 }
 501
 502 static int
 503 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 504                      const struct rte_event_port_conf *port_conf)
 505 {
 506
 507         RTE_SET_USED(port_conf);
 508         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 509 }
 510
 511 static void
 512 cn10k_sso_port_release(void *port)
 513 {
 514         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 515         struct cnxk_sso_evdev *dev;
 516
 517         if (port == NULL)
 518                 return;
 519
 520         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 521         if (!gws_cookie->configured)
 522                 goto free;
 523
 524         cn10k_sso_hws_release(dev, port);
 525         memset(gws_cookie, 0, sizeof(*gws_cookie));
 526 free:
 527         rte_free(gws_cookie);
 528 }
 529
 530 static int
 531 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 532                     const uint8_t queues[], const uint8_t priorities[],
 533                     uint16_t nb_links)
 534 {
 535         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 536         uint16_t hwgrp_ids[nb_links];
 537         uint16_t link;
 538
 539         RTE_SET_USED(priorities);
 540         for (link = 0; link < nb_links; link++)
 541                 hwgrp_ids[link] = queues[link];
 542         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 543
 544         return (int)nb_links;
 545 }
 546
 547 static int
 548 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 549                       uint8_t queues[], uint16_t nb_unlinks)
 550 {
 551         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 552         uint16_t hwgrp_ids[nb_unlinks];
 553         uint16_t unlink;
 554
 555         for (unlink = 0; unlink < nb_unlinks; unlink++)
 556                 hwgrp_ids[unlink] = queues[unlink];
 557         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 558
 559         return (int)nb_unlinks;
 560 }
 561
 562 static int
 563 cn10k_sso_start(struct rte_eventdev *event_dev)
 564 {
 565         int rc;
 566
 567         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 568         if (rc < 0)
 569                 return rc;
 570
 571         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 572                             cn10k_sso_hws_flush_events);
 573         if (rc < 0)
 574                 return rc;
 575         cn10k_sso_fp_fns_set(event_dev);
 576
 577         return rc;
 578 }
 579
 580 static void
 581 cn10k_sso_stop(struct rte_eventdev *event_dev)
 582 {
 583         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 584                       cn10k_sso_hws_flush_events);
 585 }
 586
 587 static int
 588 cn10k_sso_close(struct rte_eventdev *event_dev)
 589 {
 590         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 591 }
 592
 593 static int
 594 cn10k_sso_selftest(void)
 595 {
 596         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 597 }
 598
 599 static int
 600 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 601                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 602 {
 603         int rc;
 604
 605         RTE_SET_USED(event_dev);
 606         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 607         if (rc)
 608                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 609         else
 610                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 611                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 612                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
 613                         RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
 614
 615         return 0;
 616 }
 617
 618 static void
 619 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 620                        void *tstmp_info)
 621 {
 622         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 623         int i;
 624
 625         for (i = 0; i < dev->nb_event_ports; i++) {
 626                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 627                 ws->lookup_mem = lookup_mem;
 628                 ws->tstamp = tstmp_info;
 629         }
 630 }
 631
 632 static int
 633 cn10k_sso_rx_adapter_queue_add(
 634         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 635         int32_t rx_queue_id,
 636         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 637 {
 638         struct cn10k_eth_rxq *rxq;
 639         void *lookup_mem;
 640         void *tstmp_info;
 641         int rc;
 642
 643         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 644         if (rc)
 645                 return -EINVAL;
 646
 647         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 648                                            queue_conf);
 649         if (rc)
 650                 return -EINVAL;
 651         rxq = eth_dev->data->rx_queues[0];
 652         lookup_mem = rxq->lookup_mem;
 653         tstmp_info = rxq->tstamp;
 654         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 655         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 656
 657         return 0;
 658 }
 659
 660 static int
 661 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 662                                const struct rte_eth_dev *eth_dev,
 663                                int32_t rx_queue_id)
 664 {
 665         int rc;
 666
 667         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 668         if (rc)
 669                 return -EINVAL;
 670
 671         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 672 }
 673
 674 static int
 675 cn10k_sso_rx_adapter_vector_limits(
 676         const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
 677         struct rte_event_eth_rx_adapter_vector_limits *limits)
 678 {
 679         struct cnxk_eth_dev *cnxk_eth_dev;
 680         int ret;
 681
 682         RTE_SET_USED(dev);
 683         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 684         if (ret)
 685                 return -ENOTSUP;
 686
 687         cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
 688         limits->log2_sz = true;
 689         limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
 690         limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
 691         limits->min_timeout_ns =
 692                 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
 693         limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
 694
 695         return 0;
 696 }
 697
 698 static int
 699 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 700                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 701 {
 702         int ret;
 703
 704         RTE_SET_USED(dev);
 705         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 706         if (ret)
 707                 *caps = 0;
 708         else
 709                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
 710                         RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
 711
 712         return 0;
 713 }
 714
 715 static int
 716 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
 717                                const struct rte_eth_dev *eth_dev,
 718                                int32_t tx_queue_id)
 719 {
 720         int rc;
 721
 722         RTE_SET_USED(id);
 723         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
 724         if (rc < 0)
 725                 return rc;
 726         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 727         if (rc < 0)
 728                 return rc;
 729         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 730
 731         return 0;
 732 }
 733
 734 static int
 735 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
 736                                const struct rte_eth_dev *eth_dev,
 737                                int32_t tx_queue_id)
 738 {
 739         int rc;
 740
 741         RTE_SET_USED(id);
 742         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
 743         if (rc < 0)
 744                 return rc;
 745         return cn10k_sso_updt_tx_adptr_data(event_dev);
 746 }
 747
 748 static int
 749 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
 750                               const struct rte_cryptodev *cdev, uint32_t *caps)
 751 {
 752         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 753         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 754
 755         *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
 756                 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 757
 758         return 0;
 759 }
 760
 761 static int
 762 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
 763                             const struct rte_cryptodev *cdev,
 764                             int32_t queue_pair_id,
 765                             const struct rte_event *event)
 766 {
 767         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 768
 769         RTE_SET_USED(event);
 770
 771         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 772         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 773
 774         dev->is_ca_internal_port = 1;
 775         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 776
 777         return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
 778 }
 779
 780 static int
 781 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
 782                             const struct rte_cryptodev *cdev,
 783                             int32_t queue_pair_id)
 784 {
 785         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 786         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 787
 788         return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 789 }
 790
 791 static struct eventdev_ops cn10k_sso_dev_ops = {
 792         .dev_infos_get = cn10k_sso_info_get,
 793         .dev_configure = cn10k_sso_dev_configure,
 794         .queue_def_conf = cnxk_sso_queue_def_conf,
 795         .queue_setup = cnxk_sso_queue_setup,
 796         .queue_release = cnxk_sso_queue_release,
 797         .port_def_conf = cnxk_sso_port_def_conf,
 798         .port_setup = cn10k_sso_port_setup,
 799         .port_release = cn10k_sso_port_release,
 800         .port_link = cn10k_sso_port_link,
 801         .port_unlink = cn10k_sso_port_unlink,
 802         .timeout_ticks = cnxk_sso_timeout_ticks,
 803
 804         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 805         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 806         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 807         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 808         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 809
 810         .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
 811
 812         .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
 813         .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
 814         .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
 815
 816         .timer_adapter_caps_get = cnxk_tim_caps_get,
 817
 818         .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
 819         .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
 820         .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
 821
 822         .dump = cnxk_sso_dump,
 823         .dev_start = cn10k_sso_start,
 824         .dev_stop = cn10k_sso_stop,
 825         .dev_close = cn10k_sso_close,
 826         .dev_selftest = cn10k_sso_selftest,
 827 };
 828
 829 static int
 830 cn10k_sso_init(struct rte_eventdev *event_dev)
 831 {
 832         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 833         int rc;
 834
 835         if (RTE_CACHE_LINE_SIZE != 64) {
 836                 plt_err("Driver not compiled for CN10K");
 837                 return -EFAULT;
 838         }
 839
 840         rc = roc_plt_init();
 841         if (rc < 0) {
 842                 plt_err("Failed to initialize platform model");
 843                 return rc;
 844         }
 845
 846         event_dev->dev_ops = &cn10k_sso_dev_ops;
 847         /* For secondary processes, the primary has done all the work */
 848         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 849                 cn10k_sso_fp_fns_set(event_dev);
 850                 return 0;
 851         }
 852
 853         rc = cnxk_sso_init(event_dev);
 854         if (rc < 0)
 855                 return rc;
 856
 857         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 858         if (!dev->max_event_ports || !dev->max_event_queues) {
 859                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 860                         dev->max_event_queues, dev->max_event_ports);
 861                 cnxk_sso_fini(event_dev);
 862                 return -ENODEV;
 863         }
 864
 865         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 866                     event_dev->data->name, dev->max_event_queues,
 867                     dev->max_event_ports);
 868
 869         return 0;
 870 }
 871
 872 static int
 873 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 874 {
 875         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 876                                        sizeof(struct cnxk_sso_evdev),
 877                                        cn10k_sso_init);
 878 }
 879
 880 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 881         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 882         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 883         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 884         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 885         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 886         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 887         {
 888                 .vendor_id = 0,
 889         },
 890 };
 891
 892 static struct rte_pci_driver cn10k_pci_sso = {
 893         .id_table = cn10k_pci_sso_map,
 894         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 895         .probe = cn10k_sso_probe,
 896         .remove = cnxk_sso_remove,
 897 };
 898
 899 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 900 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 901 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 902 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 903                               CNXK_SSO_GGRP_QOS "=<string>"
 904                               CNXK_SSO_FORCE_BP "=1"
 905                               CN10K_SSO_GW_MODE "=<int>"
 906                               CNXK_TIM_DISABLE_NPA "=1"
 907                               CNXK_TIM_CHNK_SLOTS "=<int>"
 908                               CNXK_TIM_RINGS_LMT "=<int>"
 909                               CNXK_TIM_STATS_ENA "=1");