drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cnxk_eventdev.h"
   6
   7 static void
   8 cn10k_init_hws_ops(struct cn10k_sso_hws *ws, uintptr_t base)
   9 {
  10         ws->tag_wqe_op = base + SSOW_LF_GWS_WQE0;
  11         ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0;
  12         ws->updt_wqe_op = base + SSOW_LF_GWS_OP_UPD_WQP_GRP1;
  13         ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
  14         ws->swtag_untag_op = base + SSOW_LF_GWS_OP_SWTAG_UNTAG;
  15         ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;
  16         ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
  17 }
  18
  19 static uint32_t
  20 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  21 {
  22         uint32_t wdata = BIT(16) | 1;
  23
  24         switch (dev->gw_mode) {
  25         case CN10K_GW_MODE_NONE:
  26         default:
  27                 break;
  28         case CN10K_GW_MODE_PREF:
  29                 wdata |= BIT(19);
  30                 break;
  31         case CN10K_GW_MODE_PREF_WFE:
  32                 wdata |= BIT(20) | BIT(19);
  33                 break;
  34         }
  35
  36         return wdata;
  37 }
  38
  39 static void *
  40 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  41 {
  42         struct cnxk_sso_evdev *dev = arg;
  43         struct cn10k_sso_hws *ws;
  44
  45         /* Allocate event port memory */
  46         ws = rte_zmalloc("cn10k_ws",
  47                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  48                          RTE_CACHE_LINE_SIZE);
  49         if (ws == NULL) {
  50                 plt_err("Failed to alloc memory for port=%d", port_id);
  51                 return NULL;
  52         }
  53
  54         /* First cache line is reserved for cookie */
  55         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  56         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  57         cn10k_init_hws_ops(ws, ws->base);
  58         ws->hws_id = port_id;
  59         ws->swtag_req = 0;
  60         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  61         ws->lmt_base = dev->sso.lmt_base;
  62
  63         return ws;
  64 }
  65
  66 static void
  67 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
  68 {
  69         struct cnxk_sso_evdev *dev = arg;
  70         struct cn10k_sso_hws *ws = hws;
  71         uint64_t val;
  72
  73         rte_memcpy(ws->grps_base, grps_base,
  74                    sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
  75         ws->fc_mem = dev->fc_mem;
  76         ws->xaq_lmt = dev->xaq_lmt;
  77
  78         /* Set get_work timeout for HWS */
  79         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
  80         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  81 }
  82
  83 static void
  84 cn10k_sso_hws_release(void *arg, void *hws)
  85 {
  86         struct cn10k_sso_hws *ws = hws;
  87
  88         RTE_SET_USED(arg);
  89         memset(ws, 0, sizeof(*ws));
  90 }
  91
  92 static void
  93 cn10k_sso_set_rsrc(void *arg)
  94 {
  95         struct cnxk_sso_evdev *dev = arg;
  96
  97         dev->max_event_ports = dev->sso.max_hws;
  98         dev->max_event_queues =
  99                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 100                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 101                               dev->sso.max_hwgrp;
 102 }
 103
 104 static int
 105 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 106 {
 107         struct cnxk_sso_evdev *dev = arg;
 108
 109         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 110 }
 111
 112 static void
 113 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 114                    struct rte_event_dev_info *dev_info)
 115 {
 116         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 117
 118         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 119         cnxk_sso_info_get(dev, dev_info);
 120 }
 121
 122 static int
 123 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 124 {
 125         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 126         int rc;
 127
 128         rc = cnxk_sso_dev_validate(event_dev);
 129         if (rc < 0) {
 130                 plt_err("Invalid event device configuration");
 131                 return -EINVAL;
 132         }
 133
 134         roc_sso_rsrc_fini(&dev->sso);
 135
 136         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 137                                  dev->nb_event_queues);
 138         if (rc < 0) {
 139                 plt_err("Failed to initialize SSO resources");
 140                 return -ENODEV;
 141         }
 142
 143         rc = cnxk_sso_xaq_allocate(dev);
 144         if (rc < 0)
 145                 goto cnxk_rsrc_fini;
 146
 147         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 148                                     cn10k_sso_hws_setup);
 149         if (rc < 0)
 150                 goto cnxk_rsrc_fini;
 151
 152         return 0;
 153 cnxk_rsrc_fini:
 154         roc_sso_rsrc_fini(&dev->sso);
 155         dev->nb_event_ports = 0;
 156         return rc;
 157 }
 158
 159 static int
 160 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 161                      const struct rte_event_port_conf *port_conf)
 162 {
 163
 164         RTE_SET_USED(port_conf);
 165         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 166 }
 167
 168 static void
 169 cn10k_sso_port_release(void *port)
 170 {
 171         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 172         struct cnxk_sso_evdev *dev;
 173
 174         if (port == NULL)
 175                 return;
 176
 177         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 178         if (!gws_cookie->configured)
 179                 goto free;
 180
 181         cn10k_sso_hws_release(dev, port);
 182         memset(gws_cookie, 0, sizeof(*gws_cookie));
 183 free:
 184         rte_free(gws_cookie);
 185 }
 186
 187 static struct rte_eventdev_ops cn10k_sso_dev_ops = {
 188         .dev_infos_get = cn10k_sso_info_get,
 189         .dev_configure = cn10k_sso_dev_configure,
 190         .queue_def_conf = cnxk_sso_queue_def_conf,
 191         .queue_setup = cnxk_sso_queue_setup,
 192         .queue_release = cnxk_sso_queue_release,
 193         .port_def_conf = cnxk_sso_port_def_conf,
 194         .port_setup = cn10k_sso_port_setup,
 195         .port_release = cn10k_sso_port_release,
 196 };
 197
 198 static int
 199 cn10k_sso_init(struct rte_eventdev *event_dev)
 200 {
 201         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 202         int rc;
 203
 204         if (RTE_CACHE_LINE_SIZE != 64) {
 205                 plt_err("Driver not compiled for CN9K");
 206                 return -EFAULT;
 207         }
 208
 209         rc = roc_plt_init();
 210         if (rc < 0) {
 211                 plt_err("Failed to initialize platform model");
 212                 return rc;
 213         }
 214
 215         event_dev->dev_ops = &cn10k_sso_dev_ops;
 216         /* For secondary processes, the primary has done all the work */
 217         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 218                 return 0;
 219
 220         rc = cnxk_sso_init(event_dev);
 221         if (rc < 0)
 222                 return rc;
 223
 224         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 225         if (!dev->max_event_ports || !dev->max_event_queues) {
 226                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 227                         dev->max_event_queues, dev->max_event_ports);
 228                 cnxk_sso_fini(event_dev);
 229                 return -ENODEV;
 230         }
 231
 232         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 233                     event_dev->data->name, dev->max_event_queues,
 234                     dev->max_event_ports);
 235
 236         return 0;
 237 }
 238
 239 static int
 240 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 241 {
 242         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 243                                        sizeof(struct cnxk_sso_evdev),
 244                                        cn10k_sso_init);
 245 }
 246
 247 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 248         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 249         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 250         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 251         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 252         {
 253                 .vendor_id = 0,
 254         },
 255 };
 256
 257 static struct rte_pci_driver cn10k_pci_sso = {
 258         .id_table = cn10k_pci_sso_map,
 259         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 260         .probe = cn10k_sso_probe,
 261         .remove = cnxk_sso_remove,
 262 };
 263
 264 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 265 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 266 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 267 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 268                               CNXK_SSO_GGRP_QOS "=<string>");