drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                           \
  10         (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]    \
  11                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]  \
  12                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]      \
  13                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
  14                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]    \
  15                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]       \
  16                          [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
  17
  18 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                           \
  19         (enq_op =                                                              \
  20                  enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]     \
  21                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]       \
  22                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]          \
  23                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]    \
  24                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]    \
  25                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
  26                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
  27
  28 static uint32_t
  29 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  30 {
  31         uint32_t wdata = BIT(16) | 1;
  32
  33         switch (dev->gw_mode) {
  34         case CN10K_GW_MODE_NONE:
  35         default:
  36                 break;
  37         case CN10K_GW_MODE_PREF:
  38                 wdata |= BIT(19);
  39                 break;
  40         case CN10K_GW_MODE_PREF_WFE:
  41                 wdata |= BIT(20) | BIT(19);
  42                 break;
  43         }
  44
  45         return wdata;
  46 }
  47
  48 static void *
  49 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  50 {
  51         struct cnxk_sso_evdev *dev = arg;
  52         struct cn10k_sso_hws *ws;
  53
  54         /* Allocate event port memory */
  55         ws = rte_zmalloc("cn10k_ws",
  56                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  57                          RTE_CACHE_LINE_SIZE);
  58         if (ws == NULL) {
  59                 plt_err("Failed to alloc memory for port=%d", port_id);
  60                 return NULL;
  61         }
  62
  63         /* First cache line is reserved for cookie */
  64         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  65         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  66         ws->tx_base = ws->base;
  67         ws->hws_id = port_id;
  68         ws->swtag_req = 0;
  69         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  70         ws->lmt_base = dev->sso.lmt_base;
  71
  72         return ws;
  73 }
  74
  75 static int
  76 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  77 {
  78         struct cnxk_sso_evdev *dev = arg;
  79         struct cn10k_sso_hws *ws = port;
  80
  81         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  82 }
  83
  84 static int
  85 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  86 {
  87         struct cnxk_sso_evdev *dev = arg;
  88         struct cn10k_sso_hws *ws = port;
  89
  90         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  91 }
  92
  93 static void
  94 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
  95 {
  96         struct cnxk_sso_evdev *dev = arg;
  97         struct cn10k_sso_hws *ws = hws;
  98         uint64_t val;
  99
 100         rte_memcpy(ws->grps_base, grps_base,
 101                    sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
 102         ws->fc_mem = dev->fc_mem;
 103         ws->xaq_lmt = dev->xaq_lmt;
 104
 105         /* Set get_work timeout for HWS */
 106         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
 107         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
 108 }
 109
 110 static void
 111 cn10k_sso_hws_release(void *arg, void *hws)
 112 {
 113         struct cnxk_sso_evdev *dev = arg;
 114         struct cn10k_sso_hws *ws = hws;
 115         int i;
 116
 117         for (i = 0; i < dev->nb_event_queues; i++)
 118                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
 119         memset(ws, 0, sizeof(*ws));
 120 }
 121
 122 static void
 123 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 124                            cnxk_handle_event_t fn, void *arg)
 125 {
 126         struct cn10k_sso_hws *ws = hws;
 127         uint64_t cq_ds_cnt = 1;
 128         uint64_t aq_cnt = 1;
 129         uint64_t ds_cnt = 1;
 130         struct rte_event ev;
 131         uint64_t val, req;
 132
 133         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 134
 135         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 136         req = queue_id;     /* GGRP ID */
 137         req |= BIT_ULL(18); /* Grouped */
 138         req |= BIT_ULL(16); /* WAIT */
 139
 140         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 141         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 142         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 143         cq_ds_cnt &= 0x3FFF3FFF0000;
 144
 145         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 146                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 147                 cn10k_sso_hws_get_work_empty(ws, &ev);
 148                 if (fn != NULL && ev.u64 != 0)
 149                         fn(arg, ev);
 150                 if (ev.sched_type != SSO_TT_EMPTY)
 151                         cnxk_sso_hws_swtag_flush(
 152                                 ws->base + SSOW_LF_GWS_WQE0,
 153                                 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
 154                 do {
 155                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 156                 } while (val & BIT_ULL(56));
 157                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 158                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 159                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 160                 /* Extract cq and ds count */
 161                 cq_ds_cnt &= 0x3FFF3FFF0000;
 162         }
 163
 164         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 165         rte_mb();
 166 }
 167
 168 static void
 169 cn10k_sso_hws_reset(void *arg, void *hws)
 170 {
 171         struct cnxk_sso_evdev *dev = arg;
 172         struct cn10k_sso_hws *ws = hws;
 173         uintptr_t base = ws->base;
 174         uint64_t pend_state;
 175         union {
 176                 __uint128_t wdata;
 177                 uint64_t u64[2];
 178         } gw;
 179         uint8_t pend_tt;
 180
 181         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 182         /* Wait till getwork/swtp/waitw/desched completes. */
 183         do {
 184                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 185         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 186                                BIT_ULL(56) | BIT_ULL(54)));
 187         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 188         if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 189                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 190                         cnxk_sso_hws_swtag_untag(base +
 191                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 192                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 193         }
 194
 195         /* Wait for desched to complete. */
 196         do {
 197                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 198         } while (pend_state & BIT_ULL(58));
 199
 200         switch (dev->gw_mode) {
 201         case CN10K_GW_MODE_PREF:
 202                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 203                         ;
 204                 break;
 205         case CN10K_GW_MODE_PREF_WFE:
 206                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
 207                        SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
 208                         continue;
 209                 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 210                 break;
 211         case CN10K_GW_MODE_NONE:
 212         default:
 213                 break;
 214         }
 215
 216         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 217             SSO_TT_EMPTY) {
 218                 plt_write64(BIT_ULL(16) | 1,
 219                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 220                 do {
 221                         roc_load_pair(gw.u64[0], gw.u64[1],
 222                                       ws->base + SSOW_LF_GWS_WQE0);
 223                 } while (gw.u64[0] & BIT_ULL(63));
 224                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 225                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 226                         if (pend_tt == SSO_TT_ATOMIC ||
 227                             pend_tt == SSO_TT_ORDERED)
 228                                 cnxk_sso_hws_swtag_untag(
 229                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 230                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 231                 }
 232         }
 233
 234         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 235         rte_mb();
 236 }
 237
 238 static void
 239 cn10k_sso_set_rsrc(void *arg)
 240 {
 241         struct cnxk_sso_evdev *dev = arg;
 242
 243         dev->max_event_ports = dev->sso.max_hws;
 244         dev->max_event_queues =
 245                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 246                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 247                               dev->sso.max_hwgrp;
 248 }
 249
 250 static int
 251 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 252 {
 253         struct cnxk_sso_evdev *dev = arg;
 254
 255         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 256 }
 257
 258 static int
 259 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 260 {
 261         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 262         int i;
 263
 264         if (dev->tx_adptr_data == NULL)
 265                 return 0;
 266
 267         for (i = 0; i < dev->nb_event_ports; i++) {
 268                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 269                 void *ws_cookie;
 270
 271                 ws_cookie = cnxk_sso_hws_get_cookie(ws);
 272                 ws_cookie = rte_realloc_socket(
 273                         ws_cookie,
 274                         sizeof(struct cnxk_sso_hws_cookie) +
 275                                 sizeof(struct cn10k_sso_hws) +
 276                                 (sizeof(uint64_t) * (dev->max_port_id + 1) *
 277                                  RTE_MAX_QUEUES_PER_PORT),
 278                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 279                 if (ws_cookie == NULL)
 280                         return -ENOMEM;
 281                 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
 282                 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 283                        sizeof(uint64_t) * (dev->max_port_id + 1) *
 284                                RTE_MAX_QUEUES_PER_PORT);
 285                 event_dev->data->ports[i] = ws;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static void
 292 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 293 {
 294         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 295         const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {
 296 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                            \
 297         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,
 298                 NIX_RX_FASTPATH_MODES
 299 #undef R
 300         };
 301
 302         const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {
 303 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 304         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,
 305                 NIX_RX_FASTPATH_MODES
 306 #undef R
 307         };
 308
 309         const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {
 310 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 311         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,
 312                 NIX_RX_FASTPATH_MODES
 313 #undef R
 314         };
 315
 316         const event_dequeue_burst_t
 317                 sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {
 318 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 319         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,
 320                 NIX_RX_FASTPATH_MODES
 321 #undef R
 322         };
 323
 324         const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {
 325 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 326         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,
 327                 NIX_RX_FASTPATH_MODES
 328 #undef R
 329         };
 330
 331         const event_dequeue_burst_t
 332                 sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {
 333 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 334         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,
 335                 NIX_RX_FASTPATH_MODES
 336 #undef R
 337         };
 338
 339         const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {
 340 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 341         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
 342                 NIX_RX_FASTPATH_MODES
 343 #undef R
 344         };
 345
 346         const event_dequeue_burst_t
 347                 sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {
 348 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 349         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,
 350                 NIX_RX_FASTPATH_MODES
 351 #undef R
 352         };
 353
 354         const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {
 355 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 356         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,
 357                 NIX_RX_FASTPATH_MODES
 358 #undef R
 359         };
 360
 361         const event_dequeue_burst_t
 362                 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
 363 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 364         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 365                         NIX_RX_FASTPATH_MODES
 366 #undef R
 367                 };
 368
 369         const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {
 370 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 371         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,
 372                 NIX_RX_FASTPATH_MODES
 373 #undef R
 374         };
 375
 376         const event_dequeue_burst_t
 377                 sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
 378 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 379         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,
 380                         NIX_RX_FASTPATH_MODES
 381 #undef R
 382         };
 383
 384         /* Tx modes */
 385         const event_tx_adapter_enqueue_t
 386                 sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
 387 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
 388         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
 389                         NIX_TX_FASTPATH_MODES
 390 #undef T
 391                 };
 392
 393         const event_tx_adapter_enqueue_t
 394                 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 395 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
 396         [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
 397                         NIX_TX_FASTPATH_MODES
 398 #undef T
 399                 };
 400
 401         event_dev->enqueue = cn10k_sso_hws_enq;
 402         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 403         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 404         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 405         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 406                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 407                                        sso_hws_deq_seg);
 408                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 409                                        sso_hws_deq_seg_burst);
 410                 if (dev->is_timeout_deq) {
 411                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 412                                                sso_hws_deq_tmo_seg);
 413                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 414                                                sso_hws_deq_tmo_seg_burst);
 415                 }
 416                 if (dev->is_ca_internal_port) {
 417                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 418                                                sso_hws_deq_ca_seg);
 419                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 420                                                sso_hws_deq_ca_seg_burst);
 421                 }
 422         } else {
 423                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
 424                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 425                                        sso_hws_deq_burst);
 426                 if (dev->is_timeout_deq) {
 427                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 428                                                sso_hws_deq_tmo);
 429                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 430                                                sso_hws_deq_tmo_burst);
 431                 }
 432                 if (dev->is_ca_internal_port) {
 433                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 434                                                sso_hws_deq_ca);
 435                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 436                                                sso_hws_deq_ca_burst);
 437                 }
 438         }
 439         event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 440
 441         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
 442                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 443                                        sso_hws_tx_adptr_enq_seg);
 444         else
 445                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 446                                        sso_hws_tx_adptr_enq);
 447
 448         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 449 }
 450
 451 static void
 452 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 453                    struct rte_event_dev_info *dev_info)
 454 {
 455         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 456
 457         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 458         cnxk_sso_info_get(dev, dev_info);
 459 }
 460
 461 static int
 462 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 463 {
 464         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 465         int rc;
 466
 467         rc = cnxk_sso_dev_validate(event_dev);
 468         if (rc < 0) {
 469                 plt_err("Invalid event device configuration");
 470                 return -EINVAL;
 471         }
 472
 473         roc_sso_rsrc_fini(&dev->sso);
 474
 475         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 476                                  dev->nb_event_queues);
 477         if (rc < 0) {
 478                 plt_err("Failed to initialize SSO resources");
 479                 return -ENODEV;
 480         }
 481
 482         rc = cnxk_sso_xaq_allocate(dev);
 483         if (rc < 0)
 484                 goto cnxk_rsrc_fini;
 485
 486         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 487                                     cn10k_sso_hws_setup);
 488         if (rc < 0)
 489                 goto cnxk_rsrc_fini;
 490
 491         /* Restore any prior port-queue mapping. */
 492         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 493
 494         dev->configured = 1;
 495         rte_mb();
 496
 497         return 0;
 498 cnxk_rsrc_fini:
 499         roc_sso_rsrc_fini(&dev->sso);
 500         dev->nb_event_ports = 0;
 501         return rc;
 502 }
 503
 504 static int
 505 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 506                      const struct rte_event_port_conf *port_conf)
 507 {
 508
 509         RTE_SET_USED(port_conf);
 510         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 511 }
 512
 513 static void
 514 cn10k_sso_port_release(void *port)
 515 {
 516         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 517         struct cnxk_sso_evdev *dev;
 518
 519         if (port == NULL)
 520                 return;
 521
 522         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 523         if (!gws_cookie->configured)
 524                 goto free;
 525
 526         cn10k_sso_hws_release(dev, port);
 527         memset(gws_cookie, 0, sizeof(*gws_cookie));
 528 free:
 529         rte_free(gws_cookie);
 530 }
 531
 532 static int
 533 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 534                     const uint8_t queues[], const uint8_t priorities[],
 535                     uint16_t nb_links)
 536 {
 537         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 538         uint16_t hwgrp_ids[nb_links];
 539         uint16_t link;
 540
 541         RTE_SET_USED(priorities);
 542         for (link = 0; link < nb_links; link++)
 543                 hwgrp_ids[link] = queues[link];
 544         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 545
 546         return (int)nb_links;
 547 }
 548
 549 static int
 550 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 551                       uint8_t queues[], uint16_t nb_unlinks)
 552 {
 553         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 554         uint16_t hwgrp_ids[nb_unlinks];
 555         uint16_t unlink;
 556
 557         for (unlink = 0; unlink < nb_unlinks; unlink++)
 558                 hwgrp_ids[unlink] = queues[unlink];
 559         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 560
 561         return (int)nb_unlinks;
 562 }
 563
 564 static int
 565 cn10k_sso_start(struct rte_eventdev *event_dev)
 566 {
 567         int rc;
 568
 569         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 570         if (rc < 0)
 571                 return rc;
 572
 573         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 574                             cn10k_sso_hws_flush_events);
 575         if (rc < 0)
 576                 return rc;
 577         cn10k_sso_fp_fns_set(event_dev);
 578
 579         return rc;
 580 }
 581
 582 static void
 583 cn10k_sso_stop(struct rte_eventdev *event_dev)
 584 {
 585         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 586                       cn10k_sso_hws_flush_events);
 587 }
 588
 589 static int
 590 cn10k_sso_close(struct rte_eventdev *event_dev)
 591 {
 592         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 593 }
 594
 595 static int
 596 cn10k_sso_selftest(void)
 597 {
 598         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 599 }
 600
 601 static int
 602 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 603                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 604 {
 605         int rc;
 606
 607         RTE_SET_USED(event_dev);
 608         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 609         if (rc)
 610                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 611         else
 612                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 613                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 614                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
 615                         RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
 616
 617         return 0;
 618 }
 619
 620 static void
 621 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 622                        void *tstmp_info)
 623 {
 624         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 625         int i;
 626
 627         for (i = 0; i < dev->nb_event_ports; i++) {
 628                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 629                 ws->lookup_mem = lookup_mem;
 630                 ws->tstamp = tstmp_info;
 631         }
 632 }
 633
 634 static int
 635 cn10k_sso_rx_adapter_queue_add(
 636         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 637         int32_t rx_queue_id,
 638         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 639 {
 640         struct cn10k_eth_rxq *rxq;
 641         void *lookup_mem;
 642         void *tstmp_info;
 643         int rc;
 644
 645         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 646         if (rc)
 647                 return -EINVAL;
 648
 649         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 650                                            queue_conf);
 651         if (rc)
 652                 return -EINVAL;
 653         rxq = eth_dev->data->rx_queues[0];
 654         lookup_mem = rxq->lookup_mem;
 655         tstmp_info = rxq->tstamp;
 656         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 657         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 658
 659         return 0;
 660 }
 661
 662 static int
 663 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 664                                const struct rte_eth_dev *eth_dev,
 665                                int32_t rx_queue_id)
 666 {
 667         int rc;
 668
 669         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 670         if (rc)
 671                 return -EINVAL;
 672
 673         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 674 }
 675
 676 static int
 677 cn10k_sso_rx_adapter_vector_limits(
 678         const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
 679         struct rte_event_eth_rx_adapter_vector_limits *limits)
 680 {
 681         struct cnxk_eth_dev *cnxk_eth_dev;
 682         int ret;
 683
 684         RTE_SET_USED(dev);
 685         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 686         if (ret)
 687                 return -ENOTSUP;
 688
 689         cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
 690         limits->log2_sz = true;
 691         limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
 692         limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
 693         limits->min_timeout_ns =
 694                 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
 695         limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
 696
 697         return 0;
 698 }
 699
 700 static int
 701 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 702                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 703 {
 704         int ret;
 705
 706         RTE_SET_USED(dev);
 707         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 708         if (ret)
 709                 *caps = 0;
 710         else
 711                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
 712                         RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
 713
 714         return 0;
 715 }
 716
 717 static int
 718 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
 719                                const struct rte_eth_dev *eth_dev,
 720                                int32_t tx_queue_id)
 721 {
 722         int rc;
 723
 724         RTE_SET_USED(id);
 725         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
 726         if (rc < 0)
 727                 return rc;
 728         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 729         if (rc < 0)
 730                 return rc;
 731         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 732
 733         return 0;
 734 }
 735
 736 static int
 737 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
 738                                const struct rte_eth_dev *eth_dev,
 739                                int32_t tx_queue_id)
 740 {
 741         int rc;
 742
 743         RTE_SET_USED(id);
 744         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
 745         if (rc < 0)
 746                 return rc;
 747         return cn10k_sso_updt_tx_adptr_data(event_dev);
 748 }
 749
 750 static int
 751 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
 752                               const struct rte_cryptodev *cdev, uint32_t *caps)
 753 {
 754         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 755         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 756
 757         *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
 758                 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 759
 760         return 0;
 761 }
 762
 763 static int
 764 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
 765                             const struct rte_cryptodev *cdev,
 766                             int32_t queue_pair_id,
 767                             const struct rte_event *event)
 768 {
 769         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 770
 771         RTE_SET_USED(event);
 772
 773         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 774         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 775
 776         dev->is_ca_internal_port = 1;
 777         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 778
 779         return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
 780 }
 781
 782 static int
 783 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
 784                             const struct rte_cryptodev *cdev,
 785                             int32_t queue_pair_id)
 786 {
 787         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 788         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 789
 790         return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 791 }
 792
 793 static struct eventdev_ops cn10k_sso_dev_ops = {
 794         .dev_infos_get = cn10k_sso_info_get,
 795         .dev_configure = cn10k_sso_dev_configure,
 796         .queue_def_conf = cnxk_sso_queue_def_conf,
 797         .queue_setup = cnxk_sso_queue_setup,
 798         .queue_release = cnxk_sso_queue_release,
 799         .port_def_conf = cnxk_sso_port_def_conf,
 800         .port_setup = cn10k_sso_port_setup,
 801         .port_release = cn10k_sso_port_release,
 802         .port_link = cn10k_sso_port_link,
 803         .port_unlink = cn10k_sso_port_unlink,
 804         .timeout_ticks = cnxk_sso_timeout_ticks,
 805
 806         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 807         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 808         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 809         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 810         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 811
 812         .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
 813
 814         .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
 815         .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
 816         .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
 817
 818         .timer_adapter_caps_get = cnxk_tim_caps_get,
 819
 820         .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
 821         .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
 822         .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
 823
 824         .dump = cnxk_sso_dump,
 825         .dev_start = cn10k_sso_start,
 826         .dev_stop = cn10k_sso_stop,
 827         .dev_close = cn10k_sso_close,
 828         .dev_selftest = cn10k_sso_selftest,
 829 };
 830
 831 static int
 832 cn10k_sso_init(struct rte_eventdev *event_dev)
 833 {
 834         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 835         int rc;
 836
 837         if (RTE_CACHE_LINE_SIZE != 64) {
 838                 plt_err("Driver not compiled for CN10K");
 839                 return -EFAULT;
 840         }
 841
 842         rc = roc_plt_init();
 843         if (rc < 0) {
 844                 plt_err("Failed to initialize platform model");
 845                 return rc;
 846         }
 847
 848         event_dev->dev_ops = &cn10k_sso_dev_ops;
 849         /* For secondary processes, the primary has done all the work */
 850         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 851                 cn10k_sso_fp_fns_set(event_dev);
 852                 return 0;
 853         }
 854
 855         rc = cnxk_sso_init(event_dev);
 856         if (rc < 0)
 857                 return rc;
 858
 859         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 860         if (!dev->max_event_ports || !dev->max_event_queues) {
 861                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 862                         dev->max_event_queues, dev->max_event_ports);
 863                 cnxk_sso_fini(event_dev);
 864                 return -ENODEV;
 865         }
 866
 867         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 868                     event_dev->data->name, dev->max_event_queues,
 869                     dev->max_event_ports);
 870
 871         return 0;
 872 }
 873
 874 static int
 875 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 876 {
 877         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 878                                        sizeof(struct cnxk_sso_evdev),
 879                                        cn10k_sso_init);
 880 }
 881
 882 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 883         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 884         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 885         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 886         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 887         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 888         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 889         {
 890                 .vendor_id = 0,
 891         },
 892 };
 893
 894 static struct rte_pci_driver cn10k_pci_sso = {
 895         .id_table = cn10k_pci_sso_map,
 896         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 897         .probe = cn10k_sso_probe,
 898         .remove = cnxk_sso_remove,
 899 };
 900
 901 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 902 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 903 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 904 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 905                               CNXK_SSO_GGRP_QOS "=<string>"
 906                               CNXK_SSO_FORCE_BP "=1"
 907                               CN10K_SSO_GW_MODE "=<int>"
 908                               CNXK_TIM_DISABLE_NPA "=1"
 909                               CNXK_TIM_CHNK_SLOTS "=<int>"
 910                               CNXK_TIM_RINGS_LMT "=<int>"
 911                               CNXK_TIM_STATS_ENA "=1");