1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn10k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
10 (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)] \
11 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \
12 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \
13 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
14 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \
15 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)] \
16 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
18 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
20 enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)] \
21 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
22 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \
23 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \
24 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \
25 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
26 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
29 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
31 uint32_t wdata = BIT(16) | 1;
33 switch (dev->gw_mode) {
34 case CN10K_GW_MODE_NONE:
37 case CN10K_GW_MODE_PREF:
40 case CN10K_GW_MODE_PREF_WFE:
41 wdata |= BIT(20) | BIT(19);
49 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
51 struct cnxk_sso_evdev *dev = arg;
52 struct cn10k_sso_hws *ws;
54 /* Allocate event port memory */
55 ws = rte_zmalloc("cn10k_ws",
56 sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
59 plt_err("Failed to alloc memory for port=%d", port_id);
63 /* First cache line is reserved for cookie */
64 ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
65 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
66 ws->tx_base = ws->base;
69 ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
70 ws->lmt_base = dev->sso.lmt_base;
76 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
78 struct cnxk_sso_evdev *dev = arg;
79 struct cn10k_sso_hws *ws = port;
81 return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
85 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
87 struct cnxk_sso_evdev *dev = arg;
88 struct cn10k_sso_hws *ws = port;
90 return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
94 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
96 struct cnxk_sso_evdev *dev = arg;
97 struct cn10k_sso_hws *ws = hws;
100 rte_memcpy(ws->grps_base, grps_base,
101 sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
102 ws->fc_mem = dev->fc_mem;
103 ws->xaq_lmt = dev->xaq_lmt;
105 /* Set get_work timeout for HWS */
106 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
107 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
111 cn10k_sso_hws_release(void *arg, void *hws)
113 struct cnxk_sso_evdev *dev = arg;
114 struct cn10k_sso_hws *ws = hws;
117 for (i = 0; i < dev->nb_event_queues; i++)
118 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
119 memset(ws, 0, sizeof(*ws));
123 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
124 cnxk_handle_event_t fn, void *arg)
126 struct cn10k_sso_hws *ws = hws;
127 uint64_t cq_ds_cnt = 1;
133 plt_write64(0, base + SSO_LF_GGRP_QCTL);
135 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
136 req = queue_id; /* GGRP ID */
137 req |= BIT_ULL(18); /* Grouped */
138 req |= BIT_ULL(16); /* WAIT */
140 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
141 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
142 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
143 cq_ds_cnt &= 0x3FFF3FFF0000;
145 while (aq_cnt || cq_ds_cnt || ds_cnt) {
146 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
147 cn10k_sso_hws_get_work_empty(ws, &ev);
148 if (fn != NULL && ev.u64 != 0)
150 if (ev.sched_type != SSO_TT_EMPTY)
151 cnxk_sso_hws_swtag_flush(
152 ws->base + SSOW_LF_GWS_WQE0,
153 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
155 val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
156 } while (val & BIT_ULL(56));
157 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
158 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
159 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
160 /* Extract cq and ds count */
161 cq_ds_cnt &= 0x3FFF3FFF0000;
164 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
169 cn10k_sso_hws_reset(void *arg, void *hws)
171 struct cnxk_sso_evdev *dev = arg;
172 struct cn10k_sso_hws *ws = hws;
173 uintptr_t base = ws->base;
181 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
182 /* Wait till getwork/swtp/waitw/desched completes. */
184 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
185 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
186 BIT_ULL(56) | BIT_ULL(54)));
187 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
188 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
189 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
190 cnxk_sso_hws_swtag_untag(base +
191 SSOW_LF_GWS_OP_SWTAG_UNTAG);
192 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
195 /* Wait for desched to complete. */
197 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
198 } while (pend_state & BIT_ULL(58));
200 switch (dev->gw_mode) {
201 case CN10K_GW_MODE_PREF:
202 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
205 case CN10K_GW_MODE_PREF_WFE:
206 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
207 SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
209 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
211 case CN10K_GW_MODE_NONE:
216 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
218 plt_write64(BIT_ULL(16) | 1,
219 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
221 roc_load_pair(gw.u64[0], gw.u64[1],
222 ws->base + SSOW_LF_GWS_WQE0);
223 } while (gw.u64[0] & BIT_ULL(63));
224 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
225 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
226 if (pend_tt == SSO_TT_ATOMIC ||
227 pend_tt == SSO_TT_ORDERED)
228 cnxk_sso_hws_swtag_untag(
229 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
230 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
234 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
239 cn10k_sso_set_rsrc(void *arg)
241 struct cnxk_sso_evdev *dev = arg;
243 dev->max_event_ports = dev->sso.max_hws;
244 dev->max_event_queues =
245 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
246 RTE_EVENT_MAX_QUEUES_PER_DEV :
251 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
253 struct cnxk_sso_evdev *dev = arg;
255 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
259 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
261 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
264 if (dev->tx_adptr_data == NULL)
267 for (i = 0; i < dev->nb_event_ports; i++) {
268 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
271 ws_cookie = cnxk_sso_hws_get_cookie(ws);
272 ws_cookie = rte_realloc_socket(
274 sizeof(struct cnxk_sso_hws_cookie) +
275 sizeof(struct cn10k_sso_hws) +
276 (sizeof(uint64_t) * (dev->max_port_id + 1) *
277 RTE_MAX_QUEUES_PER_PORT),
278 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
279 if (ws_cookie == NULL)
281 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
282 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
283 sizeof(uint64_t) * (dev->max_port_id + 1) *
284 RTE_MAX_QUEUES_PER_PORT);
285 event_dev->data->ports[i] = ws;
292 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
294 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
295 const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {
296 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
297 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,
298 NIX_RX_FASTPATH_MODES
302 const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {
303 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
304 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,
305 NIX_RX_FASTPATH_MODES
309 const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {
310 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
311 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,
312 NIX_RX_FASTPATH_MODES
316 const event_dequeue_burst_t
317 sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {
318 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
319 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,
320 NIX_RX_FASTPATH_MODES
324 const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {
325 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
326 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,
327 NIX_RX_FASTPATH_MODES
331 const event_dequeue_burst_t
332 sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {
333 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
334 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,
335 NIX_RX_FASTPATH_MODES
339 const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {
340 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
341 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
342 NIX_RX_FASTPATH_MODES
346 const event_dequeue_burst_t
347 sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {
348 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
349 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,
350 NIX_RX_FASTPATH_MODES
354 const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {
355 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
356 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,
357 NIX_RX_FASTPATH_MODES
361 const event_dequeue_burst_t
362 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
363 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
364 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
365 NIX_RX_FASTPATH_MODES
369 const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {
370 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
371 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,
372 NIX_RX_FASTPATH_MODES
376 const event_dequeue_burst_t
377 sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
378 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
379 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,
380 NIX_RX_FASTPATH_MODES
385 const event_tx_adapter_enqueue_t
386 sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
387 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
388 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
389 NIX_TX_FASTPATH_MODES
393 const event_tx_adapter_enqueue_t
394 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
395 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
396 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
397 NIX_TX_FASTPATH_MODES
401 event_dev->enqueue = cn10k_sso_hws_enq;
402 event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
403 event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
404 event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
405 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
406 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
408 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
409 sso_hws_deq_seg_burst);
410 if (dev->is_timeout_deq) {
411 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
412 sso_hws_deq_tmo_seg);
413 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
414 sso_hws_deq_tmo_seg_burst);
416 if (dev->is_ca_internal_port) {
417 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
419 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
420 sso_hws_deq_ca_seg_burst);
423 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
424 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
426 if (dev->is_timeout_deq) {
427 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
429 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
430 sso_hws_deq_tmo_burst);
432 if (dev->is_ca_internal_port) {
433 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
435 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
436 sso_hws_deq_ca_burst);
439 event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
441 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
442 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
443 sso_hws_tx_adptr_enq_seg);
445 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
446 sso_hws_tx_adptr_enq);
448 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
452 cn10k_sso_info_get(struct rte_eventdev *event_dev,
453 struct rte_event_dev_info *dev_info)
455 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
457 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
458 cnxk_sso_info_get(dev, dev_info);
462 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
464 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
467 rc = cnxk_sso_dev_validate(event_dev);
469 plt_err("Invalid event device configuration");
473 roc_sso_rsrc_fini(&dev->sso);
475 rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
476 dev->nb_event_queues);
478 plt_err("Failed to initialize SSO resources");
482 rc = cnxk_sso_xaq_allocate(dev);
486 rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
487 cn10k_sso_hws_setup);
491 /* Restore any prior port-queue mapping. */
492 cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
499 roc_sso_rsrc_fini(&dev->sso);
500 dev->nb_event_ports = 0;
505 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
506 const struct rte_event_port_conf *port_conf)
509 RTE_SET_USED(port_conf);
510 return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
514 cn10k_sso_port_release(void *port)
516 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
517 struct cnxk_sso_evdev *dev;
522 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
523 if (!gws_cookie->configured)
526 cn10k_sso_hws_release(dev, port);
527 memset(gws_cookie, 0, sizeof(*gws_cookie));
529 rte_free(gws_cookie);
533 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
534 const uint8_t queues[], const uint8_t priorities[],
537 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
538 uint16_t hwgrp_ids[nb_links];
541 RTE_SET_USED(priorities);
542 for (link = 0; link < nb_links; link++)
543 hwgrp_ids[link] = queues[link];
544 nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
546 return (int)nb_links;
550 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
551 uint8_t queues[], uint16_t nb_unlinks)
553 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
554 uint16_t hwgrp_ids[nb_unlinks];
557 for (unlink = 0; unlink < nb_unlinks; unlink++)
558 hwgrp_ids[unlink] = queues[unlink];
559 nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
561 return (int)nb_unlinks;
565 cn10k_sso_start(struct rte_eventdev *event_dev)
569 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
573 rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
574 cn10k_sso_hws_flush_events);
577 cn10k_sso_fp_fns_set(event_dev);
583 cn10k_sso_stop(struct rte_eventdev *event_dev)
585 cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
586 cn10k_sso_hws_flush_events);
590 cn10k_sso_close(struct rte_eventdev *event_dev)
592 return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
596 cn10k_sso_selftest(void)
598 return cnxk_sso_selftest(RTE_STR(event_cn10k));
602 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
603 const struct rte_eth_dev *eth_dev, uint32_t *caps)
607 RTE_SET_USED(event_dev);
608 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
610 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
612 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
613 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
614 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
615 RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
621 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
624 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
627 for (i = 0; i < dev->nb_event_ports; i++) {
628 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
629 ws->lookup_mem = lookup_mem;
630 ws->tstamp = tstmp_info;
635 cn10k_sso_rx_adapter_queue_add(
636 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
638 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
640 struct cn10k_eth_rxq *rxq;
645 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
649 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
653 rxq = eth_dev->data->rx_queues[0];
654 lookup_mem = rxq->lookup_mem;
655 tstmp_info = rxq->tstamp;
656 cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
657 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
663 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
664 const struct rte_eth_dev *eth_dev,
669 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
673 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
677 cn10k_sso_rx_adapter_vector_limits(
678 const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
679 struct rte_event_eth_rx_adapter_vector_limits *limits)
681 struct cnxk_eth_dev *cnxk_eth_dev;
685 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
689 cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
690 limits->log2_sz = true;
691 limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
692 limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
693 limits->min_timeout_ns =
694 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
695 limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
701 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
702 const struct rte_eth_dev *eth_dev, uint32_t *caps)
707 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
711 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
712 RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
718 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
719 const struct rte_eth_dev *eth_dev,
725 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
728 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
731 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
737 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
738 const struct rte_eth_dev *eth_dev,
744 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
747 return cn10k_sso_updt_tx_adptr_data(event_dev);
751 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
752 const struct rte_cryptodev *cdev, uint32_t *caps)
754 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
755 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
757 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
758 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
764 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
765 const struct rte_cryptodev *cdev,
766 int32_t queue_pair_id,
767 const struct rte_event *event)
769 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
773 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
774 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
776 dev->is_ca_internal_port = 1;
777 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
779 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
783 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
784 const struct rte_cryptodev *cdev,
785 int32_t queue_pair_id)
787 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
788 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
790 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
793 static struct eventdev_ops cn10k_sso_dev_ops = {
794 .dev_infos_get = cn10k_sso_info_get,
795 .dev_configure = cn10k_sso_dev_configure,
796 .queue_def_conf = cnxk_sso_queue_def_conf,
797 .queue_setup = cnxk_sso_queue_setup,
798 .queue_release = cnxk_sso_queue_release,
799 .port_def_conf = cnxk_sso_port_def_conf,
800 .port_setup = cn10k_sso_port_setup,
801 .port_release = cn10k_sso_port_release,
802 .port_link = cn10k_sso_port_link,
803 .port_unlink = cn10k_sso_port_unlink,
804 .timeout_ticks = cnxk_sso_timeout_ticks,
806 .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
807 .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
808 .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
809 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
810 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
812 .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
814 .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
815 .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
816 .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
818 .timer_adapter_caps_get = cnxk_tim_caps_get,
820 .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
821 .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
822 .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
824 .dump = cnxk_sso_dump,
825 .dev_start = cn10k_sso_start,
826 .dev_stop = cn10k_sso_stop,
827 .dev_close = cn10k_sso_close,
828 .dev_selftest = cn10k_sso_selftest,
832 cn10k_sso_init(struct rte_eventdev *event_dev)
834 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
837 if (RTE_CACHE_LINE_SIZE != 64) {
838 plt_err("Driver not compiled for CN10K");
844 plt_err("Failed to initialize platform model");
848 event_dev->dev_ops = &cn10k_sso_dev_ops;
849 /* For secondary processes, the primary has done all the work */
850 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
851 cn10k_sso_fp_fns_set(event_dev);
855 rc = cnxk_sso_init(event_dev);
859 cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
860 if (!dev->max_event_ports || !dev->max_event_queues) {
861 plt_err("Not enough eventdev resource queues=%d ports=%d",
862 dev->max_event_queues, dev->max_event_ports);
863 cnxk_sso_fini(event_dev);
867 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
868 event_dev->data->name, dev->max_event_queues,
869 dev->max_event_ports);
875 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
877 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
878 sizeof(struct cnxk_sso_evdev),
882 static const struct rte_pci_id cn10k_pci_sso_map[] = {
883 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
884 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
885 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
886 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
887 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
888 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
894 static struct rte_pci_driver cn10k_pci_sso = {
895 .id_table = cn10k_pci_sso_map,
896 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
897 .probe = cn10k_sso_probe,
898 .remove = cnxk_sso_remove,
901 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
902 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
903 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
904 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
905 CNXK_SSO_GGRP_QOS "=<string>"
906 CNXK_SSO_FORCE_BP "=1"
907 CN10K_SSO_GW_MODE "=<int>"
908 CNXK_TIM_DISABLE_NPA "=1"
909 CNXK_TIM_CHNK_SLOTS "=<int>"
910 CNXK_TIM_RINGS_LMT "=<int>"
911 CNXK_TIM_STATS_ENA "=1");