drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                           \
  10         deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
  11
  12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                           \
  13         enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
  14
  15 static uint32_t
  16 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  17 {
  18         uint32_t wdata = 1;
  19
  20         if (dev->deq_tmo_ns)
  21                 wdata |= BIT(16);
  22
  23         switch (dev->gw_mode) {
  24         case CN10K_GW_MODE_NONE:
  25         default:
  26                 break;
  27         case CN10K_GW_MODE_PREF:
  28                 wdata |= BIT(19);
  29                 break;
  30         case CN10K_GW_MODE_PREF_WFE:
  31                 wdata |= BIT(20) | BIT(19);
  32                 break;
  33         }
  34
  35         return wdata;
  36 }
  37
  38 static void *
  39 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  40 {
  41         struct cnxk_sso_evdev *dev = arg;
  42         struct cn10k_sso_hws *ws;
  43
  44         /* Allocate event port memory */
  45         ws = rte_zmalloc("cn10k_ws",
  46                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  47                          RTE_CACHE_LINE_SIZE);
  48         if (ws == NULL) {
  49                 plt_err("Failed to alloc memory for port=%d", port_id);
  50                 return NULL;
  51         }
  52
  53         /* First cache line is reserved for cookie */
  54         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  55         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  56         ws->hws_id = port_id;
  57         ws->swtag_req = 0;
  58         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  59         ws->lmt_base = dev->sso.lmt_base;
  60
  61         return ws;
  62 }
  63
  64 static int
  65 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  66 {
  67         struct cnxk_sso_evdev *dev = arg;
  68         struct cn10k_sso_hws *ws = port;
  69
  70         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  71 }
  72
  73 static int
  74 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  75 {
  76         struct cnxk_sso_evdev *dev = arg;
  77         struct cn10k_sso_hws *ws = port;
  78
  79         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  80 }
  81
  82 static void
  83 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
  84 {
  85         struct cnxk_sso_evdev *dev = arg;
  86         struct cn10k_sso_hws *ws = hws;
  87         uint64_t val;
  88
  89         ws->grp_base = grp_base;
  90         ws->fc_mem = (uint64_t *)dev->fc_iova;
  91         ws->xaq_lmt = dev->xaq_lmt;
  92
  93         /* Set get_work timeout for HWS */
  94         val = NSEC2USEC(dev->deq_tmo_ns);
  95         val = val ? val - 1 : 0;
  96         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  97 }
  98
  99 static void
 100 cn10k_sso_hws_release(void *arg, void *hws)
 101 {
 102         struct cnxk_sso_evdev *dev = arg;
 103         struct cn10k_sso_hws *ws = hws;
 104         uint16_t i;
 105
 106         for (i = 0; i < dev->nb_event_queues; i++)
 107                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
 108         memset(ws, 0, sizeof(*ws));
 109 }
 110
 111 static int
 112 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 113                            cnxk_handle_event_t fn, void *arg)
 114 {
 115         uint64_t retry = CNXK_SSO_FLUSH_RETRY_MAX;
 116         struct cn10k_sso_hws *ws = hws;
 117         uint64_t cq_ds_cnt = 1;
 118         uint64_t aq_cnt = 1;
 119         uint64_t ds_cnt = 1;
 120         struct rte_event ev;
 121         uint64_t val, req;
 122
 123         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 124
 125         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 126         req = queue_id;     /* GGRP ID */
 127         req |= BIT_ULL(18); /* Grouped */
 128         req |= BIT_ULL(16); /* WAIT */
 129
 130         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 131         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 132         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 133         cq_ds_cnt &= 0x3FFF3FFF0000;
 134
 135         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 136                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 137                 cn10k_sso_hws_get_work_empty(
 138                         ws, &ev,
 139                         (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 140                                 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 141                 if (fn != NULL && ev.u64 != 0)
 142                         fn(arg, ev);
 143                 if (ev.sched_type != SSO_TT_EMPTY)
 144                         cnxk_sso_hws_swtag_flush(ws->base);
 145                 else if (retry-- == 0)
 146                         break;
 147                 do {
 148                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 149                 } while (val & BIT_ULL(56));
 150                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 151                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 152                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 153                 /* Extract cq and ds count */
 154                 cq_ds_cnt &= 0x3FFF3FFF0000;
 155         }
 156
 157         if (aq_cnt || cq_ds_cnt || ds_cnt)
 158                 return -EAGAIN;
 159
 160         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 161         rte_mb();
 162
 163         return 0;
 164 }
 165
 166 static void
 167 cn10k_sso_hws_reset(void *arg, void *hws)
 168 {
 169         struct cnxk_sso_evdev *dev = arg;
 170         struct cn10k_sso_hws *ws = hws;
 171         uintptr_t base = ws->base;
 172         uint64_t pend_state;
 173         union {
 174                 __uint128_t wdata;
 175                 uint64_t u64[2];
 176         } gw;
 177         uint8_t pend_tt;
 178         bool is_pend;
 179
 180         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 181         /* Wait till getwork/swtp/waitw/desched completes. */
 182         is_pend = false;
 183         /* Work in WQE0 is always consumed, unless its a SWTAG. */
 184         pend_state = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 185         if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
 186             ws->swtag_req)
 187                 is_pend = true;
 188
 189         do {
 190                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 191         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 192                                BIT_ULL(56) | BIT_ULL(54)));
 193         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 194         if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 195                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 196                         cnxk_sso_hws_swtag_untag(base +
 197                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 198                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 199         }
 200
 201         /* Wait for desched to complete. */
 202         do {
 203                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 204         } while (pend_state & BIT_ULL(58));
 205
 206         switch (dev->gw_mode) {
 207         case CN10K_GW_MODE_PREF:
 208         case CN10K_GW_MODE_PREF_WFE:
 209                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 210                         ;
 211                 break;
 212         case CN10K_GW_MODE_NONE:
 213         default:
 214                 break;
 215         }
 216
 217         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 218             SSO_TT_EMPTY) {
 219                 plt_write64(BIT_ULL(16) | 1,
 220                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 221                 do {
 222                         roc_load_pair(gw.u64[0], gw.u64[1],
 223                                       ws->base + SSOW_LF_GWS_WQE0);
 224                 } while (gw.u64[0] & BIT_ULL(63));
 225                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 226                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 227                         if (pend_tt == SSO_TT_ATOMIC ||
 228                             pend_tt == SSO_TT_ORDERED)
 229                                 cnxk_sso_hws_swtag_untag(
 230                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 231                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 232                 }
 233         }
 234
 235         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 236         rte_mb();
 237 }
 238
 239 static void
 240 cn10k_sso_set_rsrc(void *arg)
 241 {
 242         struct cnxk_sso_evdev *dev = arg;
 243
 244         dev->max_event_ports = dev->sso.max_hws;
 245         dev->max_event_queues =
 246                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 247                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 248                               dev->sso.max_hwgrp;
 249 }
 250
 251 static int
 252 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 253 {
 254         struct cnxk_sso_evdev *dev = arg;
 255
 256         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 257 }
 258
 259 static int
 260 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 261 {
 262         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 263         int i;
 264
 265         if (dev->tx_adptr_data == NULL)
 266                 return 0;
 267
 268         for (i = 0; i < dev->nb_event_ports; i++) {
 269                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 270                 void *ws_cookie;
 271
 272                 ws_cookie = cnxk_sso_hws_get_cookie(ws);
 273                 ws_cookie = rte_realloc_socket(
 274                         ws_cookie,
 275                         sizeof(struct cnxk_sso_hws_cookie) +
 276                                 sizeof(struct cn10k_sso_hws) +
 277                                 dev->tx_adptr_data_sz,
 278                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 279                 if (ws_cookie == NULL)
 280                         return -ENOMEM;
 281                 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
 282                 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 283                        dev->tx_adptr_data_sz);
 284                 event_dev->data->ports[i] = ws;
 285         }
 286
 287         return 0;
 288 }
 289
 290 static void
 291 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 292 {
 293         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 294         const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
 295 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
 296                 NIX_RX_FASTPATH_MODES
 297 #undef R
 298         };
 299
 300         const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
 301 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
 302                 NIX_RX_FASTPATH_MODES
 303 #undef R
 304         };
 305
 306         const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
 307 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
 308                 NIX_RX_FASTPATH_MODES
 309 #undef R
 310         };
 311
 312         const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
 313 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
 314                 NIX_RX_FASTPATH_MODES
 315 #undef R
 316         };
 317
 318         const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
 319 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
 320                 NIX_RX_FASTPATH_MODES
 321 #undef R
 322         };
 323
 324         const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 325 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
 326                 NIX_RX_FASTPATH_MODES
 327 #undef R
 328         };
 329
 330         const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
 331 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
 332                 NIX_RX_FASTPATH_MODES
 333 #undef R
 334         };
 335
 336         const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 337 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
 338                 NIX_RX_FASTPATH_MODES
 339 #undef R
 340         };
 341
 342         const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
 343 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
 344
 345                 NIX_RX_FASTPATH_MODES
 346 #undef R
 347         };
 348
 349         const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 350 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
 351                         NIX_RX_FASTPATH_MODES
 352 #undef R
 353         };
 354
 355         const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
 356 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
 357                 NIX_RX_FASTPATH_MODES
 358 #undef R
 359         };
 360
 361         const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 362 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 363                 NIX_RX_FASTPATH_MODES
 364 #undef R
 365         };
 366
 367         const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 368 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
 369                 NIX_RX_FASTPATH_MODES
 370 #undef R
 371         };
 372
 373         const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 374 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
 375                 NIX_RX_FASTPATH_MODES
 376 #undef R
 377         };
 378
 379         const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 380 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
 381                 NIX_RX_FASTPATH_MODES
 382 #undef R
 383         };
 384
 385         const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 386 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
 387                 NIX_RX_FASTPATH_MODES
 388 #undef R
 389         };
 390
 391         /* Tx modes */
 392         const event_tx_adapter_enqueue_t
 393                 sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
 394 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name,
 395                         NIX_TX_FASTPATH_MODES
 396 #undef T
 397                 };
 398
 399         const event_tx_adapter_enqueue_t
 400                 sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
 401 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
 402                         NIX_TX_FASTPATH_MODES
 403 #undef T
 404                 };
 405
 406         event_dev->enqueue = cn10k_sso_hws_enq;
 407         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 408         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 409         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 410         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 411                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 412                                        sso_hws_deq_seg);
 413                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 414                                        sso_hws_deq_seg_burst);
 415                 if (dev->is_timeout_deq) {
 416                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 417                                                sso_hws_deq_tmo_seg);
 418                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 419                                                sso_hws_deq_tmo_seg_burst);
 420                 }
 421                 if (dev->is_ca_internal_port) {
 422                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 423                                                sso_hws_deq_ca_seg);
 424                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 425                                                sso_hws_deq_ca_seg_burst);
 426                 }
 427                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 428                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 429                                                sso_hws_deq_tmo_ca_seg);
 430                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 431                                                sso_hws_deq_tmo_ca_seg_burst);
 432                 }
 433         } else {
 434                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
 435                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 436                                        sso_hws_deq_burst);
 437                 if (dev->is_timeout_deq) {
 438                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 439                                                sso_hws_deq_tmo);
 440                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 441                                                sso_hws_deq_tmo_burst);
 442                 }
 443                 if (dev->is_ca_internal_port) {
 444                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 445                                                sso_hws_deq_ca);
 446                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 447                                                sso_hws_deq_ca_burst);
 448                 }
 449                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 450                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 451                                                sso_hws_deq_tmo_ca);
 452                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 453                                                sso_hws_deq_tmo_ca_burst);
 454                 }
 455         }
 456         event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 457
 458         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
 459                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 460                                        sso_hws_tx_adptr_enq_seg);
 461         else
 462                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 463                                        sso_hws_tx_adptr_enq);
 464
 465         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 466 }
 467
 468 static void
 469 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 470                    struct rte_event_dev_info *dev_info)
 471 {
 472         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 473
 474         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 475         cnxk_sso_info_get(dev, dev_info);
 476 }
 477
 478 static int
 479 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 480 {
 481         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 482         int rc;
 483
 484         rc = cnxk_sso_dev_validate(event_dev);
 485         if (rc < 0) {
 486                 plt_err("Invalid event device configuration");
 487                 return -EINVAL;
 488         }
 489
 490         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 491                                  dev->nb_event_queues);
 492         if (rc < 0) {
 493                 plt_err("Failed to initialize SSO resources");
 494                 return -ENODEV;
 495         }
 496
 497         rc = cnxk_sso_xaq_allocate(dev);
 498         if (rc < 0)
 499                 goto cnxk_rsrc_fini;
 500
 501         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 502                                     cn10k_sso_hws_setup);
 503         if (rc < 0)
 504                 goto cnxk_rsrc_fini;
 505
 506         /* Restore any prior port-queue mapping. */
 507         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 508
 509         dev->configured = 1;
 510         rte_mb();
 511
 512         return 0;
 513 cnxk_rsrc_fini:
 514         roc_sso_rsrc_fini(&dev->sso);
 515         dev->nb_event_ports = 0;
 516         return rc;
 517 }
 518
 519 static int
 520 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 521                      const struct rte_event_port_conf *port_conf)
 522 {
 523
 524         RTE_SET_USED(port_conf);
 525         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 526 }
 527
 528 static void
 529 cn10k_sso_port_release(void *port)
 530 {
 531         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 532         struct cnxk_sso_evdev *dev;
 533
 534         if (port == NULL)
 535                 return;
 536
 537         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 538         if (!gws_cookie->configured)
 539                 goto free;
 540
 541         cn10k_sso_hws_release(dev, port);
 542         memset(gws_cookie, 0, sizeof(*gws_cookie));
 543 free:
 544         rte_free(gws_cookie);
 545 }
 546
 547 static void
 548 cn10k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,
 549                        rte_eventdev_port_flush_t flush_cb, void *args)
 550 {
 551         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 552         struct cn10k_sso_hws *ws = port;
 553         struct rte_event ev;
 554         uint64_t ptag;
 555         bool is_pend;
 556
 557         is_pend = false;
 558         /* Work in WQE0 is always consumed, unless its a SWTAG. */
 559         ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 560         if (ptag & (BIT_ULL(62) | BIT_ULL(54)) || ws->swtag_req)
 561                 is_pend = true;
 562         do {
 563                 ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 564         } while (ptag &
 565                  (BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54)));
 566
 567         cn10k_sso_hws_get_work_empty(ws, &ev,
 568                                      (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 569                                              NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 570         if (is_pend && ev.u64) {
 571                 if (flush_cb)
 572                         flush_cb(event_dev->data->dev_id, ev, args);
 573                 cnxk_sso_hws_swtag_flush(ws->base);
 574         }
 575
 576         /* Check if we have work in PRF_WQE0, if so extract it. */
 577         switch (dev->gw_mode) {
 578         case CN10K_GW_MODE_PREF:
 579         case CN10K_GW_MODE_PREF_WFE:
 580                 while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) &
 581                        BIT_ULL(63))
 582                         ;
 583                 break;
 584         case CN10K_GW_MODE_NONE:
 585         default:
 586                 break;
 587         }
 588
 589         if (CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0)) !=
 590             SSO_TT_EMPTY) {
 591                 plt_write64(BIT_ULL(16) | 1,
 592                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 593                 cn10k_sso_hws_get_work_empty(
 594                         ws, &ev,
 595                         (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 596                                 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 597                 if (ev.u64) {
 598                         if (flush_cb)
 599                                 flush_cb(event_dev->data->dev_id, ev, args);
 600                         cnxk_sso_hws_swtag_flush(ws->base);
 601                 }
 602         }
 603         ws->swtag_req = 0;
 604         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 605 }
 606
 607 static int
 608 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 609                     const uint8_t queues[], const uint8_t priorities[],
 610                     uint16_t nb_links)
 611 {
 612         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 613         uint16_t hwgrp_ids[nb_links];
 614         uint16_t link;
 615
 616         RTE_SET_USED(priorities);
 617         for (link = 0; link < nb_links; link++)
 618                 hwgrp_ids[link] = queues[link];
 619         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 620
 621         return (int)nb_links;
 622 }
 623
 624 static int
 625 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 626                       uint8_t queues[], uint16_t nb_unlinks)
 627 {
 628         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 629         uint16_t hwgrp_ids[nb_unlinks];
 630         uint16_t unlink;
 631
 632         for (unlink = 0; unlink < nb_unlinks; unlink++)
 633                 hwgrp_ids[unlink] = queues[unlink];
 634         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 635
 636         return (int)nb_unlinks;
 637 }
 638
 639 static int
 640 cn10k_sso_start(struct rte_eventdev *event_dev)
 641 {
 642         int rc;
 643
 644         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 645         if (rc < 0)
 646                 return rc;
 647
 648         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 649                             cn10k_sso_hws_flush_events);
 650         if (rc < 0)
 651                 return rc;
 652         cn10k_sso_fp_fns_set(event_dev);
 653
 654         return rc;
 655 }
 656
 657 static void
 658 cn10k_sso_stop(struct rte_eventdev *event_dev)
 659 {
 660         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 661                       cn10k_sso_hws_flush_events);
 662 }
 663
 664 static int
 665 cn10k_sso_close(struct rte_eventdev *event_dev)
 666 {
 667         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 668 }
 669
 670 static int
 671 cn10k_sso_selftest(void)
 672 {
 673         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 674 }
 675
 676 static int
 677 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 678                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 679 {
 680         int rc;
 681
 682         RTE_SET_USED(event_dev);
 683         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 684         if (rc)
 685                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 686         else
 687                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 688                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 689                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
 690                         RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
 691
 692         return 0;
 693 }
 694
 695 static void
 696 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 697                        void *tstmp_info)
 698 {
 699         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 700         int i;
 701
 702         for (i = 0; i < dev->nb_event_ports; i++) {
 703                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 704                 ws->lookup_mem = lookup_mem;
 705                 ws->tstamp = tstmp_info;
 706         }
 707 }
 708
 709 static int
 710 cn10k_sso_rx_adapter_queue_add(
 711         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 712         int32_t rx_queue_id,
 713         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 714 {
 715         struct cn10k_eth_rxq *rxq;
 716         void *lookup_mem;
 717         void *tstmp_info;
 718         int rc;
 719
 720         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 721         if (rc)
 722                 return -EINVAL;
 723
 724         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 725                                            queue_conf);
 726         if (rc)
 727                 return -EINVAL;
 728         rxq = eth_dev->data->rx_queues[0];
 729         lookup_mem = rxq->lookup_mem;
 730         tstmp_info = rxq->tstamp;
 731         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 732         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 733
 734         return 0;
 735 }
 736
 737 static int
 738 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 739                                const struct rte_eth_dev *eth_dev,
 740                                int32_t rx_queue_id)
 741 {
 742         int rc;
 743
 744         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 745         if (rc)
 746                 return -EINVAL;
 747
 748         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 749 }
 750
 751 static int
 752 cn10k_sso_rx_adapter_vector_limits(
 753         const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
 754         struct rte_event_eth_rx_adapter_vector_limits *limits)
 755 {
 756         struct cnxk_eth_dev *cnxk_eth_dev;
 757         int ret;
 758
 759         RTE_SET_USED(dev);
 760         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 761         if (ret)
 762                 return -ENOTSUP;
 763
 764         cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
 765         limits->log2_sz = true;
 766         limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
 767         limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
 768         limits->min_timeout_ns =
 769                 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
 770         limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
 771
 772         return 0;
 773 }
 774
 775 static int
 776 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 777                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 778 {
 779         int ret;
 780
 781         RTE_SET_USED(dev);
 782         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 783         if (ret)
 784                 *caps = 0;
 785         else
 786                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
 787                         RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
 788
 789         return 0;
 790 }
 791
 792 static void
 793 cn10k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)
 794 {
 795         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 796         struct cn10k_eth_txq *txq;
 797         struct roc_nix_sq *sq;
 798         int i;
 799
 800         if (tx_queue_id < 0) {
 801                 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 802                         cn10k_sso_txq_fc_update(eth_dev, i);
 803         } else {
 804                 uint16_t sqes_per_sqb;
 805
 806                 sq = &cnxk_eth_dev->sqs[tx_queue_id];
 807                 txq = eth_dev->data->tx_queues[tx_queue_id];
 808                 sqes_per_sqb = 1U << txq->sqes_per_sqb_log2;
 809                 sq->nb_sqb_bufs_adj =
 810                         sq->nb_sqb_bufs -
 811                         RTE_ALIGN_MUL_CEIL(sq->nb_sqb_bufs, sqes_per_sqb) /
 812                                 sqes_per_sqb;
 813                 if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
 814                         sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc /
 815                                                 (sqes_per_sqb - 1));
 816                 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
 817                 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
 818         }
 819 }
 820
 821 static int
 822 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
 823                                const struct rte_eth_dev *eth_dev,
 824                                int32_t tx_queue_id)
 825 {
 826         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 827         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 828         uint64_t tx_offloads;
 829         int rc;
 830
 831         RTE_SET_USED(id);
 832         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
 833         if (rc < 0)
 834                 return rc;
 835
 836         /* Can't enable tstamp if all the ports don't have it enabled. */
 837         tx_offloads = cnxk_eth_dev->tx_offload_flags;
 838         if (dev->tx_adptr_configured) {
 839                 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 840                 uint8_t tstmp_ena =
 841                         !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 842
 843                 if (tstmp_ena && !tstmp_req)
 844                         dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 845                 else if (!tstmp_ena && tstmp_req)
 846                         tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 847         }
 848
 849         dev->tx_offloads |= tx_offloads;
 850         cn10k_sso_txq_fc_update(eth_dev, tx_queue_id);
 851         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 852         if (rc < 0)
 853                 return rc;
 854         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 855         dev->tx_adptr_configured = 1;
 856
 857         return 0;
 858 }
 859
 860 static int
 861 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
 862                                const struct rte_eth_dev *eth_dev,
 863                                int32_t tx_queue_id)
 864 {
 865         int rc;
 866
 867         RTE_SET_USED(id);
 868         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
 869         if (rc < 0)
 870                 return rc;
 871         return cn10k_sso_updt_tx_adptr_data(event_dev);
 872 }
 873
 874 static int
 875 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
 876                               const struct rte_cryptodev *cdev, uint32_t *caps)
 877 {
 878         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 879         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 880
 881         *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
 882                 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
 889                             const struct rte_cryptodev *cdev,
 890                             int32_t queue_pair_id,
 891                             const struct rte_event *event)
 892 {
 893         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 894
 895         RTE_SET_USED(event);
 896
 897         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 898         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 899
 900         dev->is_ca_internal_port = 1;
 901         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 902
 903         return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
 904 }
 905
 906 static int
 907 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
 908                             const struct rte_cryptodev *cdev,
 909                             int32_t queue_pair_id)
 910 {
 911         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 912         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 913
 914         return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 915 }
 916
 917 static struct eventdev_ops cn10k_sso_dev_ops = {
 918         .dev_infos_get = cn10k_sso_info_get,
 919         .dev_configure = cn10k_sso_dev_configure,
 920
 921         .queue_def_conf = cnxk_sso_queue_def_conf,
 922         .queue_setup = cnxk_sso_queue_setup,
 923         .queue_release = cnxk_sso_queue_release,
 924         .queue_attr_get = cnxk_sso_queue_attribute_get,
 925         .queue_attr_set = cnxk_sso_queue_attribute_set,
 926
 927         .port_def_conf = cnxk_sso_port_def_conf,
 928         .port_setup = cn10k_sso_port_setup,
 929         .port_release = cn10k_sso_port_release,
 930         .port_quiesce = cn10k_sso_port_quiesce,
 931         .port_link = cn10k_sso_port_link,
 932         .port_unlink = cn10k_sso_port_unlink,
 933         .timeout_ticks = cnxk_sso_timeout_ticks,
 934
 935         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 936         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 937         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 938         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 939         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 940
 941         .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
 942
 943         .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
 944         .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
 945         .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
 946
 947         .timer_adapter_caps_get = cnxk_tim_caps_get,
 948
 949         .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
 950         .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
 951         .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
 952
 953         .dump = cnxk_sso_dump,
 954         .dev_start = cn10k_sso_start,
 955         .dev_stop = cn10k_sso_stop,
 956         .dev_close = cn10k_sso_close,
 957         .dev_selftest = cn10k_sso_selftest,
 958 };
 959
 960 static int
 961 cn10k_sso_init(struct rte_eventdev *event_dev)
 962 {
 963         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 964         int rc;
 965
 966         if (RTE_CACHE_LINE_SIZE != 64) {
 967                 plt_err("Driver not compiled for CN10K");
 968                 return -EFAULT;
 969         }
 970
 971         rc = roc_plt_init();
 972         if (rc < 0) {
 973                 plt_err("Failed to initialize platform model");
 974                 return rc;
 975         }
 976
 977         event_dev->dev_ops = &cn10k_sso_dev_ops;
 978         /* For secondary processes, the primary has done all the work */
 979         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 980                 cn10k_sso_fp_fns_set(event_dev);
 981                 return 0;
 982         }
 983
 984         rc = cnxk_sso_init(event_dev);
 985         if (rc < 0)
 986                 return rc;
 987
 988         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 989         if (!dev->max_event_ports || !dev->max_event_queues) {
 990                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 991                         dev->max_event_queues, dev->max_event_ports);
 992                 cnxk_sso_fini(event_dev);
 993                 return -ENODEV;
 994         }
 995
 996         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 997                     event_dev->data->name, dev->max_event_queues,
 998                     dev->max_event_ports);
 999
1000         return 0;
1001 }
1002
1003 static int
1004 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1005 {
1006         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1007                                        sizeof(struct cnxk_sso_evdev),
1008                                        cn10k_sso_init);
1009 }
1010
1011 static const struct rte_pci_id cn10k_pci_sso_map[] = {
1012         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1013         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1014         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1015         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1016         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1017         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1018         {
1019                 .vendor_id = 0,
1020         },
1021 };
1022
1023 static struct rte_pci_driver cn10k_pci_sso = {
1024         .id_table = cn10k_pci_sso_map,
1025         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1026         .probe = cn10k_sso_probe,
1027         .remove = cnxk_sso_remove,
1028 };
1029
1030 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
1031 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
1032 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
1033 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
1034                               CNXK_SSO_GGRP_QOS "=<string>"
1035                               CNXK_SSO_FORCE_BP "=1"
1036                               CN10K_SSO_GW_MODE "=<int>"
1037                               CNXK_TIM_DISABLE_NPA "=1"
1038                               CNXK_TIM_CHNK_SLOTS "=<int>"
1039                               CNXK_TIM_RINGS_LMT "=<int>"
1040                               CNXK_TIM_STATS_ENA "=1"
1041                               CNXK_TIM_EXT_CLK "=<string>");