1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn10k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
10 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
13 enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
16 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
23 switch (dev->gw_mode) {
24 case CN10K_GW_MODE_NONE:
27 case CN10K_GW_MODE_PREF:
30 case CN10K_GW_MODE_PREF_WFE:
31 wdata |= BIT(20) | BIT(19);
39 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
41 struct cnxk_sso_evdev *dev = arg;
42 struct cn10k_sso_hws *ws;
44 /* Allocate event port memory */
45 ws = rte_zmalloc("cn10k_ws",
46 sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
49 plt_err("Failed to alloc memory for port=%d", port_id);
53 /* First cache line is reserved for cookie */
54 ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
55 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
58 ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
59 ws->lmt_base = dev->sso.lmt_base;
65 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
67 struct cnxk_sso_evdev *dev = arg;
68 struct cn10k_sso_hws *ws = port;
70 return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
74 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
76 struct cnxk_sso_evdev *dev = arg;
77 struct cn10k_sso_hws *ws = port;
79 return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
83 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
85 struct cnxk_sso_evdev *dev = arg;
86 struct cn10k_sso_hws *ws = hws;
89 ws->grp_base = grp_base;
90 ws->fc_mem = (uint64_t *)dev->fc_iova;
91 ws->xaq_lmt = dev->xaq_lmt;
93 /* Set get_work timeout for HWS */
94 val = NSEC2USEC(dev->deq_tmo_ns);
95 val = val ? val - 1 : 0;
96 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
100 cn10k_sso_hws_release(void *arg, void *hws)
102 struct cnxk_sso_evdev *dev = arg;
103 struct cn10k_sso_hws *ws = hws;
106 for (i = 0; i < dev->nb_event_queues; i++)
107 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
108 memset(ws, 0, sizeof(*ws));
112 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
113 cnxk_handle_event_t fn, void *arg)
115 uint64_t retry = CNXK_SSO_FLUSH_RETRY_MAX;
116 struct cn10k_sso_hws *ws = hws;
117 uint64_t cq_ds_cnt = 1;
123 plt_write64(0, base + SSO_LF_GGRP_QCTL);
125 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
126 req = queue_id; /* GGRP ID */
127 req |= BIT_ULL(18); /* Grouped */
128 req |= BIT_ULL(16); /* WAIT */
130 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
131 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
132 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
133 cq_ds_cnt &= 0x3FFF3FFF0000;
135 while (aq_cnt || cq_ds_cnt || ds_cnt) {
136 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
137 cn10k_sso_hws_get_work_empty(
139 (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
140 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
141 if (fn != NULL && ev.u64 != 0)
143 if (ev.sched_type != SSO_TT_EMPTY)
144 cnxk_sso_hws_swtag_flush(ws->base);
145 else if (retry-- == 0)
148 val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
149 } while (val & BIT_ULL(56));
150 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
151 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
152 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
153 /* Extract cq and ds count */
154 cq_ds_cnt &= 0x3FFF3FFF0000;
157 if (aq_cnt || cq_ds_cnt || ds_cnt)
160 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
167 cn10k_sso_hws_reset(void *arg, void *hws)
169 struct cnxk_sso_evdev *dev = arg;
170 struct cn10k_sso_hws *ws = hws;
171 uintptr_t base = ws->base;
180 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
181 /* Wait till getwork/swtp/waitw/desched completes. */
183 /* Work in WQE0 is always consumed, unless its a SWTAG. */
184 pend_state = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
185 if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
190 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
191 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
192 BIT_ULL(56) | BIT_ULL(54)));
193 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
194 if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
195 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
196 cnxk_sso_hws_swtag_untag(base +
197 SSOW_LF_GWS_OP_SWTAG_UNTAG);
198 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
201 /* Wait for desched to complete. */
203 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
204 } while (pend_state & BIT_ULL(58));
206 switch (dev->gw_mode) {
207 case CN10K_GW_MODE_PREF:
208 case CN10K_GW_MODE_PREF_WFE:
209 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
212 case CN10K_GW_MODE_NONE:
217 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
219 plt_write64(BIT_ULL(16) | 1,
220 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
222 roc_load_pair(gw.u64[0], gw.u64[1],
223 ws->base + SSOW_LF_GWS_WQE0);
224 } while (gw.u64[0] & BIT_ULL(63));
225 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
226 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
227 if (pend_tt == SSO_TT_ATOMIC ||
228 pend_tt == SSO_TT_ORDERED)
229 cnxk_sso_hws_swtag_untag(
230 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
231 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
235 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
240 cn10k_sso_set_rsrc(void *arg)
242 struct cnxk_sso_evdev *dev = arg;
244 dev->max_event_ports = dev->sso.max_hws;
245 dev->max_event_queues =
246 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
247 RTE_EVENT_MAX_QUEUES_PER_DEV :
252 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
254 struct cnxk_sso_evdev *dev = arg;
256 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
260 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
262 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
265 if (dev->tx_adptr_data == NULL)
268 for (i = 0; i < dev->nb_event_ports; i++) {
269 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
272 ws_cookie = cnxk_sso_hws_get_cookie(ws);
273 ws_cookie = rte_realloc_socket(
275 sizeof(struct cnxk_sso_hws_cookie) +
276 sizeof(struct cn10k_sso_hws) +
277 dev->tx_adptr_data_sz,
278 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
279 if (ws_cookie == NULL)
281 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
282 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
283 dev->tx_adptr_data_sz);
284 event_dev->data->ports[i] = ws;
291 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
293 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
294 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
295 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
296 NIX_RX_FASTPATH_MODES
300 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
301 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
302 NIX_RX_FASTPATH_MODES
306 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
307 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
308 NIX_RX_FASTPATH_MODES
312 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
313 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
314 NIX_RX_FASTPATH_MODES
318 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
319 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
320 NIX_RX_FASTPATH_MODES
324 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
325 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
326 NIX_RX_FASTPATH_MODES
330 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
331 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
332 NIX_RX_FASTPATH_MODES
336 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
337 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
338 NIX_RX_FASTPATH_MODES
342 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
343 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
345 NIX_RX_FASTPATH_MODES
349 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
350 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
351 NIX_RX_FASTPATH_MODES
355 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
356 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
357 NIX_RX_FASTPATH_MODES
361 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
362 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
363 NIX_RX_FASTPATH_MODES
367 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
368 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
369 NIX_RX_FASTPATH_MODES
373 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
374 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
375 NIX_RX_FASTPATH_MODES
379 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
380 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
381 NIX_RX_FASTPATH_MODES
385 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
386 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
387 NIX_RX_FASTPATH_MODES
392 const event_tx_adapter_enqueue_t
393 sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
394 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name,
395 NIX_TX_FASTPATH_MODES
399 const event_tx_adapter_enqueue_t
400 sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
401 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
402 NIX_TX_FASTPATH_MODES
406 event_dev->enqueue = cn10k_sso_hws_enq;
407 event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
408 event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
409 event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
410 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
411 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
413 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
414 sso_hws_deq_seg_burst);
415 if (dev->is_timeout_deq) {
416 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
417 sso_hws_deq_tmo_seg);
418 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
419 sso_hws_deq_tmo_seg_burst);
421 if (dev->is_ca_internal_port) {
422 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
424 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
425 sso_hws_deq_ca_seg_burst);
427 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
428 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
429 sso_hws_deq_tmo_ca_seg);
430 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
431 sso_hws_deq_tmo_ca_seg_burst);
434 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
435 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
437 if (dev->is_timeout_deq) {
438 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
440 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
441 sso_hws_deq_tmo_burst);
443 if (dev->is_ca_internal_port) {
444 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
446 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
447 sso_hws_deq_ca_burst);
449 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
450 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
452 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
453 sso_hws_deq_tmo_ca_burst);
456 event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
458 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
459 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
460 sso_hws_tx_adptr_enq_seg);
462 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
463 sso_hws_tx_adptr_enq);
465 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
469 cn10k_sso_info_get(struct rte_eventdev *event_dev,
470 struct rte_event_dev_info *dev_info)
472 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
474 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
475 cnxk_sso_info_get(dev, dev_info);
479 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
481 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
484 rc = cnxk_sso_dev_validate(event_dev);
486 plt_err("Invalid event device configuration");
490 rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
491 dev->nb_event_queues);
493 plt_err("Failed to initialize SSO resources");
497 rc = cnxk_sso_xaq_allocate(dev);
501 rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
502 cn10k_sso_hws_setup);
506 /* Restore any prior port-queue mapping. */
507 cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
514 roc_sso_rsrc_fini(&dev->sso);
515 dev->nb_event_ports = 0;
520 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
521 const struct rte_event_port_conf *port_conf)
524 RTE_SET_USED(port_conf);
525 return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
529 cn10k_sso_port_release(void *port)
531 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
532 struct cnxk_sso_evdev *dev;
537 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
538 if (!gws_cookie->configured)
541 cn10k_sso_hws_release(dev, port);
542 memset(gws_cookie, 0, sizeof(*gws_cookie));
544 rte_free(gws_cookie);
548 cn10k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,
549 rte_eventdev_port_flush_t flush_cb, void *args)
551 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
552 struct cn10k_sso_hws *ws = port;
558 /* Work in WQE0 is always consumed, unless its a SWTAG. */
559 ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
560 if (ptag & (BIT_ULL(62) | BIT_ULL(54)) || ws->swtag_req)
563 ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
565 (BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54)));
567 cn10k_sso_hws_get_work_empty(ws, &ev,
568 (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
569 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
570 if (is_pend && ev.u64) {
572 flush_cb(event_dev->data->dev_id, ev, args);
573 cnxk_sso_hws_swtag_flush(ws->base);
576 /* Check if we have work in PRF_WQE0, if so extract it. */
577 switch (dev->gw_mode) {
578 case CN10K_GW_MODE_PREF:
579 case CN10K_GW_MODE_PREF_WFE:
580 while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) &
584 case CN10K_GW_MODE_NONE:
589 if (CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0)) !=
591 plt_write64(BIT_ULL(16) | 1,
592 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
593 cn10k_sso_hws_get_work_empty(
595 (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
596 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
599 flush_cb(event_dev->data->dev_id, ev, args);
600 cnxk_sso_hws_swtag_flush(ws->base);
604 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
608 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
609 const uint8_t queues[], const uint8_t priorities[],
612 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
613 uint16_t hwgrp_ids[nb_links];
616 RTE_SET_USED(priorities);
617 for (link = 0; link < nb_links; link++)
618 hwgrp_ids[link] = queues[link];
619 nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
621 return (int)nb_links;
625 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
626 uint8_t queues[], uint16_t nb_unlinks)
628 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
629 uint16_t hwgrp_ids[nb_unlinks];
632 for (unlink = 0; unlink < nb_unlinks; unlink++)
633 hwgrp_ids[unlink] = queues[unlink];
634 nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
636 return (int)nb_unlinks;
640 cn10k_sso_start(struct rte_eventdev *event_dev)
644 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
648 rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
649 cn10k_sso_hws_flush_events);
652 cn10k_sso_fp_fns_set(event_dev);
658 cn10k_sso_stop(struct rte_eventdev *event_dev)
660 cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
661 cn10k_sso_hws_flush_events);
665 cn10k_sso_close(struct rte_eventdev *event_dev)
667 return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
671 cn10k_sso_selftest(void)
673 return cnxk_sso_selftest(RTE_STR(event_cn10k));
677 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
678 const struct rte_eth_dev *eth_dev, uint32_t *caps)
682 RTE_SET_USED(event_dev);
683 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
685 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
687 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
688 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
689 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
690 RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
696 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
699 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
702 for (i = 0; i < dev->nb_event_ports; i++) {
703 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
704 ws->lookup_mem = lookup_mem;
705 ws->tstamp = tstmp_info;
710 cn10k_sso_rx_adapter_queue_add(
711 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
713 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
715 struct cn10k_eth_rxq *rxq;
720 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
724 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
728 rxq = eth_dev->data->rx_queues[0];
729 lookup_mem = rxq->lookup_mem;
730 tstmp_info = rxq->tstamp;
731 cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
732 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
738 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
739 const struct rte_eth_dev *eth_dev,
744 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
748 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
752 cn10k_sso_rx_adapter_vector_limits(
753 const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
754 struct rte_event_eth_rx_adapter_vector_limits *limits)
756 struct cnxk_eth_dev *cnxk_eth_dev;
760 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
764 cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
765 limits->log2_sz = true;
766 limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
767 limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
768 limits->min_timeout_ns =
769 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
770 limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
776 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
777 const struct rte_eth_dev *eth_dev, uint32_t *caps)
782 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
786 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
787 RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
793 cn10k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)
795 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
796 struct cn10k_eth_txq *txq;
797 struct roc_nix_sq *sq;
800 if (tx_queue_id < 0) {
801 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
802 cn10k_sso_txq_fc_update(eth_dev, i);
804 uint16_t sqes_per_sqb;
806 sq = &cnxk_eth_dev->sqs[tx_queue_id];
807 txq = eth_dev->data->tx_queues[tx_queue_id];
808 sqes_per_sqb = 1U << txq->sqes_per_sqb_log2;
809 sq->nb_sqb_bufs_adj =
811 RTE_ALIGN_MUL_CEIL(sq->nb_sqb_bufs, sqes_per_sqb) /
813 if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
814 sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc /
816 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
817 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
822 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
823 const struct rte_eth_dev *eth_dev,
826 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
827 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
828 uint64_t tx_offloads;
832 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
836 /* Can't enable tstamp if all the ports don't have it enabled. */
837 tx_offloads = cnxk_eth_dev->tx_offload_flags;
838 if (dev->tx_adptr_configured) {
839 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
841 !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
843 if (tstmp_ena && !tstmp_req)
844 dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
845 else if (!tstmp_ena && tstmp_req)
846 tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
849 dev->tx_offloads |= tx_offloads;
850 cn10k_sso_txq_fc_update(eth_dev, tx_queue_id);
851 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
854 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
855 dev->tx_adptr_configured = 1;
861 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
862 const struct rte_eth_dev *eth_dev,
868 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
871 return cn10k_sso_updt_tx_adptr_data(event_dev);
875 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
876 const struct rte_cryptodev *cdev, uint32_t *caps)
878 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
879 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
881 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
882 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
888 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
889 const struct rte_cryptodev *cdev,
890 int32_t queue_pair_id,
891 const struct rte_event *event)
893 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
897 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
898 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
900 dev->is_ca_internal_port = 1;
901 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
903 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
907 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
908 const struct rte_cryptodev *cdev,
909 int32_t queue_pair_id)
911 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
912 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
914 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
917 static struct eventdev_ops cn10k_sso_dev_ops = {
918 .dev_infos_get = cn10k_sso_info_get,
919 .dev_configure = cn10k_sso_dev_configure,
921 .queue_def_conf = cnxk_sso_queue_def_conf,
922 .queue_setup = cnxk_sso_queue_setup,
923 .queue_release = cnxk_sso_queue_release,
924 .queue_attr_get = cnxk_sso_queue_attribute_get,
925 .queue_attr_set = cnxk_sso_queue_attribute_set,
927 .port_def_conf = cnxk_sso_port_def_conf,
928 .port_setup = cn10k_sso_port_setup,
929 .port_release = cn10k_sso_port_release,
930 .port_quiesce = cn10k_sso_port_quiesce,
931 .port_link = cn10k_sso_port_link,
932 .port_unlink = cn10k_sso_port_unlink,
933 .timeout_ticks = cnxk_sso_timeout_ticks,
935 .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
936 .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
937 .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
938 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
939 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
941 .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
943 .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
944 .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
945 .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
947 .timer_adapter_caps_get = cnxk_tim_caps_get,
949 .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
950 .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
951 .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
953 .dump = cnxk_sso_dump,
954 .dev_start = cn10k_sso_start,
955 .dev_stop = cn10k_sso_stop,
956 .dev_close = cn10k_sso_close,
957 .dev_selftest = cn10k_sso_selftest,
961 cn10k_sso_init(struct rte_eventdev *event_dev)
963 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
966 if (RTE_CACHE_LINE_SIZE != 64) {
967 plt_err("Driver not compiled for CN10K");
973 plt_err("Failed to initialize platform model");
977 event_dev->dev_ops = &cn10k_sso_dev_ops;
978 /* For secondary processes, the primary has done all the work */
979 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
980 cn10k_sso_fp_fns_set(event_dev);
984 rc = cnxk_sso_init(event_dev);
988 cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
989 if (!dev->max_event_ports || !dev->max_event_queues) {
990 plt_err("Not enough eventdev resource queues=%d ports=%d",
991 dev->max_event_queues, dev->max_event_ports);
992 cnxk_sso_fini(event_dev);
996 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
997 event_dev->data->name, dev->max_event_queues,
998 dev->max_event_ports);
1004 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1006 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1007 sizeof(struct cnxk_sso_evdev),
1011 static const struct rte_pci_id cn10k_pci_sso_map[] = {
1012 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1013 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1014 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1015 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1016 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1017 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1023 static struct rte_pci_driver cn10k_pci_sso = {
1024 .id_table = cn10k_pci_sso_map,
1025 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1026 .probe = cn10k_sso_probe,
1027 .remove = cnxk_sso_remove,
1030 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
1031 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
1032 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
1033 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
1034 CNXK_SSO_GGRP_QOS "=<string>"
1035 CNXK_SSO_FORCE_BP "=1"
1036 CN10K_SSO_GW_MODE "=<int>"
1037 CNXK_TIM_DISABLE_NPA "=1"
1038 CNXK_TIM_CHNK_SLOTS "=<int>"
1039 CNXK_TIM_RINGS_LMT "=<int>"
1040 CNXK_TIM_STATS_ENA "=1"
1041 CNXK_TIM_EXT_CLK "=<string>");