drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                           \
  10         deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
  11
  12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                           \
  13         enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
  14
  15 static uint32_t
  16 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  17 {
  18         uint32_t wdata = 1;
  19
  20         if (dev->deq_tmo_ns)
  21                 wdata |= BIT(16);
  22
  23         switch (dev->gw_mode) {
  24         case CN10K_GW_MODE_NONE:
  25         default:
  26                 break;
  27         case CN10K_GW_MODE_PREF:
  28                 wdata |= BIT(19);
  29                 break;
  30         case CN10K_GW_MODE_PREF_WFE:
  31                 wdata |= BIT(20) | BIT(19);
  32                 break;
  33         }
  34
  35         return wdata;
  36 }
  37
  38 static void *
  39 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  40 {
  41         struct cnxk_sso_evdev *dev = arg;
  42         struct cn10k_sso_hws *ws;
  43
  44         /* Allocate event port memory */
  45         ws = rte_zmalloc("cn10k_ws",
  46                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  47                          RTE_CACHE_LINE_SIZE);
  48         if (ws == NULL) {
  49                 plt_err("Failed to alloc memory for port=%d", port_id);
  50                 return NULL;
  51         }
  52
  53         /* First cache line is reserved for cookie */
  54         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  55         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  56         ws->hws_id = port_id;
  57         ws->swtag_req = 0;
  58         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  59         ws->lmt_base = dev->sso.lmt_base;
  60
  61         return ws;
  62 }
  63
  64 static int
  65 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  66 {
  67         struct cnxk_sso_evdev *dev = arg;
  68         struct cn10k_sso_hws *ws = port;
  69
  70         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  71 }
  72
  73 static int
  74 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  75 {
  76         struct cnxk_sso_evdev *dev = arg;
  77         struct cn10k_sso_hws *ws = port;
  78
  79         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  80 }
  81
  82 static void
  83 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
  84 {
  85         struct cnxk_sso_evdev *dev = arg;
  86         struct cn10k_sso_hws *ws = hws;
  87         uint64_t val;
  88
  89         ws->grp_base = grp_base;
  90         ws->fc_mem = (uint64_t *)dev->fc_iova;
  91         ws->xaq_lmt = dev->xaq_lmt;
  92
  93         /* Set get_work timeout for HWS */
  94         val = NSEC2USEC(dev->deq_tmo_ns);
  95         val = val ? val - 1 : 0;
  96         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  97 }
  98
  99 static void
 100 cn10k_sso_hws_release(void *arg, void *hws)
 101 {
 102         struct cnxk_sso_evdev *dev = arg;
 103         struct cn10k_sso_hws *ws = hws;
 104         uint16_t i;
 105
 106         for (i = 0; i < dev->nb_event_queues; i++)
 107                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
 108         memset(ws, 0, sizeof(*ws));
 109 }
 110
 111 static void
 112 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 113                            cnxk_handle_event_t fn, void *arg)
 114 {
 115         struct cn10k_sso_hws *ws = hws;
 116         uint64_t cq_ds_cnt = 1;
 117         uint64_t aq_cnt = 1;
 118         uint64_t ds_cnt = 1;
 119         struct rte_event ev;
 120         uint64_t val, req;
 121
 122         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 123
 124         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 125         req = queue_id;     /* GGRP ID */
 126         req |= BIT_ULL(18); /* Grouped */
 127         req |= BIT_ULL(16); /* WAIT */
 128
 129         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 130         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 131         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 132         cq_ds_cnt &= 0x3FFF3FFF0000;
 133
 134         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 135                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 136                 cn10k_sso_hws_get_work_empty(
 137                         ws, &ev,
 138                         (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 139                                 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 140                 if (fn != NULL && ev.u64 != 0)
 141                         fn(arg, ev);
 142                 if (ev.sched_type != SSO_TT_EMPTY)
 143                         cnxk_sso_hws_swtag_flush(ws->base);
 144                 do {
 145                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 146                 } while (val & BIT_ULL(56));
 147                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 148                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 149                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 150                 /* Extract cq and ds count */
 151                 cq_ds_cnt &= 0x3FFF3FFF0000;
 152         }
 153
 154         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 155         rte_mb();
 156 }
 157
 158 static void
 159 cn10k_sso_hws_reset(void *arg, void *hws)
 160 {
 161         struct cnxk_sso_evdev *dev = arg;
 162         struct cn10k_sso_hws *ws = hws;
 163         uintptr_t base = ws->base;
 164         uint64_t pend_state;
 165         union {
 166                 __uint128_t wdata;
 167                 uint64_t u64[2];
 168         } gw;
 169         uint8_t pend_tt;
 170         bool is_pend;
 171
 172         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 173         /* Wait till getwork/swtp/waitw/desched completes. */
 174         is_pend = false;
 175         /* Work in WQE0 is always consumed, unless its a SWTAG. */
 176         pend_state = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 177         if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
 178             ws->swtag_req)
 179                 is_pend = true;
 180
 181         do {
 182                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 183         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 184                                BIT_ULL(56) | BIT_ULL(54)));
 185         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 186         if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 187                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 188                         cnxk_sso_hws_swtag_untag(base +
 189                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 190                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 191         }
 192
 193         /* Wait for desched to complete. */
 194         do {
 195                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 196         } while (pend_state & BIT_ULL(58));
 197
 198         switch (dev->gw_mode) {
 199         case CN10K_GW_MODE_PREF:
 200         case CN10K_GW_MODE_PREF_WFE:
 201                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 202                         ;
 203                 break;
 204         case CN10K_GW_MODE_NONE:
 205         default:
 206                 break;
 207         }
 208
 209         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 210             SSO_TT_EMPTY) {
 211                 plt_write64(BIT_ULL(16) | 1,
 212                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 213                 do {
 214                         roc_load_pair(gw.u64[0], gw.u64[1],
 215                                       ws->base + SSOW_LF_GWS_WQE0);
 216                 } while (gw.u64[0] & BIT_ULL(63));
 217                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 218                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 219                         if (pend_tt == SSO_TT_ATOMIC ||
 220                             pend_tt == SSO_TT_ORDERED)
 221                                 cnxk_sso_hws_swtag_untag(
 222                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 223                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 224                 }
 225         }
 226
 227         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 228         rte_mb();
 229 }
 230
 231 static void
 232 cn10k_sso_set_rsrc(void *arg)
 233 {
 234         struct cnxk_sso_evdev *dev = arg;
 235
 236         dev->max_event_ports = dev->sso.max_hws;
 237         dev->max_event_queues =
 238                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 239                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 240                               dev->sso.max_hwgrp;
 241 }
 242
 243 static int
 244 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 245 {
 246         struct cnxk_sso_evdev *dev = arg;
 247
 248         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 249 }
 250
 251 static int
 252 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 253 {
 254         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 255         int i;
 256
 257         if (dev->tx_adptr_data == NULL)
 258                 return 0;
 259
 260         for (i = 0; i < dev->nb_event_ports; i++) {
 261                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 262                 void *ws_cookie;
 263
 264                 ws_cookie = cnxk_sso_hws_get_cookie(ws);
 265                 ws_cookie = rte_realloc_socket(
 266                         ws_cookie,
 267                         sizeof(struct cnxk_sso_hws_cookie) +
 268                                 sizeof(struct cn10k_sso_hws) +
 269                                 dev->tx_adptr_data_sz,
 270                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 271                 if (ws_cookie == NULL)
 272                         return -ENOMEM;
 273                 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
 274                 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 275                        dev->tx_adptr_data_sz);
 276                 event_dev->data->ports[i] = ws;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void
 283 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 284 {
 285         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 286         const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
 287 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
 288                 NIX_RX_FASTPATH_MODES
 289 #undef R
 290         };
 291
 292         const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
 293 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
 294                 NIX_RX_FASTPATH_MODES
 295 #undef R
 296         };
 297
 298         const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
 299 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
 300                 NIX_RX_FASTPATH_MODES
 301 #undef R
 302         };
 303
 304         const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
 305 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
 306                 NIX_RX_FASTPATH_MODES
 307 #undef R
 308         };
 309
 310         const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
 311 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
 312                 NIX_RX_FASTPATH_MODES
 313 #undef R
 314         };
 315
 316         const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 317 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
 318                 NIX_RX_FASTPATH_MODES
 319 #undef R
 320         };
 321
 322         const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
 323 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
 324                 NIX_RX_FASTPATH_MODES
 325 #undef R
 326         };
 327
 328         const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 329 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
 330                 NIX_RX_FASTPATH_MODES
 331 #undef R
 332         };
 333
 334         const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
 335 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
 336
 337                 NIX_RX_FASTPATH_MODES
 338 #undef R
 339         };
 340
 341         const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 342 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
 343                         NIX_RX_FASTPATH_MODES
 344 #undef R
 345         };
 346
 347         const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
 348 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
 349                 NIX_RX_FASTPATH_MODES
 350 #undef R
 351         };
 352
 353         const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 354 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 355                 NIX_RX_FASTPATH_MODES
 356 #undef R
 357         };
 358
 359         const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 360 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
 361                 NIX_RX_FASTPATH_MODES
 362 #undef R
 363         };
 364
 365         const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 366 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
 367                 NIX_RX_FASTPATH_MODES
 368 #undef R
 369         };
 370
 371         const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 372 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
 373                 NIX_RX_FASTPATH_MODES
 374 #undef R
 375         };
 376
 377         const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 378 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
 379                 NIX_RX_FASTPATH_MODES
 380 #undef R
 381         };
 382
 383         /* Tx modes */
 384         const event_tx_adapter_enqueue_t
 385                 sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
 386 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name,
 387                         NIX_TX_FASTPATH_MODES
 388 #undef T
 389                 };
 390
 391         const event_tx_adapter_enqueue_t
 392                 sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
 393 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
 394                         NIX_TX_FASTPATH_MODES
 395 #undef T
 396                 };
 397
 398         event_dev->enqueue = cn10k_sso_hws_enq;
 399         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 400         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 401         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 402         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 403                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 404                                        sso_hws_deq_seg);
 405                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 406                                        sso_hws_deq_seg_burst);
 407                 if (dev->is_timeout_deq) {
 408                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 409                                                sso_hws_deq_tmo_seg);
 410                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 411                                                sso_hws_deq_tmo_seg_burst);
 412                 }
 413                 if (dev->is_ca_internal_port) {
 414                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 415                                                sso_hws_deq_ca_seg);
 416                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 417                                                sso_hws_deq_ca_seg_burst);
 418                 }
 419                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 420                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 421                                                sso_hws_deq_tmo_ca_seg);
 422                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 423                                                sso_hws_deq_tmo_ca_seg_burst);
 424                 }
 425         } else {
 426                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
 427                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 428                                        sso_hws_deq_burst);
 429                 if (dev->is_timeout_deq) {
 430                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 431                                                sso_hws_deq_tmo);
 432                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 433                                                sso_hws_deq_tmo_burst);
 434                 }
 435                 if (dev->is_ca_internal_port) {
 436                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 437                                                sso_hws_deq_ca);
 438                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 439                                                sso_hws_deq_ca_burst);
 440                 }
 441                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 442                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 443                                                sso_hws_deq_tmo_ca);
 444                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 445                                                sso_hws_deq_tmo_ca_burst);
 446                 }
 447         }
 448         event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 449
 450         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
 451                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 452                                        sso_hws_tx_adptr_enq_seg);
 453         else
 454                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 455                                        sso_hws_tx_adptr_enq);
 456
 457         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 458 }
 459
 460 static void
 461 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 462                    struct rte_event_dev_info *dev_info)
 463 {
 464         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 465
 466         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 467         cnxk_sso_info_get(dev, dev_info);
 468 }
 469
 470 static int
 471 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 472 {
 473         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 474         int rc;
 475
 476         rc = cnxk_sso_dev_validate(event_dev);
 477         if (rc < 0) {
 478                 plt_err("Invalid event device configuration");
 479                 return -EINVAL;
 480         }
 481
 482         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 483                                  dev->nb_event_queues);
 484         if (rc < 0) {
 485                 plt_err("Failed to initialize SSO resources");
 486                 return -ENODEV;
 487         }
 488
 489         rc = cnxk_sso_xaq_allocate(dev);
 490         if (rc < 0)
 491                 goto cnxk_rsrc_fini;
 492
 493         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 494                                     cn10k_sso_hws_setup);
 495         if (rc < 0)
 496                 goto cnxk_rsrc_fini;
 497
 498         /* Restore any prior port-queue mapping. */
 499         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 500
 501         dev->configured = 1;
 502         rte_mb();
 503
 504         return 0;
 505 cnxk_rsrc_fini:
 506         roc_sso_rsrc_fini(&dev->sso);
 507         dev->nb_event_ports = 0;
 508         return rc;
 509 }
 510
 511 static int
 512 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 513                      const struct rte_event_port_conf *port_conf)
 514 {
 515
 516         RTE_SET_USED(port_conf);
 517         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 518 }
 519
 520 static void
 521 cn10k_sso_port_release(void *port)
 522 {
 523         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 524         struct cnxk_sso_evdev *dev;
 525
 526         if (port == NULL)
 527                 return;
 528
 529         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 530         if (!gws_cookie->configured)
 531                 goto free;
 532
 533         cn10k_sso_hws_release(dev, port);
 534         memset(gws_cookie, 0, sizeof(*gws_cookie));
 535 free:
 536         rte_free(gws_cookie);
 537 }
 538
 539 static void
 540 cn10k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,
 541                        rte_eventdev_port_flush_t flush_cb, void *args)
 542 {
 543         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 544         struct cn10k_sso_hws *ws = port;
 545         struct rte_event ev;
 546         uint64_t ptag;
 547         bool is_pend;
 548
 549         is_pend = false;
 550         /* Work in WQE0 is always consumed, unless its a SWTAG. */
 551         ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 552         if (ptag & (BIT_ULL(62) | BIT_ULL(54)) || ws->swtag_req)
 553                 is_pend = true;
 554         do {
 555                 ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 556         } while (ptag &
 557                  (BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54)));
 558
 559         cn10k_sso_hws_get_work_empty(ws, &ev,
 560                                      (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 561                                              NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 562         if (is_pend && ev.u64) {
 563                 if (flush_cb)
 564                         flush_cb(event_dev->data->dev_id, ev, args);
 565                 cnxk_sso_hws_swtag_flush(ws->base);
 566         }
 567
 568         /* Check if we have work in PRF_WQE0, if so extract it. */
 569         switch (dev->gw_mode) {
 570         case CN10K_GW_MODE_PREF:
 571         case CN10K_GW_MODE_PREF_WFE:
 572                 while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) &
 573                        BIT_ULL(63))
 574                         ;
 575                 break;
 576         case CN10K_GW_MODE_NONE:
 577         default:
 578                 break;
 579         }
 580
 581         if (CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0)) !=
 582             SSO_TT_EMPTY) {
 583                 plt_write64(BIT_ULL(16) | 1,
 584                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 585                 cn10k_sso_hws_get_work_empty(
 586                         ws, &ev,
 587                         (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 588                                 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 589                 if (ev.u64) {
 590                         if (flush_cb)
 591                                 flush_cb(event_dev->data->dev_id, ev, args);
 592                         cnxk_sso_hws_swtag_flush(ws->base);
 593                 }
 594         }
 595         ws->swtag_req = 0;
 596         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 597 }
 598
 599 static int
 600 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 601                     const uint8_t queues[], const uint8_t priorities[],
 602                     uint16_t nb_links)
 603 {
 604         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 605         uint16_t hwgrp_ids[nb_links];
 606         uint16_t link;
 607
 608         RTE_SET_USED(priorities);
 609         for (link = 0; link < nb_links; link++)
 610                 hwgrp_ids[link] = queues[link];
 611         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 612
 613         return (int)nb_links;
 614 }
 615
 616 static int
 617 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 618                       uint8_t queues[], uint16_t nb_unlinks)
 619 {
 620         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 621         uint16_t hwgrp_ids[nb_unlinks];
 622         uint16_t unlink;
 623
 624         for (unlink = 0; unlink < nb_unlinks; unlink++)
 625                 hwgrp_ids[unlink] = queues[unlink];
 626         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 627
 628         return (int)nb_unlinks;
 629 }
 630
 631 static int
 632 cn10k_sso_start(struct rte_eventdev *event_dev)
 633 {
 634         int rc;
 635
 636         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 637         if (rc < 0)
 638                 return rc;
 639
 640         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 641                             cn10k_sso_hws_flush_events);
 642         if (rc < 0)
 643                 return rc;
 644         cn10k_sso_fp_fns_set(event_dev);
 645
 646         return rc;
 647 }
 648
 649 static void
 650 cn10k_sso_stop(struct rte_eventdev *event_dev)
 651 {
 652         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 653                       cn10k_sso_hws_flush_events);
 654 }
 655
 656 static int
 657 cn10k_sso_close(struct rte_eventdev *event_dev)
 658 {
 659         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 660 }
 661
 662 static int
 663 cn10k_sso_selftest(void)
 664 {
 665         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 666 }
 667
 668 static int
 669 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 670                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 671 {
 672         int rc;
 673
 674         RTE_SET_USED(event_dev);
 675         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 676         if (rc)
 677                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 678         else
 679                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 680                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 681                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
 682                         RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
 683
 684         return 0;
 685 }
 686
 687 static void
 688 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 689                        void *tstmp_info)
 690 {
 691         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 692         int i;
 693
 694         for (i = 0; i < dev->nb_event_ports; i++) {
 695                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 696                 ws->lookup_mem = lookup_mem;
 697                 ws->tstamp = tstmp_info;
 698         }
 699 }
 700
 701 static int
 702 cn10k_sso_rx_adapter_queue_add(
 703         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 704         int32_t rx_queue_id,
 705         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 706 {
 707         struct cn10k_eth_rxq *rxq;
 708         void *lookup_mem;
 709         void *tstmp_info;
 710         int rc;
 711
 712         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 713         if (rc)
 714                 return -EINVAL;
 715
 716         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 717                                            queue_conf);
 718         if (rc)
 719                 return -EINVAL;
 720         rxq = eth_dev->data->rx_queues[0];
 721         lookup_mem = rxq->lookup_mem;
 722         tstmp_info = rxq->tstamp;
 723         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 724         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 725
 726         return 0;
 727 }
 728
 729 static int
 730 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 731                                const struct rte_eth_dev *eth_dev,
 732                                int32_t rx_queue_id)
 733 {
 734         int rc;
 735
 736         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 737         if (rc)
 738                 return -EINVAL;
 739
 740         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 741 }
 742
 743 static int
 744 cn10k_sso_rx_adapter_vector_limits(
 745         const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
 746         struct rte_event_eth_rx_adapter_vector_limits *limits)
 747 {
 748         struct cnxk_eth_dev *cnxk_eth_dev;
 749         int ret;
 750
 751         RTE_SET_USED(dev);
 752         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 753         if (ret)
 754                 return -ENOTSUP;
 755
 756         cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
 757         limits->log2_sz = true;
 758         limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
 759         limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
 760         limits->min_timeout_ns =
 761                 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
 762         limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
 763
 764         return 0;
 765 }
 766
 767 static int
 768 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 769                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 770 {
 771         int ret;
 772
 773         RTE_SET_USED(dev);
 774         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 775         if (ret)
 776                 *caps = 0;
 777         else
 778                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
 779                         RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
 780
 781         return 0;
 782 }
 783
 784 static void
 785 cn10k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)
 786 {
 787         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 788         struct cn10k_eth_txq *txq;
 789         struct roc_nix_sq *sq;
 790         int i;
 791
 792         if (tx_queue_id < 0) {
 793                 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 794                         cn10k_sso_txq_fc_update(eth_dev, i);
 795         } else {
 796                 uint16_t sqes_per_sqb;
 797
 798                 sq = &cnxk_eth_dev->sqs[tx_queue_id];
 799                 txq = eth_dev->data->tx_queues[tx_queue_id];
 800                 sqes_per_sqb = 1U << txq->sqes_per_sqb_log2;
 801                 sq->nb_sqb_bufs_adj =
 802                         sq->nb_sqb_bufs -
 803                         RTE_ALIGN_MUL_CEIL(sq->nb_sqb_bufs, sqes_per_sqb) /
 804                                 sqes_per_sqb;
 805                 if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
 806                         sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc /
 807                                                 (sqes_per_sqb - 1));
 808                 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
 809                 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
 810         }
 811 }
 812
 813 static int
 814 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
 815                                const struct rte_eth_dev *eth_dev,
 816                                int32_t tx_queue_id)
 817 {
 818         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 819         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 820         uint64_t tx_offloads;
 821         int rc;
 822
 823         RTE_SET_USED(id);
 824         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
 825         if (rc < 0)
 826                 return rc;
 827
 828         /* Can't enable tstamp if all the ports don't have it enabled. */
 829         tx_offloads = cnxk_eth_dev->tx_offload_flags;
 830         if (dev->tx_adptr_configured) {
 831                 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 832                 uint8_t tstmp_ena =
 833                         !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 834
 835                 if (tstmp_ena && !tstmp_req)
 836                         dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 837                 else if (!tstmp_ena && tstmp_req)
 838                         tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 839         }
 840
 841         dev->tx_offloads |= tx_offloads;
 842         cn10k_sso_txq_fc_update(eth_dev, tx_queue_id);
 843         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 844         if (rc < 0)
 845                 return rc;
 846         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 847         dev->tx_adptr_configured = 1;
 848
 849         return 0;
 850 }
 851
 852 static int
 853 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
 854                                const struct rte_eth_dev *eth_dev,
 855                                int32_t tx_queue_id)
 856 {
 857         int rc;
 858
 859         RTE_SET_USED(id);
 860         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
 861         if (rc < 0)
 862                 return rc;
 863         return cn10k_sso_updt_tx_adptr_data(event_dev);
 864 }
 865
 866 static int
 867 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
 868                               const struct rte_cryptodev *cdev, uint32_t *caps)
 869 {
 870         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 871         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 872
 873         *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
 874                 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 875
 876         return 0;
 877 }
 878
 879 static int
 880 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
 881                             const struct rte_cryptodev *cdev,
 882                             int32_t queue_pair_id,
 883                             const struct rte_event *event)
 884 {
 885         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 886
 887         RTE_SET_USED(event);
 888
 889         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 890         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 891
 892         dev->is_ca_internal_port = 1;
 893         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 894
 895         return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
 896 }
 897
 898 static int
 899 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
 900                             const struct rte_cryptodev *cdev,
 901                             int32_t queue_pair_id)
 902 {
 903         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 904         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 905
 906         return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 907 }
 908
 909 static struct eventdev_ops cn10k_sso_dev_ops = {
 910         .dev_infos_get = cn10k_sso_info_get,
 911         .dev_configure = cn10k_sso_dev_configure,
 912
 913         .queue_def_conf = cnxk_sso_queue_def_conf,
 914         .queue_setup = cnxk_sso_queue_setup,
 915         .queue_release = cnxk_sso_queue_release,
 916         .queue_attr_get = cnxk_sso_queue_attribute_get,
 917         .queue_attr_set = cnxk_sso_queue_attribute_set,
 918
 919         .port_def_conf = cnxk_sso_port_def_conf,
 920         .port_setup = cn10k_sso_port_setup,
 921         .port_release = cn10k_sso_port_release,
 922         .port_quiesce = cn10k_sso_port_quiesce,
 923         .port_link = cn10k_sso_port_link,
 924         .port_unlink = cn10k_sso_port_unlink,
 925         .timeout_ticks = cnxk_sso_timeout_ticks,
 926
 927         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 928         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 929         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 930         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 931         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 932
 933         .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
 934
 935         .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
 936         .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
 937         .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
 938
 939         .timer_adapter_caps_get = cnxk_tim_caps_get,
 940
 941         .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
 942         .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
 943         .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
 944
 945         .dump = cnxk_sso_dump,
 946         .dev_start = cn10k_sso_start,
 947         .dev_stop = cn10k_sso_stop,
 948         .dev_close = cn10k_sso_close,
 949         .dev_selftest = cn10k_sso_selftest,
 950 };
 951
 952 static int
 953 cn10k_sso_init(struct rte_eventdev *event_dev)
 954 {
 955         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 956         int rc;
 957
 958         if (RTE_CACHE_LINE_SIZE != 64) {
 959                 plt_err("Driver not compiled for CN10K");
 960                 return -EFAULT;
 961         }
 962
 963         rc = roc_plt_init();
 964         if (rc < 0) {
 965                 plt_err("Failed to initialize platform model");
 966                 return rc;
 967         }
 968
 969         event_dev->dev_ops = &cn10k_sso_dev_ops;
 970         /* For secondary processes, the primary has done all the work */
 971         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 972                 cn10k_sso_fp_fns_set(event_dev);
 973                 return 0;
 974         }
 975
 976         rc = cnxk_sso_init(event_dev);
 977         if (rc < 0)
 978                 return rc;
 979
 980         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 981         if (!dev->max_event_ports || !dev->max_event_queues) {
 982                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 983                         dev->max_event_queues, dev->max_event_ports);
 984                 cnxk_sso_fini(event_dev);
 985                 return -ENODEV;
 986         }
 987
 988         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 989                     event_dev->data->name, dev->max_event_queues,
 990                     dev->max_event_ports);
 991
 992         return 0;
 993 }
 994
 995 static int
 996 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 997 {
 998         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 999                                        sizeof(struct cnxk_sso_evdev),
1000                                        cn10k_sso_init);
1001 }
1002
1003 static const struct rte_pci_id cn10k_pci_sso_map[] = {
1004         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1005         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1006         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1007         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1008         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1009         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1010         {
1011                 .vendor_id = 0,
1012         },
1013 };
1014
1015 static struct rte_pci_driver cn10k_pci_sso = {
1016         .id_table = cn10k_pci_sso_map,
1017         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1018         .probe = cn10k_sso_probe,
1019         .remove = cnxk_sso_remove,
1020 };
1021
1022 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
1023 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
1024 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
1025 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
1026                               CNXK_SSO_GGRP_QOS "=<string>"
1027                               CNXK_SSO_FORCE_BP "=1"
1028                               CN10K_SSO_GW_MODE "=<int>"
1029                               CNXK_TIM_DISABLE_NPA "=1"
1030                               CNXK_TIM_CHNK_SLOTS "=<int>"
1031                               CNXK_TIM_RINGS_LMT "=<int>"
1032                               CNXK_TIM_STATS_ENA "=1"
1033                               CNXK_TIM_EXT_CLK "=<string>");