1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn10k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
10 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
14 enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)] \
15 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
16 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \
17 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \
18 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \
19 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
20 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
23 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
25 uint32_t wdata = BIT(16) | 1;
27 switch (dev->gw_mode) {
28 case CN10K_GW_MODE_NONE:
31 case CN10K_GW_MODE_PREF:
34 case CN10K_GW_MODE_PREF_WFE:
35 wdata |= BIT(20) | BIT(19);
43 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
45 struct cnxk_sso_evdev *dev = arg;
46 struct cn10k_sso_hws *ws;
48 /* Allocate event port memory */
49 ws = rte_zmalloc("cn10k_ws",
50 sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
53 plt_err("Failed to alloc memory for port=%d", port_id);
57 /* First cache line is reserved for cookie */
58 ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
59 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
60 ws->tx_base = ws->base;
63 ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
64 ws->lmt_base = dev->sso.lmt_base;
70 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
72 struct cnxk_sso_evdev *dev = arg;
73 struct cn10k_sso_hws *ws = port;
75 return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
79 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
81 struct cnxk_sso_evdev *dev = arg;
82 struct cn10k_sso_hws *ws = port;
84 return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
88 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
90 struct cnxk_sso_evdev *dev = arg;
91 struct cn10k_sso_hws *ws = hws;
94 ws->grp_base = grp_base;
95 ws->fc_mem = (uint64_t *)dev->fc_iova;
96 ws->xaq_lmt = dev->xaq_lmt;
98 /* Set get_work timeout for HWS */
99 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
100 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
104 cn10k_sso_hws_release(void *arg, void *hws)
106 struct cnxk_sso_evdev *dev = arg;
107 struct cn10k_sso_hws *ws = hws;
110 for (i = 0; i < dev->nb_event_queues; i++)
111 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
112 memset(ws, 0, sizeof(*ws));
116 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
117 cnxk_handle_event_t fn, void *arg)
119 struct cn10k_sso_hws *ws = hws;
120 uint64_t cq_ds_cnt = 1;
126 plt_write64(0, base + SSO_LF_GGRP_QCTL);
128 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
129 req = queue_id; /* GGRP ID */
130 req |= BIT_ULL(18); /* Grouped */
131 req |= BIT_ULL(16); /* WAIT */
133 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
134 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
135 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
136 cq_ds_cnt &= 0x3FFF3FFF0000;
138 while (aq_cnt || cq_ds_cnt || ds_cnt) {
139 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
140 cn10k_sso_hws_get_work_empty(ws, &ev);
141 if (fn != NULL && ev.u64 != 0)
143 if (ev.sched_type != SSO_TT_EMPTY)
144 cnxk_sso_hws_swtag_flush(
145 ws->base + SSOW_LF_GWS_WQE0,
146 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
148 val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
149 } while (val & BIT_ULL(56));
150 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
151 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
152 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
153 /* Extract cq and ds count */
154 cq_ds_cnt &= 0x3FFF3FFF0000;
157 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
162 cn10k_sso_hws_reset(void *arg, void *hws)
164 struct cnxk_sso_evdev *dev = arg;
165 struct cn10k_sso_hws *ws = hws;
166 uintptr_t base = ws->base;
174 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
175 /* Wait till getwork/swtp/waitw/desched completes. */
177 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
178 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
179 BIT_ULL(56) | BIT_ULL(54)));
180 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
181 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
182 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
183 cnxk_sso_hws_swtag_untag(base +
184 SSOW_LF_GWS_OP_SWTAG_UNTAG);
185 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
188 /* Wait for desched to complete. */
190 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
191 } while (pend_state & BIT_ULL(58));
193 switch (dev->gw_mode) {
194 case CN10K_GW_MODE_PREF:
195 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
198 case CN10K_GW_MODE_PREF_WFE:
199 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
200 SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
202 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
204 case CN10K_GW_MODE_NONE:
209 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
211 plt_write64(BIT_ULL(16) | 1,
212 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
214 roc_load_pair(gw.u64[0], gw.u64[1],
215 ws->base + SSOW_LF_GWS_WQE0);
216 } while (gw.u64[0] & BIT_ULL(63));
217 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
218 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
219 if (pend_tt == SSO_TT_ATOMIC ||
220 pend_tt == SSO_TT_ORDERED)
221 cnxk_sso_hws_swtag_untag(
222 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
223 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
227 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
232 cn10k_sso_set_rsrc(void *arg)
234 struct cnxk_sso_evdev *dev = arg;
236 dev->max_event_ports = dev->sso.max_hws;
237 dev->max_event_queues =
238 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
239 RTE_EVENT_MAX_QUEUES_PER_DEV :
244 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
246 struct cnxk_sso_evdev *dev = arg;
248 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
252 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
254 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
257 if (dev->tx_adptr_data == NULL)
260 for (i = 0; i < dev->nb_event_ports; i++) {
261 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
264 ws_cookie = cnxk_sso_hws_get_cookie(ws);
265 ws_cookie = rte_realloc_socket(
267 sizeof(struct cnxk_sso_hws_cookie) +
268 sizeof(struct cn10k_sso_hws) +
269 (sizeof(uint64_t) * (dev->max_port_id + 1) *
270 RTE_MAX_QUEUES_PER_PORT),
271 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
272 if (ws_cookie == NULL)
274 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
275 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
276 sizeof(uint64_t) * (dev->max_port_id + 1) *
277 RTE_MAX_QUEUES_PER_PORT);
278 event_dev->data->ports[i] = ws;
285 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
287 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
288 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
289 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
290 NIX_RX_FASTPATH_MODES
294 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
295 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
296 NIX_RX_FASTPATH_MODES
300 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
301 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
302 NIX_RX_FASTPATH_MODES
306 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
307 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
308 NIX_RX_FASTPATH_MODES
312 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
313 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
314 NIX_RX_FASTPATH_MODES
318 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
319 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
320 NIX_RX_FASTPATH_MODES
324 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
325 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
326 NIX_RX_FASTPATH_MODES
330 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
331 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
332 NIX_RX_FASTPATH_MODES
336 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
337 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
339 NIX_RX_FASTPATH_MODES
343 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
344 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
345 NIX_RX_FASTPATH_MODES
349 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
350 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
351 NIX_RX_FASTPATH_MODES
355 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
356 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
357 NIX_RX_FASTPATH_MODES
361 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
362 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
363 NIX_RX_FASTPATH_MODES
367 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
368 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
369 NIX_RX_FASTPATH_MODES
373 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
374 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
375 NIX_RX_FASTPATH_MODES
379 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
380 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
381 NIX_RX_FASTPATH_MODES
386 const event_tx_adapter_enqueue_t
387 sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
388 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
389 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
390 NIX_TX_FASTPATH_MODES
394 const event_tx_adapter_enqueue_t
395 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
396 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
397 [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
398 NIX_TX_FASTPATH_MODES
402 event_dev->enqueue = cn10k_sso_hws_enq;
403 event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
404 event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
405 event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
406 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
407 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
409 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
410 sso_hws_deq_seg_burst);
411 if (dev->is_timeout_deq) {
412 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
413 sso_hws_deq_tmo_seg);
414 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
415 sso_hws_deq_tmo_seg_burst);
417 if (dev->is_ca_internal_port) {
418 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
420 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
421 sso_hws_deq_ca_seg_burst);
423 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
424 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
425 sso_hws_deq_tmo_ca_seg);
426 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
427 sso_hws_deq_tmo_ca_seg_burst);
430 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
431 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
433 if (dev->is_timeout_deq) {
434 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
436 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
437 sso_hws_deq_tmo_burst);
439 if (dev->is_ca_internal_port) {
440 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
442 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
443 sso_hws_deq_ca_burst);
445 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
446 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
448 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
449 sso_hws_deq_tmo_ca_burst);
452 event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
454 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
455 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
456 sso_hws_tx_adptr_enq_seg);
458 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
459 sso_hws_tx_adptr_enq);
461 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
465 cn10k_sso_info_get(struct rte_eventdev *event_dev,
466 struct rte_event_dev_info *dev_info)
468 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
470 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
471 cnxk_sso_info_get(dev, dev_info);
475 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
477 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
480 rc = cnxk_sso_dev_validate(event_dev);
482 plt_err("Invalid event device configuration");
486 rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
487 dev->nb_event_queues);
489 plt_err("Failed to initialize SSO resources");
493 rc = cnxk_sso_xaq_allocate(dev);
497 rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
498 cn10k_sso_hws_setup);
502 /* Restore any prior port-queue mapping. */
503 cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
510 roc_sso_rsrc_fini(&dev->sso);
511 dev->nb_event_ports = 0;
516 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
517 const struct rte_event_port_conf *port_conf)
520 RTE_SET_USED(port_conf);
521 return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
525 cn10k_sso_port_release(void *port)
527 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
528 struct cnxk_sso_evdev *dev;
533 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
534 if (!gws_cookie->configured)
537 cn10k_sso_hws_release(dev, port);
538 memset(gws_cookie, 0, sizeof(*gws_cookie));
540 rte_free(gws_cookie);
544 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
545 const uint8_t queues[], const uint8_t priorities[],
548 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
549 uint16_t hwgrp_ids[nb_links];
552 RTE_SET_USED(priorities);
553 for (link = 0; link < nb_links; link++)
554 hwgrp_ids[link] = queues[link];
555 nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
557 return (int)nb_links;
561 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
562 uint8_t queues[], uint16_t nb_unlinks)
564 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
565 uint16_t hwgrp_ids[nb_unlinks];
568 for (unlink = 0; unlink < nb_unlinks; unlink++)
569 hwgrp_ids[unlink] = queues[unlink];
570 nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
572 return (int)nb_unlinks;
576 cn10k_sso_start(struct rte_eventdev *event_dev)
580 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
584 rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
585 cn10k_sso_hws_flush_events);
588 cn10k_sso_fp_fns_set(event_dev);
594 cn10k_sso_stop(struct rte_eventdev *event_dev)
596 cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
597 cn10k_sso_hws_flush_events);
601 cn10k_sso_close(struct rte_eventdev *event_dev)
603 return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
607 cn10k_sso_selftest(void)
609 return cnxk_sso_selftest(RTE_STR(event_cn10k));
613 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
614 const struct rte_eth_dev *eth_dev, uint32_t *caps)
618 RTE_SET_USED(event_dev);
619 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
621 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
623 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
624 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
625 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
626 RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
632 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
635 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
638 for (i = 0; i < dev->nb_event_ports; i++) {
639 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
640 ws->lookup_mem = lookup_mem;
641 ws->tstamp = tstmp_info;
646 cn10k_sso_rx_adapter_queue_add(
647 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
649 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
651 struct cn10k_eth_rxq *rxq;
656 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
660 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
664 rxq = eth_dev->data->rx_queues[0];
665 lookup_mem = rxq->lookup_mem;
666 tstmp_info = rxq->tstamp;
667 cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
668 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
674 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
675 const struct rte_eth_dev *eth_dev,
680 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
684 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
688 cn10k_sso_rx_adapter_vector_limits(
689 const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
690 struct rte_event_eth_rx_adapter_vector_limits *limits)
692 struct cnxk_eth_dev *cnxk_eth_dev;
696 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
700 cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
701 limits->log2_sz = true;
702 limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
703 limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
704 limits->min_timeout_ns =
705 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
706 limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
712 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
713 const struct rte_eth_dev *eth_dev, uint32_t *caps)
718 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
722 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
723 RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
729 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
730 const struct rte_eth_dev *eth_dev,
736 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
739 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
742 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
748 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
749 const struct rte_eth_dev *eth_dev,
755 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
758 return cn10k_sso_updt_tx_adptr_data(event_dev);
762 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
763 const struct rte_cryptodev *cdev, uint32_t *caps)
765 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
766 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
768 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
769 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
775 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
776 const struct rte_cryptodev *cdev,
777 int32_t queue_pair_id,
778 const struct rte_event *event)
780 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
784 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
785 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
787 dev->is_ca_internal_port = 1;
788 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
790 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
794 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
795 const struct rte_cryptodev *cdev,
796 int32_t queue_pair_id)
798 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
799 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
801 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
804 static struct eventdev_ops cn10k_sso_dev_ops = {
805 .dev_infos_get = cn10k_sso_info_get,
806 .dev_configure = cn10k_sso_dev_configure,
807 .queue_def_conf = cnxk_sso_queue_def_conf,
808 .queue_setup = cnxk_sso_queue_setup,
809 .queue_release = cnxk_sso_queue_release,
810 .port_def_conf = cnxk_sso_port_def_conf,
811 .port_setup = cn10k_sso_port_setup,
812 .port_release = cn10k_sso_port_release,
813 .port_link = cn10k_sso_port_link,
814 .port_unlink = cn10k_sso_port_unlink,
815 .timeout_ticks = cnxk_sso_timeout_ticks,
817 .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
818 .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
819 .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
820 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
821 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
823 .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
825 .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
826 .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
827 .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
829 .timer_adapter_caps_get = cnxk_tim_caps_get,
831 .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
832 .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
833 .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
835 .dump = cnxk_sso_dump,
836 .dev_start = cn10k_sso_start,
837 .dev_stop = cn10k_sso_stop,
838 .dev_close = cn10k_sso_close,
839 .dev_selftest = cn10k_sso_selftest,
843 cn10k_sso_init(struct rte_eventdev *event_dev)
845 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
848 if (RTE_CACHE_LINE_SIZE != 64) {
849 plt_err("Driver not compiled for CN10K");
855 plt_err("Failed to initialize platform model");
859 event_dev->dev_ops = &cn10k_sso_dev_ops;
860 /* For secondary processes, the primary has done all the work */
861 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
862 cn10k_sso_fp_fns_set(event_dev);
866 rc = cnxk_sso_init(event_dev);
870 cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
871 if (!dev->max_event_ports || !dev->max_event_queues) {
872 plt_err("Not enough eventdev resource queues=%d ports=%d",
873 dev->max_event_queues, dev->max_event_ports);
874 cnxk_sso_fini(event_dev);
878 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
879 event_dev->data->name, dev->max_event_queues,
880 dev->max_event_ports);
886 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
888 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
889 sizeof(struct cnxk_sso_evdev),
893 static const struct rte_pci_id cn10k_pci_sso_map[] = {
894 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
895 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
896 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
897 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
898 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
899 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
905 static struct rte_pci_driver cn10k_pci_sso = {
906 .id_table = cn10k_pci_sso_map,
907 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
908 .probe = cn10k_sso_probe,
909 .remove = cnxk_sso_remove,
912 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
913 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
914 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
915 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
916 CNXK_SSO_GGRP_QOS "=<string>"
917 CNXK_SSO_FORCE_BP "=1"
918 CN10K_SSO_GW_MODE "=<int>"
919 CNXK_TIM_DISABLE_NPA "=1"
920 CNXK_TIM_CHNK_SLOTS "=<int>"
921 CNXK_TIM_RINGS_LMT "=<int>"
922 CNXK_TIM_STATS_ENA "=1"
923 CNXK_TIM_EXT_CLK "=<string>");