drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                           \
  10         deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
  11
  12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                           \
  13         enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
  14
  15 static uint32_t
  16 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  17 {
  18         uint32_t wdata = 1;
  19
  20         if (dev->deq_tmo_ns)
  21                 wdata |= BIT(16);
  22
  23         switch (dev->gw_mode) {
  24         case CN10K_GW_MODE_NONE:
  25         default:
  26                 break;
  27         case CN10K_GW_MODE_PREF:
  28                 wdata |= BIT(19);
  29                 break;
  30         case CN10K_GW_MODE_PREF_WFE:
  31                 wdata |= BIT(20) | BIT(19);
  32                 break;
  33         }
  34
  35         return wdata;
  36 }
  37
  38 static void *
  39 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  40 {
  41         struct cnxk_sso_evdev *dev = arg;
  42         struct cn10k_sso_hws *ws;
  43
  44         /* Allocate event port memory */
  45         ws = rte_zmalloc("cn10k_ws",
  46                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  47                          RTE_CACHE_LINE_SIZE);
  48         if (ws == NULL) {
  49                 plt_err("Failed to alloc memory for port=%d", port_id);
  50                 return NULL;
  51         }
  52
  53         /* First cache line is reserved for cookie */
  54         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  55         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  56         ws->hws_id = port_id;
  57         ws->swtag_req = 0;
  58         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  59         ws->lmt_base = dev->sso.lmt_base;
  60
  61         return ws;
  62 }
  63
  64 static int
  65 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  66 {
  67         struct cnxk_sso_evdev *dev = arg;
  68         struct cn10k_sso_hws *ws = port;
  69
  70         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  71 }
  72
  73 static int
  74 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  75 {
  76         struct cnxk_sso_evdev *dev = arg;
  77         struct cn10k_sso_hws *ws = port;
  78
  79         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  80 }
  81
  82 static void
  83 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
  84 {
  85         struct cnxk_sso_evdev *dev = arg;
  86         struct cn10k_sso_hws *ws = hws;
  87         uint64_t val;
  88
  89         ws->grp_base = grp_base;
  90         ws->fc_mem = (uint64_t *)dev->fc_iova;
  91         ws->xaq_lmt = dev->xaq_lmt;
  92
  93         /* Set get_work timeout for HWS */
  94         val = NSEC2USEC(dev->deq_tmo_ns);
  95         val = val ? val - 1 : 0;
  96         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  97 }
  98
  99 static void
 100 cn10k_sso_hws_release(void *arg, void *hws)
 101 {
 102         struct cnxk_sso_evdev *dev = arg;
 103         struct cn10k_sso_hws *ws = hws;
 104         uint16_t i;
 105
 106         for (i = 0; i < dev->nb_event_queues; i++)
 107                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
 108         memset(ws, 0, sizeof(*ws));
 109 }
 110
 111 static void
 112 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 113                            cnxk_handle_event_t fn, void *arg)
 114 {
 115         struct cn10k_sso_hws *ws = hws;
 116         uint64_t cq_ds_cnt = 1;
 117         uint64_t aq_cnt = 1;
 118         uint64_t ds_cnt = 1;
 119         struct rte_event ev;
 120         uint64_t val, req;
 121
 122         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 123
 124         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 125         req = queue_id;     /* GGRP ID */
 126         req |= BIT_ULL(18); /* Grouped */
 127         req |= BIT_ULL(16); /* WAIT */
 128
 129         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 130         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 131         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 132         cq_ds_cnt &= 0x3FFF3FFF0000;
 133
 134         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 135                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 136                 cn10k_sso_hws_get_work_empty(
 137                         ws, &ev,
 138                         (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
 139                                 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
 140                 if (fn != NULL && ev.u64 != 0)
 141                         fn(arg, ev);
 142                 if (ev.sched_type != SSO_TT_EMPTY)
 143                         cnxk_sso_hws_swtag_flush(ws->base);
 144                 do {
 145                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 146                 } while (val & BIT_ULL(56));
 147                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 148                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 149                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 150                 /* Extract cq and ds count */
 151                 cq_ds_cnt &= 0x3FFF3FFF0000;
 152         }
 153
 154         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 155         rte_mb();
 156 }
 157
 158 static void
 159 cn10k_sso_hws_reset(void *arg, void *hws)
 160 {
 161         struct cnxk_sso_evdev *dev = arg;
 162         struct cn10k_sso_hws *ws = hws;
 163         uintptr_t base = ws->base;
 164         uint64_t pend_state;
 165         union {
 166                 __uint128_t wdata;
 167                 uint64_t u64[2];
 168         } gw;
 169         uint8_t pend_tt;
 170
 171         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 172         /* Wait till getwork/swtp/waitw/desched completes. */
 173         do {
 174                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 175         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 176                                BIT_ULL(56) | BIT_ULL(54)));
 177         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 178         if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 179                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 180                         cnxk_sso_hws_swtag_untag(base +
 181                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 182                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 183         }
 184
 185         /* Wait for desched to complete. */
 186         do {
 187                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 188         } while (pend_state & BIT_ULL(58));
 189
 190         switch (dev->gw_mode) {
 191         case CN10K_GW_MODE_PREF:
 192                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 193                         ;
 194                 break;
 195         case CN10K_GW_MODE_PREF_WFE:
 196                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
 197                        SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
 198                         continue;
 199                 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 200                 break;
 201         case CN10K_GW_MODE_NONE:
 202         default:
 203                 break;
 204         }
 205
 206         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 207             SSO_TT_EMPTY) {
 208                 plt_write64(BIT_ULL(16) | 1,
 209                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 210                 do {
 211                         roc_load_pair(gw.u64[0], gw.u64[1],
 212                                       ws->base + SSOW_LF_GWS_WQE0);
 213                 } while (gw.u64[0] & BIT_ULL(63));
 214                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 215                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 216                         if (pend_tt == SSO_TT_ATOMIC ||
 217                             pend_tt == SSO_TT_ORDERED)
 218                                 cnxk_sso_hws_swtag_untag(
 219                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 220                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 221                 }
 222         }
 223
 224         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 225         rte_mb();
 226 }
 227
 228 static void
 229 cn10k_sso_set_rsrc(void *arg)
 230 {
 231         struct cnxk_sso_evdev *dev = arg;
 232
 233         dev->max_event_ports = dev->sso.max_hws;
 234         dev->max_event_queues =
 235                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 236                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 237                               dev->sso.max_hwgrp;
 238 }
 239
 240 static int
 241 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 242 {
 243         struct cnxk_sso_evdev *dev = arg;
 244
 245         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 246 }
 247
 248 static int
 249 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 250 {
 251         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 252         int i;
 253
 254         if (dev->tx_adptr_data == NULL)
 255                 return 0;
 256
 257         for (i = 0; i < dev->nb_event_ports; i++) {
 258                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 259                 void *ws_cookie;
 260
 261                 ws_cookie = cnxk_sso_hws_get_cookie(ws);
 262                 ws_cookie = rte_realloc_socket(
 263                         ws_cookie,
 264                         sizeof(struct cnxk_sso_hws_cookie) +
 265                                 sizeof(struct cn10k_sso_hws) +
 266                                 dev->tx_adptr_data_sz,
 267                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 268                 if (ws_cookie == NULL)
 269                         return -ENOMEM;
 270                 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
 271                 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 272                        dev->tx_adptr_data_sz);
 273                 event_dev->data->ports[i] = ws;
 274         }
 275
 276         return 0;
 277 }
 278
 279 static void
 280 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 281 {
 282         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 283         const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
 284 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
 285                 NIX_RX_FASTPATH_MODES
 286 #undef R
 287         };
 288
 289         const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
 290 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
 291                 NIX_RX_FASTPATH_MODES
 292 #undef R
 293         };
 294
 295         const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
 296 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
 297                 NIX_RX_FASTPATH_MODES
 298 #undef R
 299         };
 300
 301         const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
 302 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
 303                 NIX_RX_FASTPATH_MODES
 304 #undef R
 305         };
 306
 307         const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
 308 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
 309                 NIX_RX_FASTPATH_MODES
 310 #undef R
 311         };
 312
 313         const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 314 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
 315                 NIX_RX_FASTPATH_MODES
 316 #undef R
 317         };
 318
 319         const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
 320 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
 321                 NIX_RX_FASTPATH_MODES
 322 #undef R
 323         };
 324
 325         const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 326 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
 327                 NIX_RX_FASTPATH_MODES
 328 #undef R
 329         };
 330
 331         const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
 332 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
 333
 334                 NIX_RX_FASTPATH_MODES
 335 #undef R
 336         };
 337
 338         const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 339 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
 340                         NIX_RX_FASTPATH_MODES
 341 #undef R
 342         };
 343
 344         const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
 345 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
 346                 NIX_RX_FASTPATH_MODES
 347 #undef R
 348         };
 349
 350         const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 351 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 352                 NIX_RX_FASTPATH_MODES
 353 #undef R
 354         };
 355
 356         const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 357 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
 358                 NIX_RX_FASTPATH_MODES
 359 #undef R
 360         };
 361
 362         const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 363 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
 364                 NIX_RX_FASTPATH_MODES
 365 #undef R
 366         };
 367
 368         const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 369 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
 370                 NIX_RX_FASTPATH_MODES
 371 #undef R
 372         };
 373
 374         const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 375 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
 376                 NIX_RX_FASTPATH_MODES
 377 #undef R
 378         };
 379
 380         /* Tx modes */
 381         const event_tx_adapter_enqueue_t
 382                 sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
 383 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name,
 384                         NIX_TX_FASTPATH_MODES
 385 #undef T
 386                 };
 387
 388         const event_tx_adapter_enqueue_t
 389                 sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
 390 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
 391                         NIX_TX_FASTPATH_MODES
 392 #undef T
 393                 };
 394
 395         event_dev->enqueue = cn10k_sso_hws_enq;
 396         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 397         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 398         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 399         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 400                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 401                                        sso_hws_deq_seg);
 402                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 403                                        sso_hws_deq_seg_burst);
 404                 if (dev->is_timeout_deq) {
 405                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 406                                                sso_hws_deq_tmo_seg);
 407                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 408                                                sso_hws_deq_tmo_seg_burst);
 409                 }
 410                 if (dev->is_ca_internal_port) {
 411                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 412                                                sso_hws_deq_ca_seg);
 413                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 414                                                sso_hws_deq_ca_seg_burst);
 415                 }
 416                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 417                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 418                                                sso_hws_deq_tmo_ca_seg);
 419                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 420                                                sso_hws_deq_tmo_ca_seg_burst);
 421                 }
 422         } else {
 423                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
 424                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 425                                        sso_hws_deq_burst);
 426                 if (dev->is_timeout_deq) {
 427                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 428                                                sso_hws_deq_tmo);
 429                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 430                                                sso_hws_deq_tmo_burst);
 431                 }
 432                 if (dev->is_ca_internal_port) {
 433                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 434                                                sso_hws_deq_ca);
 435                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 436                                                sso_hws_deq_ca_burst);
 437                 }
 438                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 439                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 440                                                sso_hws_deq_tmo_ca);
 441                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 442                                                sso_hws_deq_tmo_ca_burst);
 443                 }
 444         }
 445         event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 446
 447         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
 448                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 449                                        sso_hws_tx_adptr_enq_seg);
 450         else
 451                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 452                                        sso_hws_tx_adptr_enq);
 453
 454         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 455 }
 456
 457 static void
 458 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 459                    struct rte_event_dev_info *dev_info)
 460 {
 461         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 462
 463         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 464         cnxk_sso_info_get(dev, dev_info);
 465 }
 466
 467 static int
 468 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 469 {
 470         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 471         int rc;
 472
 473         rc = cnxk_sso_dev_validate(event_dev);
 474         if (rc < 0) {
 475                 plt_err("Invalid event device configuration");
 476                 return -EINVAL;
 477         }
 478
 479         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 480                                  dev->nb_event_queues);
 481         if (rc < 0) {
 482                 plt_err("Failed to initialize SSO resources");
 483                 return -ENODEV;
 484         }
 485
 486         rc = cnxk_sso_xaq_allocate(dev);
 487         if (rc < 0)
 488                 goto cnxk_rsrc_fini;
 489
 490         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 491                                     cn10k_sso_hws_setup);
 492         if (rc < 0)
 493                 goto cnxk_rsrc_fini;
 494
 495         /* Restore any prior port-queue mapping. */
 496         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 497
 498         dev->configured = 1;
 499         rte_mb();
 500
 501         return 0;
 502 cnxk_rsrc_fini:
 503         roc_sso_rsrc_fini(&dev->sso);
 504         dev->nb_event_ports = 0;
 505         return rc;
 506 }
 507
 508 static int
 509 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 510                      const struct rte_event_port_conf *port_conf)
 511 {
 512
 513         RTE_SET_USED(port_conf);
 514         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 515 }
 516
 517 static void
 518 cn10k_sso_port_release(void *port)
 519 {
 520         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 521         struct cnxk_sso_evdev *dev;
 522
 523         if (port == NULL)
 524                 return;
 525
 526         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 527         if (!gws_cookie->configured)
 528                 goto free;
 529
 530         cn10k_sso_hws_release(dev, port);
 531         memset(gws_cookie, 0, sizeof(*gws_cookie));
 532 free:
 533         rte_free(gws_cookie);
 534 }
 535
 536 static int
 537 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 538                     const uint8_t queues[], const uint8_t priorities[],
 539                     uint16_t nb_links)
 540 {
 541         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 542         uint16_t hwgrp_ids[nb_links];
 543         uint16_t link;
 544
 545         RTE_SET_USED(priorities);
 546         for (link = 0; link < nb_links; link++)
 547                 hwgrp_ids[link] = queues[link];
 548         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 549
 550         return (int)nb_links;
 551 }
 552
 553 static int
 554 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 555                       uint8_t queues[], uint16_t nb_unlinks)
 556 {
 557         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 558         uint16_t hwgrp_ids[nb_unlinks];
 559         uint16_t unlink;
 560
 561         for (unlink = 0; unlink < nb_unlinks; unlink++)
 562                 hwgrp_ids[unlink] = queues[unlink];
 563         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 564
 565         return (int)nb_unlinks;
 566 }
 567
 568 static int
 569 cn10k_sso_start(struct rte_eventdev *event_dev)
 570 {
 571         int rc;
 572
 573         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 574         if (rc < 0)
 575                 return rc;
 576
 577         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 578                             cn10k_sso_hws_flush_events);
 579         if (rc < 0)
 580                 return rc;
 581         cn10k_sso_fp_fns_set(event_dev);
 582
 583         return rc;
 584 }
 585
 586 static void
 587 cn10k_sso_stop(struct rte_eventdev *event_dev)
 588 {
 589         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 590                       cn10k_sso_hws_flush_events);
 591 }
 592
 593 static int
 594 cn10k_sso_close(struct rte_eventdev *event_dev)
 595 {
 596         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 597 }
 598
 599 static int
 600 cn10k_sso_selftest(void)
 601 {
 602         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 603 }
 604
 605 static int
 606 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 607                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 608 {
 609         int rc;
 610
 611         RTE_SET_USED(event_dev);
 612         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 613         if (rc)
 614                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 615         else
 616                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 617                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 618                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
 619                         RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
 620
 621         return 0;
 622 }
 623
 624 static void
 625 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 626                        void *tstmp_info)
 627 {
 628         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 629         int i;
 630
 631         for (i = 0; i < dev->nb_event_ports; i++) {
 632                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 633                 ws->lookup_mem = lookup_mem;
 634                 ws->tstamp = tstmp_info;
 635         }
 636 }
 637
 638 static int
 639 cn10k_sso_rx_adapter_queue_add(
 640         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 641         int32_t rx_queue_id,
 642         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 643 {
 644         struct cn10k_eth_rxq *rxq;
 645         void *lookup_mem;
 646         void *tstmp_info;
 647         int rc;
 648
 649         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 650         if (rc)
 651                 return -EINVAL;
 652
 653         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 654                                            queue_conf);
 655         if (rc)
 656                 return -EINVAL;
 657         rxq = eth_dev->data->rx_queues[0];
 658         lookup_mem = rxq->lookup_mem;
 659         tstmp_info = rxq->tstamp;
 660         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 661         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 662
 663         return 0;
 664 }
 665
 666 static int
 667 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 668                                const struct rte_eth_dev *eth_dev,
 669                                int32_t rx_queue_id)
 670 {
 671         int rc;
 672
 673         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 674         if (rc)
 675                 return -EINVAL;
 676
 677         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 678 }
 679
 680 static int
 681 cn10k_sso_rx_adapter_vector_limits(
 682         const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
 683         struct rte_event_eth_rx_adapter_vector_limits *limits)
 684 {
 685         struct cnxk_eth_dev *cnxk_eth_dev;
 686         int ret;
 687
 688         RTE_SET_USED(dev);
 689         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 690         if (ret)
 691                 return -ENOTSUP;
 692
 693         cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
 694         limits->log2_sz = true;
 695         limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
 696         limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
 697         limits->min_timeout_ns =
 698                 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
 699         limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
 700
 701         return 0;
 702 }
 703
 704 static int
 705 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 706                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 707 {
 708         int ret;
 709
 710         RTE_SET_USED(dev);
 711         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 712         if (ret)
 713                 *caps = 0;
 714         else
 715                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
 716                         RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
 717
 718         return 0;
 719 }
 720
 721 static void
 722 cn10k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)
 723 {
 724         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 725         struct cn10k_eth_txq *txq;
 726         struct roc_nix_sq *sq;
 727         int i;
 728
 729         if (tx_queue_id < 0) {
 730                 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
 731                         cn10k_sso_txq_fc_update(eth_dev, i);
 732         } else {
 733                 uint16_t sqes_per_sqb;
 734
 735                 sq = &cnxk_eth_dev->sqs[tx_queue_id];
 736                 txq = eth_dev->data->tx_queues[tx_queue_id];
 737                 sqes_per_sqb = 1U << txq->sqes_per_sqb_log2;
 738                 sq->nb_sqb_bufs_adj =
 739                         sq->nb_sqb_bufs -
 740                         RTE_ALIGN_MUL_CEIL(sq->nb_sqb_bufs, sqes_per_sqb) /
 741                                 sqes_per_sqb;
 742                 if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
 743                         sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc /
 744                                                 (sqes_per_sqb - 1));
 745                 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
 746                 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
 747         }
 748 }
 749
 750 static int
 751 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
 752                                const struct rte_eth_dev *eth_dev,
 753                                int32_t tx_queue_id)
 754 {
 755         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 756         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 757         uint64_t tx_offloads;
 758         int rc;
 759
 760         RTE_SET_USED(id);
 761         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
 762         if (rc < 0)
 763                 return rc;
 764
 765         /* Can't enable tstamp if all the ports don't have it enabled. */
 766         tx_offloads = cnxk_eth_dev->tx_offload_flags;
 767         if (dev->tx_adptr_configured) {
 768                 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 769                 uint8_t tstmp_ena =
 770                         !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 771
 772                 if (tstmp_ena && !tstmp_req)
 773                         dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 774                 else if (!tstmp_ena && tstmp_req)
 775                         tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 776         }
 777
 778         dev->tx_offloads |= tx_offloads;
 779         cn10k_sso_txq_fc_update(eth_dev, tx_queue_id);
 780         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 781         if (rc < 0)
 782                 return rc;
 783         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 784         dev->tx_adptr_configured = 1;
 785
 786         return 0;
 787 }
 788
 789 static int
 790 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
 791                                const struct rte_eth_dev *eth_dev,
 792                                int32_t tx_queue_id)
 793 {
 794         int rc;
 795
 796         RTE_SET_USED(id);
 797         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
 798         if (rc < 0)
 799                 return rc;
 800         return cn10k_sso_updt_tx_adptr_data(event_dev);
 801 }
 802
 803 static int
 804 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
 805                               const struct rte_cryptodev *cdev, uint32_t *caps)
 806 {
 807         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 808         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 809
 810         *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
 811                 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 812
 813         return 0;
 814 }
 815
 816 static int
 817 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
 818                             const struct rte_cryptodev *cdev,
 819                             int32_t queue_pair_id,
 820                             const struct rte_event *event)
 821 {
 822         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 823
 824         RTE_SET_USED(event);
 825
 826         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 827         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 828
 829         dev->is_ca_internal_port = 1;
 830         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 831
 832         return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
 833 }
 834
 835 static int
 836 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
 837                             const struct rte_cryptodev *cdev,
 838                             int32_t queue_pair_id)
 839 {
 840         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 841         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 842
 843         return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 844 }
 845
 846 static struct eventdev_ops cn10k_sso_dev_ops = {
 847         .dev_infos_get = cn10k_sso_info_get,
 848         .dev_configure = cn10k_sso_dev_configure,
 849         .queue_def_conf = cnxk_sso_queue_def_conf,
 850         .queue_setup = cnxk_sso_queue_setup,
 851         .queue_release = cnxk_sso_queue_release,
 852         .port_def_conf = cnxk_sso_port_def_conf,
 853         .port_setup = cn10k_sso_port_setup,
 854         .port_release = cn10k_sso_port_release,
 855         .port_link = cn10k_sso_port_link,
 856         .port_unlink = cn10k_sso_port_unlink,
 857         .timeout_ticks = cnxk_sso_timeout_ticks,
 858
 859         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 860         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 861         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 862         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 863         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 864
 865         .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
 866
 867         .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
 868         .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
 869         .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
 870
 871         .timer_adapter_caps_get = cnxk_tim_caps_get,
 872
 873         .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
 874         .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
 875         .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
 876
 877         .dump = cnxk_sso_dump,
 878         .dev_start = cn10k_sso_start,
 879         .dev_stop = cn10k_sso_stop,
 880         .dev_close = cn10k_sso_close,
 881         .dev_selftest = cn10k_sso_selftest,
 882 };
 883
 884 static int
 885 cn10k_sso_init(struct rte_eventdev *event_dev)
 886 {
 887         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 888         int rc;
 889
 890         if (RTE_CACHE_LINE_SIZE != 64) {
 891                 plt_err("Driver not compiled for CN10K");
 892                 return -EFAULT;
 893         }
 894
 895         rc = roc_plt_init();
 896         if (rc < 0) {
 897                 plt_err("Failed to initialize platform model");
 898                 return rc;
 899         }
 900
 901         event_dev->dev_ops = &cn10k_sso_dev_ops;
 902         /* For secondary processes, the primary has done all the work */
 903         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 904                 cn10k_sso_fp_fns_set(event_dev);
 905                 return 0;
 906         }
 907
 908         rc = cnxk_sso_init(event_dev);
 909         if (rc < 0)
 910                 return rc;
 911
 912         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 913         if (!dev->max_event_ports || !dev->max_event_queues) {
 914                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 915                         dev->max_event_queues, dev->max_event_ports);
 916                 cnxk_sso_fini(event_dev);
 917                 return -ENODEV;
 918         }
 919
 920         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 921                     event_dev->data->name, dev->max_event_queues,
 922                     dev->max_event_ports);
 923
 924         return 0;
 925 }
 926
 927 static int
 928 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 929 {
 930         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 931                                        sizeof(struct cnxk_sso_evdev),
 932                                        cn10k_sso_init);
 933 }
 934
 935 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 936         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 937         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 938         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 939         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 940         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 941         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 942         {
 943                 .vendor_id = 0,
 944         },
 945 };
 946
 947 static struct rte_pci_driver cn10k_pci_sso = {
 948         .id_table = cn10k_pci_sso_map,
 949         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 950         .probe = cn10k_sso_probe,
 951         .remove = cnxk_sso_remove,
 952 };
 953
 954 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 955 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 956 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 957 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 958                               CNXK_SSO_GGRP_QOS "=<string>"
 959                               CNXK_SSO_FORCE_BP "=1"
 960                               CN10K_SSO_GW_MODE "=<int>"
 961                               CNXK_TIM_DISABLE_NPA "=1"
 962                               CNXK_TIM_CHNK_SLOTS "=<int>"
 963                               CNXK_TIM_RINGS_LMT "=<int>"
 964                               CNXK_TIM_STATS_ENA "=1"
 965                               CNXK_TIM_EXT_CLK "=<string>");