1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn10k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
10 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
13 enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
16 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
23 switch (dev->gw_mode) {
24 case CN10K_GW_MODE_NONE:
27 case CN10K_GW_MODE_PREF:
30 case CN10K_GW_MODE_PREF_WFE:
31 wdata |= BIT(20) | BIT(19);
39 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
41 struct cnxk_sso_evdev *dev = arg;
42 struct cn10k_sso_hws *ws;
44 /* Allocate event port memory */
45 ws = rte_zmalloc("cn10k_ws",
46 sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
49 plt_err("Failed to alloc memory for port=%d", port_id);
53 /* First cache line is reserved for cookie */
54 ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
55 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
58 ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
59 ws->lmt_base = dev->sso.lmt_base;
65 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
67 struct cnxk_sso_evdev *dev = arg;
68 struct cn10k_sso_hws *ws = port;
70 return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
74 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
76 struct cnxk_sso_evdev *dev = arg;
77 struct cn10k_sso_hws *ws = port;
79 return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
83 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
85 struct cnxk_sso_evdev *dev = arg;
86 struct cn10k_sso_hws *ws = hws;
89 ws->grp_base = grp_base;
90 ws->fc_mem = (uint64_t *)dev->fc_iova;
91 ws->xaq_lmt = dev->xaq_lmt;
93 /* Set get_work timeout for HWS */
94 val = NSEC2USEC(dev->deq_tmo_ns);
95 val = val ? val - 1 : 0;
96 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
100 cn10k_sso_hws_release(void *arg, void *hws)
102 struct cnxk_sso_evdev *dev = arg;
103 struct cn10k_sso_hws *ws = hws;
106 for (i = 0; i < dev->nb_event_queues; i++)
107 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
108 memset(ws, 0, sizeof(*ws));
112 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
113 cnxk_handle_event_t fn, void *arg)
115 struct cn10k_sso_hws *ws = hws;
116 uint64_t cq_ds_cnt = 1;
122 plt_write64(0, base + SSO_LF_GGRP_QCTL);
124 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
125 req = queue_id; /* GGRP ID */
126 req |= BIT_ULL(18); /* Grouped */
127 req |= BIT_ULL(16); /* WAIT */
129 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
130 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
131 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
132 cq_ds_cnt &= 0x3FFF3FFF0000;
134 while (aq_cnt || cq_ds_cnt || ds_cnt) {
135 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
136 cn10k_sso_hws_get_work_empty(
138 (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
139 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
140 if (fn != NULL && ev.u64 != 0)
142 if (ev.sched_type != SSO_TT_EMPTY)
143 cnxk_sso_hws_swtag_flush(ws->base);
145 val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
146 } while (val & BIT_ULL(56));
147 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
148 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
149 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
150 /* Extract cq and ds count */
151 cq_ds_cnt &= 0x3FFF3FFF0000;
154 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
159 cn10k_sso_hws_reset(void *arg, void *hws)
161 struct cnxk_sso_evdev *dev = arg;
162 struct cn10k_sso_hws *ws = hws;
163 uintptr_t base = ws->base;
172 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
173 /* Wait till getwork/swtp/waitw/desched completes. */
175 /* Work in WQE0 is always consumed, unless its a SWTAG. */
176 pend_state = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
177 if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
182 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
183 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
184 BIT_ULL(56) | BIT_ULL(54)));
185 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
186 if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
187 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
188 cnxk_sso_hws_swtag_untag(base +
189 SSOW_LF_GWS_OP_SWTAG_UNTAG);
190 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
193 /* Wait for desched to complete. */
195 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
196 } while (pend_state & BIT_ULL(58));
198 switch (dev->gw_mode) {
199 case CN10K_GW_MODE_PREF:
200 case CN10K_GW_MODE_PREF_WFE:
201 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
204 case CN10K_GW_MODE_NONE:
209 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
211 plt_write64(BIT_ULL(16) | 1,
212 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
214 roc_load_pair(gw.u64[0], gw.u64[1],
215 ws->base + SSOW_LF_GWS_WQE0);
216 } while (gw.u64[0] & BIT_ULL(63));
217 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
218 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
219 if (pend_tt == SSO_TT_ATOMIC ||
220 pend_tt == SSO_TT_ORDERED)
221 cnxk_sso_hws_swtag_untag(
222 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
223 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
227 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
232 cn10k_sso_set_rsrc(void *arg)
234 struct cnxk_sso_evdev *dev = arg;
236 dev->max_event_ports = dev->sso.max_hws;
237 dev->max_event_queues =
238 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
239 RTE_EVENT_MAX_QUEUES_PER_DEV :
244 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
246 struct cnxk_sso_evdev *dev = arg;
248 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
252 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
254 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
257 if (dev->tx_adptr_data == NULL)
260 for (i = 0; i < dev->nb_event_ports; i++) {
261 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
264 ws_cookie = cnxk_sso_hws_get_cookie(ws);
265 ws_cookie = rte_realloc_socket(
267 sizeof(struct cnxk_sso_hws_cookie) +
268 sizeof(struct cn10k_sso_hws) +
269 dev->tx_adptr_data_sz,
270 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
271 if (ws_cookie == NULL)
273 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
274 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
275 dev->tx_adptr_data_sz);
276 event_dev->data->ports[i] = ws;
283 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
285 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
286 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
287 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
288 NIX_RX_FASTPATH_MODES
292 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
293 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
294 NIX_RX_FASTPATH_MODES
298 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
299 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
300 NIX_RX_FASTPATH_MODES
304 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
305 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
306 NIX_RX_FASTPATH_MODES
310 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
311 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
312 NIX_RX_FASTPATH_MODES
316 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
317 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
318 NIX_RX_FASTPATH_MODES
322 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
323 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
324 NIX_RX_FASTPATH_MODES
328 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
329 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
330 NIX_RX_FASTPATH_MODES
334 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
335 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
337 NIX_RX_FASTPATH_MODES
341 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
342 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
343 NIX_RX_FASTPATH_MODES
347 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
348 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
349 NIX_RX_FASTPATH_MODES
353 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
354 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
355 NIX_RX_FASTPATH_MODES
359 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
360 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
361 NIX_RX_FASTPATH_MODES
365 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
366 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
367 NIX_RX_FASTPATH_MODES
371 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
372 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
373 NIX_RX_FASTPATH_MODES
377 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
378 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
379 NIX_RX_FASTPATH_MODES
384 const event_tx_adapter_enqueue_t
385 sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
386 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name,
387 NIX_TX_FASTPATH_MODES
391 const event_tx_adapter_enqueue_t
392 sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
393 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
394 NIX_TX_FASTPATH_MODES
398 event_dev->enqueue = cn10k_sso_hws_enq;
399 event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
400 event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
401 event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
402 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
403 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
405 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
406 sso_hws_deq_seg_burst);
407 if (dev->is_timeout_deq) {
408 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
409 sso_hws_deq_tmo_seg);
410 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
411 sso_hws_deq_tmo_seg_burst);
413 if (dev->is_ca_internal_port) {
414 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
416 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
417 sso_hws_deq_ca_seg_burst);
419 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
420 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
421 sso_hws_deq_tmo_ca_seg);
422 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
423 sso_hws_deq_tmo_ca_seg_burst);
426 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
427 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
429 if (dev->is_timeout_deq) {
430 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
432 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
433 sso_hws_deq_tmo_burst);
435 if (dev->is_ca_internal_port) {
436 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
438 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
439 sso_hws_deq_ca_burst);
441 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
442 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
444 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
445 sso_hws_deq_tmo_ca_burst);
448 event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
450 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
451 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
452 sso_hws_tx_adptr_enq_seg);
454 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
455 sso_hws_tx_adptr_enq);
457 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
461 cn10k_sso_info_get(struct rte_eventdev *event_dev,
462 struct rte_event_dev_info *dev_info)
464 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
466 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
467 cnxk_sso_info_get(dev, dev_info);
471 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
473 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
476 rc = cnxk_sso_dev_validate(event_dev);
478 plt_err("Invalid event device configuration");
482 rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
483 dev->nb_event_queues);
485 plt_err("Failed to initialize SSO resources");
489 rc = cnxk_sso_xaq_allocate(dev);
493 rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
494 cn10k_sso_hws_setup);
498 /* Restore any prior port-queue mapping. */
499 cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
506 roc_sso_rsrc_fini(&dev->sso);
507 dev->nb_event_ports = 0;
512 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
513 const struct rte_event_port_conf *port_conf)
516 RTE_SET_USED(port_conf);
517 return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
521 cn10k_sso_port_release(void *port)
523 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
524 struct cnxk_sso_evdev *dev;
529 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
530 if (!gws_cookie->configured)
533 cn10k_sso_hws_release(dev, port);
534 memset(gws_cookie, 0, sizeof(*gws_cookie));
536 rte_free(gws_cookie);
540 cn10k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,
541 rte_eventdev_port_flush_t flush_cb, void *args)
543 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
544 struct cn10k_sso_hws *ws = port;
550 /* Work in WQE0 is always consumed, unless its a SWTAG. */
551 ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
552 if (ptag & (BIT_ULL(62) | BIT_ULL(54)) || ws->swtag_req)
555 ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
557 (BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54)));
559 cn10k_sso_hws_get_work_empty(ws, &ev,
560 (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
561 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
562 if (is_pend && ev.u64) {
564 flush_cb(event_dev->data->dev_id, ev, args);
565 cnxk_sso_hws_swtag_flush(ws->base);
568 /* Check if we have work in PRF_WQE0, if so extract it. */
569 switch (dev->gw_mode) {
570 case CN10K_GW_MODE_PREF:
571 case CN10K_GW_MODE_PREF_WFE:
572 while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) &
576 case CN10K_GW_MODE_NONE:
581 if (CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0)) !=
583 plt_write64(BIT_ULL(16) | 1,
584 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
585 cn10k_sso_hws_get_work_empty(
587 (NIX_RX_OFFLOAD_MAX - 1) | NIX_RX_REAS_F |
588 NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F);
591 flush_cb(event_dev->data->dev_id, ev, args);
592 cnxk_sso_hws_swtag_flush(ws->base);
596 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
600 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
601 const uint8_t queues[], const uint8_t priorities[],
604 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
605 uint16_t hwgrp_ids[nb_links];
608 RTE_SET_USED(priorities);
609 for (link = 0; link < nb_links; link++)
610 hwgrp_ids[link] = queues[link];
611 nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
613 return (int)nb_links;
617 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
618 uint8_t queues[], uint16_t nb_unlinks)
620 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
621 uint16_t hwgrp_ids[nb_unlinks];
624 for (unlink = 0; unlink < nb_unlinks; unlink++)
625 hwgrp_ids[unlink] = queues[unlink];
626 nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
628 return (int)nb_unlinks;
632 cn10k_sso_start(struct rte_eventdev *event_dev)
636 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
640 rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
641 cn10k_sso_hws_flush_events);
644 cn10k_sso_fp_fns_set(event_dev);
650 cn10k_sso_stop(struct rte_eventdev *event_dev)
652 cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
653 cn10k_sso_hws_flush_events);
657 cn10k_sso_close(struct rte_eventdev *event_dev)
659 return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
663 cn10k_sso_selftest(void)
665 return cnxk_sso_selftest(RTE_STR(event_cn10k));
669 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
670 const struct rte_eth_dev *eth_dev, uint32_t *caps)
674 RTE_SET_USED(event_dev);
675 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
677 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
679 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
680 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
681 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
682 RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
688 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
691 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
694 for (i = 0; i < dev->nb_event_ports; i++) {
695 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
696 ws->lookup_mem = lookup_mem;
697 ws->tstamp = tstmp_info;
702 cn10k_sso_rx_adapter_queue_add(
703 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
705 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
707 struct cn10k_eth_rxq *rxq;
712 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
716 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
720 rxq = eth_dev->data->rx_queues[0];
721 lookup_mem = rxq->lookup_mem;
722 tstmp_info = rxq->tstamp;
723 cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
724 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
730 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
731 const struct rte_eth_dev *eth_dev,
736 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
740 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
744 cn10k_sso_rx_adapter_vector_limits(
745 const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
746 struct rte_event_eth_rx_adapter_vector_limits *limits)
748 struct cnxk_eth_dev *cnxk_eth_dev;
752 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
756 cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
757 limits->log2_sz = true;
758 limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
759 limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
760 limits->min_timeout_ns =
761 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
762 limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
768 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
769 const struct rte_eth_dev *eth_dev, uint32_t *caps)
774 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
778 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
779 RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
785 cn10k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)
787 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
788 struct cn10k_eth_txq *txq;
789 struct roc_nix_sq *sq;
792 if (tx_queue_id < 0) {
793 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
794 cn10k_sso_txq_fc_update(eth_dev, i);
796 uint16_t sqes_per_sqb;
798 sq = &cnxk_eth_dev->sqs[tx_queue_id];
799 txq = eth_dev->data->tx_queues[tx_queue_id];
800 sqes_per_sqb = 1U << txq->sqes_per_sqb_log2;
801 sq->nb_sqb_bufs_adj =
803 RTE_ALIGN_MUL_CEIL(sq->nb_sqb_bufs, sqes_per_sqb) /
805 if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
806 sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc /
808 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
809 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
814 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
815 const struct rte_eth_dev *eth_dev,
818 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
819 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
820 uint64_t tx_offloads;
824 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
828 /* Can't enable tstamp if all the ports don't have it enabled. */
829 tx_offloads = cnxk_eth_dev->tx_offload_flags;
830 if (dev->tx_adptr_configured) {
831 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
833 !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
835 if (tstmp_ena && !tstmp_req)
836 dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
837 else if (!tstmp_ena && tstmp_req)
838 tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
841 dev->tx_offloads |= tx_offloads;
842 cn10k_sso_txq_fc_update(eth_dev, tx_queue_id);
843 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
846 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
847 dev->tx_adptr_configured = 1;
853 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
854 const struct rte_eth_dev *eth_dev,
860 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
863 return cn10k_sso_updt_tx_adptr_data(event_dev);
867 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
868 const struct rte_cryptodev *cdev, uint32_t *caps)
870 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
871 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
873 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
874 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
880 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
881 const struct rte_cryptodev *cdev,
882 int32_t queue_pair_id,
883 const struct rte_event *event)
885 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
889 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
890 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
892 dev->is_ca_internal_port = 1;
893 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
895 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
899 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
900 const struct rte_cryptodev *cdev,
901 int32_t queue_pair_id)
903 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
904 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
906 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
909 static struct eventdev_ops cn10k_sso_dev_ops = {
910 .dev_infos_get = cn10k_sso_info_get,
911 .dev_configure = cn10k_sso_dev_configure,
912 .queue_def_conf = cnxk_sso_queue_def_conf,
913 .queue_setup = cnxk_sso_queue_setup,
914 .queue_release = cnxk_sso_queue_release,
915 .port_def_conf = cnxk_sso_port_def_conf,
916 .port_setup = cn10k_sso_port_setup,
917 .port_release = cn10k_sso_port_release,
918 .port_quiesce = cn10k_sso_port_quiesce,
919 .port_link = cn10k_sso_port_link,
920 .port_unlink = cn10k_sso_port_unlink,
921 .timeout_ticks = cnxk_sso_timeout_ticks,
923 .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
924 .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
925 .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
926 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
927 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
929 .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
931 .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
932 .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
933 .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
935 .timer_adapter_caps_get = cnxk_tim_caps_get,
937 .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
938 .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
939 .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
941 .dump = cnxk_sso_dump,
942 .dev_start = cn10k_sso_start,
943 .dev_stop = cn10k_sso_stop,
944 .dev_close = cn10k_sso_close,
945 .dev_selftest = cn10k_sso_selftest,
949 cn10k_sso_init(struct rte_eventdev *event_dev)
951 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
954 if (RTE_CACHE_LINE_SIZE != 64) {
955 plt_err("Driver not compiled for CN10K");
961 plt_err("Failed to initialize platform model");
965 event_dev->dev_ops = &cn10k_sso_dev_ops;
966 /* For secondary processes, the primary has done all the work */
967 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
968 cn10k_sso_fp_fns_set(event_dev);
972 rc = cnxk_sso_init(event_dev);
976 cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
977 if (!dev->max_event_ports || !dev->max_event_queues) {
978 plt_err("Not enough eventdev resource queues=%d ports=%d",
979 dev->max_event_queues, dev->max_event_ports);
980 cnxk_sso_fini(event_dev);
984 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
985 event_dev->data->name, dev->max_event_queues,
986 dev->max_event_ports);
992 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
994 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
995 sizeof(struct cnxk_sso_evdev),
999 static const struct rte_pci_id cn10k_pci_sso_map[] = {
1000 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1001 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1002 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1003 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1004 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1005 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1011 static struct rte_pci_driver cn10k_pci_sso = {
1012 .id_table = cn10k_pci_sso_map,
1013 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1014 .probe = cn10k_sso_probe,
1015 .remove = cnxk_sso_remove,
1018 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
1019 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
1020 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
1021 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
1022 CNXK_SSO_GGRP_QOS "=<string>"
1023 CNXK_SSO_FORCE_BP "=1"
1024 CN10K_SSO_GW_MODE "=<int>"
1025 CNXK_TIM_DISABLE_NPA "=1"
1026 CNXK_TIM_CHNK_SLOTS "=<int>"
1027 CNXK_TIM_RINGS_LMT "=<int>"
1028 CNXK_TIM_STATS_ENA "=1"
1029 CNXK_TIM_EXT_CLK "=<string>");