drivers/event/cnxk/cn10k_worker.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CN10K_WORKER_H__
   6 #define __CN10K_WORKER_H__
   7
   8 #include <rte_vect.h>
   9
  10 #include "cnxk_ethdev.h"
  11 #include "cnxk_eventdev.h"
  12 #include "cnxk_worker.h"
  13 #include "cn10k_cryptodev_ops.h"
  14
  15 #include "cn10k_ethdev.h"
  16 #include "cn10k_rx.h"
  17 #include "cn10k_tx.h"
  18
  19 /* SSO Operations */
  20
  21 static __rte_always_inline uint8_t
  22 cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
  23 {
  24         const uint32_t tag = (uint32_t)ev->event;
  25         const uint8_t new_tt = ev->sched_type;
  26         const uint64_t event_ptr = ev->u64;
  27         const uint16_t grp = ev->queue_id;
  28
  29         rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
  30         if (ws->xaq_lmt <= *ws->fc_mem)
  31                 return 0;
  32
  33         cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]);
  34         return 1;
  35 }
  36
  37 static __rte_always_inline void
  38 cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)
  39 {
  40         const uint32_t tag = (uint32_t)ev->event;
  41         const uint8_t new_tt = ev->sched_type;
  42         const uint8_t cur_tt =
  43                 CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0));
  44
  45         /* CNXK model
  46          * cur_tt/new_tt     SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
  47          *
  48          * SSO_TT_ORDERED        norm           norm             untag
  49          * SSO_TT_ATOMIC         norm           norm               untag
  50          * SSO_TT_UNTAGGED       norm           norm             NOOP
  51          */
  52
  53         if (new_tt == SSO_TT_UNTAGGED) {
  54                 if (cur_tt != SSO_TT_UNTAGGED)
  55                         cnxk_sso_hws_swtag_untag(ws->base +
  56                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
  57         } else {
  58                 cnxk_sso_hws_swtag_norm(tag, new_tt,
  59                                         ws->base + SSOW_LF_GWS_OP_SWTAG_NORM);
  60         }
  61         ws->swtag_req = 1;
  62 }
  63
  64 static __rte_always_inline void
  65 cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,
  66                         const uint16_t grp)
  67 {
  68         const uint32_t tag = (uint32_t)ev->event;
  69         const uint8_t new_tt = ev->sched_type;
  70
  71         plt_write64(ev->u64, ws->base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
  72         cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
  73                                    ws->base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
  74 }
  75
  76 static __rte_always_inline void
  77 cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
  78                             const struct rte_event *ev)
  79 {
  80         const uint8_t grp = ev->queue_id;
  81
  82         /* Group hasn't changed, Use SWTAG to forward the event */
  83         if (CNXK_GRP_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0)) == grp)
  84                 cn10k_sso_hws_fwd_swtag(ws, ev);
  85         else
  86                 /*
  87                  * Group has been changed for group based work pipelining,
  88                  * Use deschedule/add_work operation to transfer the event to
  89                  * new group/core
  90                  */
  91                 cn10k_sso_hws_fwd_group(ws, ev, grp);
  92 }
  93
  94 static __rte_always_inline void
  95 cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
  96                   const uint32_t tag, const uint32_t flags,
  97                   const void *const lookup_mem)
  98 {
  99         const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 100                                    (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 101
 102         cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
 103                               (struct rte_mbuf *)mbuf, lookup_mem,
 104                               mbuf_init | ((uint64_t)port_id) << 48, flags);
 105 }
 106
 107 static __rte_always_inline void
 108 cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
 109                    void *lookup_mem, void *tstamp, uintptr_t lbase)
 110 {
 111         uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 112                              (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 113         struct rte_event_vector *vec;
 114         uint64_t aura_handle, laddr;
 115         uint16_t nb_mbufs, non_vec;
 116         uint16_t lmt_id, d_off;
 117         struct rte_mbuf *mbuf;
 118         uint8_t loff = 0;
 119         uint64_t sa_base;
 120         uint64_t **wqe;
 121
 122         mbuf_init |= ((uint64_t)port_id) << 48;
 123         vec = (struct rte_event_vector *)vwqe;
 124         wqe = vec->u64s;
 125
 126         nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
 127         nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,
 128                                               flags | NIX_RX_VWQE_F, lookup_mem,
 129                                               tstamp, lbase);
 130         wqe += nb_mbufs;
 131         non_vec = vec->nb_elem - nb_mbufs;
 132
 133         if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
 134                 mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -
 135                                            sizeof(struct rte_mbuf));
 136                 /* Pick first mbuf's aura handle assuming all
 137                  * mbufs are from a vec and are from same RQ.
 138                  */
 139                 aura_handle = mbuf->pool->pool_id;
 140                 ROC_LMT_BASE_ID_GET(lbase, lmt_id);
 141                 laddr = lbase;
 142                 laddr += 8;
 143                 d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);
 144                 d_off += (mbuf_init & 0xFFFF);
 145                 sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
 146                 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
 147         }
 148
 149         while (non_vec) {
 150                 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
 151                 uint64_t tstamp_ptr;
 152
 153                 mbuf = (struct rte_mbuf *)((char *)cqe -
 154                                            sizeof(struct rte_mbuf));
 155
 156                 /* Translate meta to mbuf */
 157                 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 158                         const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
 159
 160                         mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,
 161                                                        &loff, mbuf, d_off);
 162                 }
 163
 164                 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
 165                                       mbuf_init, flags);
 166                 /* Extracting tstamp, if PTP enabled*/
 167                 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +
 168                                            CNXK_SSO_WQE_SG_PTR);
 169                 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
 170                                         flags & NIX_RX_OFFLOAD_TSTAMP_F,
 171                                         flags & NIX_RX_MULTI_SEG_F,
 172                                         (uint64_t *)tstamp_ptr);
 173                 wqe[0] = (uint64_t *)mbuf;
 174                 non_vec--;
 175                 wqe++;
 176         }
 177
 178         /* Free remaining meta buffers if any */
 179         if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
 180                 nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);
 181                 plt_io_wmb();
 182         }
 183 }
 184
 185 static __rte_always_inline uint16_t
 186 cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
 187                        const uint32_t flags, void *lookup_mem)
 188 {
 189         union {
 190                 __uint128_t get_work;
 191                 uint64_t u64[2];
 192         } gw;
 193         uint64_t tstamp_ptr;
 194         uint64_t mbuf;
 195
 196         gw.get_work = ws->gw_wdata;
 197 #if defined(RTE_ARCH_ARM64) && !defined(__clang__)
 198         asm volatile(
 199                 PLT_CPU_FEATURE_PREAMBLE
 200                 "caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
 201                 "sub %[mbuf], %H[wdata], #0x80                          \n"
 202                 : [wdata] "+r"(gw.get_work), [mbuf] "=&r"(mbuf)
 203                 : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
 204                 : "memory");
 205 #else
 206         plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 207         do {
 208                 roc_load_pair(gw.u64[0], gw.u64[1],
 209                               ws->base + SSOW_LF_GWS_WQE0);
 210         } while (gw.u64[0] & BIT_ULL(63));
 211         mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
 212 #endif
 213         gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
 214                     (gw.u64[0] & (0x3FFull << 36)) << 4 |
 215                     (gw.u64[0] & 0xffffffff);
 216
 217         if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
 218                 if ((flags & CPT_RX_WQE_F) &&
 219                     (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 220                      RTE_EVENT_TYPE_CRYPTODEV)) {
 221                         gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
 222                 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 223                            RTE_EVENT_TYPE_ETHDEV) {
 224                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 225
 226                         if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 227                                 struct rte_mbuf *m;
 228                                 uintptr_t sa_base;
 229                                 uint64_t iova = 0;
 230                                 uint8_t loff = 0;
 231                                 uint16_t d_off;
 232                                 uint64_t cq_w1;
 233
 234                                 m = (struct rte_mbuf *)mbuf;
 235                                 d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;
 236                                 d_off += RTE_PKTMBUF_HEADROOM;
 237
 238                                 cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
 239
 240                                 sa_base = cnxk_nix_sa_base_get(port,
 241                                                                lookup_mem);
 242                                 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
 243
 244                                 mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(cq_w1,
 245                                                 sa_base, (uintptr_t)&iova,
 246                                                 &loff, (struct rte_mbuf *)mbuf,
 247                                                 d_off);
 248                                 if (loff)
 249                                         roc_npa_aura_op_free(m->pool->pool_id,
 250                                                              0, iova);
 251
 252                         }
 253
 254                         gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 255                         cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 256                                           gw.u64[0] & 0xFFFFF, flags,
 257                                           lookup_mem);
 258                         /* Extracting tstamp, if PTP enabled*/
 259                         tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
 260                                                             gw.u64[1]) +
 261                                                    CNXK_SSO_WQE_SG_PTR);
 262                         cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
 263                                                 ws->tstamp,
 264                                                 flags & NIX_RX_OFFLOAD_TSTAMP_F,
 265                                                 flags & NIX_RX_MULTI_SEG_F,
 266                                                 (uint64_t *)tstamp_ptr);
 267                         gw.u64[1] = mbuf;
 268                 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 269                            RTE_EVENT_TYPE_ETHDEV_VECTOR) {
 270                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 271                         __uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];
 272
 273                         vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |
 274                                    ((vwqe_hdr & 0xFFFF) << 48) |
 275                                    ((uint64_t)port << 32);
 276                         *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
 277                         cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
 278                                            ws->tstamp, ws->lmt_base);
 279                 }
 280         }
 281
 282         ev->event = gw.u64[0];
 283         ev->u64 = gw.u64[1];
 284
 285         return !!gw.u64[1];
 286 }
 287
 288 /* Used in cleaning up workslot. */
 289 static __rte_always_inline uint16_t
 290 cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)
 291 {
 292         union {
 293                 __uint128_t get_work;
 294                 uint64_t u64[2];
 295         } gw;
 296         uint64_t mbuf;
 297
 298 #ifdef RTE_ARCH_ARM64
 299         asm volatile(PLT_CPU_FEATURE_PREAMBLE
 300                      "          ldp %[tag], %[wqp], [%[tag_loc]]        \n"
 301                      "          tbz %[tag], 63, done%=                  \n"
 302                      "          sevl                                    \n"
 303                      "rty%=:    wfe                                     \n"
 304                      "          ldp %[tag], %[wqp], [%[tag_loc]]        \n"
 305                      "          tbnz %[tag], 63, rty%=                  \n"
 306                      "done%=:   dmb ld                                  \n"
 307                      "          sub %[mbuf], %[wqp], #0x80              \n"
 308                      : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
 309                        [mbuf] "=&r"(mbuf)
 310                      : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0)
 311                      : "memory");
 312 #else
 313         do {
 314                 roc_load_pair(gw.u64[0], gw.u64[1],
 315                               ws->base + SSOW_LF_GWS_WQE0);
 316         } while (gw.u64[0] & BIT_ULL(63));
 317         mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
 318 #endif
 319
 320         gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
 321                     (gw.u64[0] & (0x3FFull << 36)) << 4 |
 322                     (gw.u64[0] & 0xffffffff);
 323
 324         if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
 325                 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 326                     RTE_EVENT_TYPE_ETHDEV) {
 327                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 328
 329                         gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 330                         cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 331                                           gw.u64[0] & 0xFFFFF, 0, NULL);
 332                         gw.u64[1] = mbuf;
 333                 }
 334         }
 335
 336         ev->event = gw.u64[0];
 337         ev->u64 = gw.u64[1];
 338
 339         return !!gw.u64[1];
 340 }
 341
 342 /* CN10K Fastpath functions. */
 343 uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);
 344 uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,
 345                                            const struct rte_event ev[],
 346                                            uint16_t nb_events);
 347 uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
 348                                                const struct rte_event ev[],
 349                                                uint16_t nb_events);
 350 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
 351                                                const struct rte_event ev[],
 352                                                uint16_t nb_events);
 353 uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
 354                                         uint16_t nb_events);
 355
 356 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
 357         uint16_t __rte_hot cn10k_sso_hws_deq_##name(                           \
 358                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 359         uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name(                     \
 360                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 361                 uint64_t timeout_ticks);                                       \
 362         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name(                       \
 363                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 364         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name(                 \
 365                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 366                 uint64_t timeout_ticks);                                       \
 367         uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name(                        \
 368                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 369         uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name(                  \
 370                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 371                 uint64_t timeout_ticks);                                       \
 372         uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name(                       \
 373                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 374         uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name(                 \
 375                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 376                 uint64_t timeout_ticks);                                       \
 377         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name(                   \
 378                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 379         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name(             \
 380                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 381                 uint64_t timeout_ticks);                                       \
 382         uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name(                    \
 383                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 384         uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name(              \
 385                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 386                 uint64_t timeout_ticks);
 387
 388 NIX_RX_FASTPATH_MODES
 389 #undef R
 390
 391 static __rte_always_inline struct cn10k_eth_txq *
 392 cn10k_sso_hws_xtract_meta(struct rte_mbuf *m,
 393                           const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])
 394 {
 395         return (struct cn10k_eth_txq *)
 396                 txq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];
 397 }
 398
 399 static __rte_always_inline void
 400 cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
 401                         uint64_t *cmd, uint16_t lmt_id, uintptr_t lmt_addr,
 402                         uint8_t sched_type, uintptr_t base,
 403                         const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
 404                         const uint32_t flags)
 405 {
 406         uint16_t port[4], queue[4];
 407         struct cn10k_eth_txq *txq;
 408         uint16_t i, j;
 409         uintptr_t pa;
 410
 411         for (i = 0; i < nb_mbufs; i += 4) {
 412                 port[0] = mbufs[i]->port;
 413                 port[1] = mbufs[i + 1]->port;
 414                 port[2] = mbufs[i + 2]->port;
 415                 port[3] = mbufs[i + 3]->port;
 416
 417                 queue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);
 418                 queue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);
 419                 queue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);
 420                 queue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);
 421
 422                 if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
 423                     ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
 424
 425                         for (j = 0; j < 4; j++) {
 426                                 uint8_t lnum = 0, loff = 0, shft = 0;
 427                                 struct rte_mbuf *m = mbufs[i + j];
 428                                 uintptr_t laddr;
 429                                 uint16_t segdw;
 430                                 bool sec;
 431
 432                                 txq = (struct cn10k_eth_txq *)
 433                                         txq_data[port[j]][queue[j]];
 434                                 cn10k_nix_tx_skeleton(txq, cmd, flags);
 435                                 /* Perform header writes before barrier
 436                                  * for TSO
 437                                  */
 438                                 if (flags & NIX_TX_OFFLOAD_TSO_F)
 439                                         cn10k_nix_xmit_prepare_tso(m, flags);
 440
 441                                 cn10k_nix_xmit_prepare(m, cmd, flags,
 442                                                        txq->lso_tun_fmt, &sec);
 443
 444                                 laddr = lmt_addr;
 445                                 /* Prepare CPT instruction and get nixtx addr if
 446                                  * it is for CPT on same lmtline.
 447                                  */
 448                                 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 449                                         cn10k_nix_prep_sec(m, cmd, &laddr,
 450                                                            lmt_addr, &lnum,
 451                                                            &loff, &shft,
 452                                                            txq->sa_base, flags);
 453
 454                                 /* Move NIX desc to LMT/NIXTX area */
 455                                 cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
 456
 457                                 if (flags & NIX_TX_MULTI_SEG_F) {
 458                                         segdw = cn10k_nix_prepare_mseg(m,
 459                                                 (uint64_t *)laddr, flags);
 460                                 } else {
 461                                         segdw = cn10k_nix_tx_ext_subs(flags) +
 462                                                 2;
 463                                 }
 464
 465                                 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 466                                         pa = txq->cpt_io_addr | 3 << 4;
 467                                 else
 468                                         pa = txq->io_addr | ((segdw - 1) << 4);
 469
 470                                 if (!sched_type)
 471                                         roc_sso_hws_head_wait(base +
 472                                                               SSOW_LF_GWS_TAG);
 473
 474                                 roc_lmt_submit_steorl(lmt_id, pa);
 475                         }
 476                 } else {
 477                         txq = (struct cn10k_eth_txq *)
 478                                 txq_data[port[0]][queue[0]];
 479                         cn10k_nix_xmit_pkts_vector(txq, &mbufs[i], 4, cmd, base
 480                                         + SSOW_LF_GWS_TAG,
 481                                                    flags | NIX_TX_VWQE_F);
 482                 }
 483         }
 484 }
 485
 486 static __rte_always_inline uint16_t
 487 cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
 488                        uint64_t *cmd,
 489                        const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
 490                        const uint32_t flags)
 491 {
 492         uint8_t lnum = 0, loff = 0, shft = 0;
 493         struct cn10k_eth_txq *txq;
 494         uint16_t ref_cnt, segdw;
 495         struct rte_mbuf *m;
 496         uintptr_t lmt_addr;
 497         uintptr_t c_laddr;
 498         uint16_t lmt_id;
 499         uintptr_t pa;
 500         bool sec;
 501
 502         lmt_addr = ws->lmt_base;
 503         ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
 504         c_laddr = lmt_addr;
 505
 506         if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
 507                 struct rte_mbuf **mbufs = ev->vec->mbufs;
 508                 uint64_t meta = *(uint64_t *)ev->vec;
 509
 510                 if (meta & BIT(31)) {
 511                         txq = (struct cn10k_eth_txq *)
 512                                 txq_data[meta >> 32][meta >> 48];
 513
 514                         cn10k_nix_xmit_pkts_vector(
 515                                 txq, mbufs, meta & 0xFFFF, cmd,
 516                                 ws->tx_base + SSOW_LF_GWS_TAG,
 517                                 flags | NIX_TX_VWQE_F);
 518                 } else {
 519                         cn10k_sso_vwqe_split_tx(
 520                                 mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,
 521                                 ev->sched_type, ws->tx_base, txq_data, flags);
 522                 }
 523                 rte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);
 524                 return (meta & 0xFFFF);
 525         }
 526
 527         m = ev->mbuf;
 528         ref_cnt = m->refcnt;
 529         txq = cn10k_sso_hws_xtract_meta(m, txq_data);
 530         cn10k_nix_tx_skeleton(txq, cmd, flags);
 531         /* Perform header writes before barrier for TSO */
 532         if (flags & NIX_TX_OFFLOAD_TSO_F)
 533                 cn10k_nix_xmit_prepare_tso(m, flags);
 534
 535         cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
 536
 537         /* Prepare CPT instruction and get nixtx addr if
 538          * it is for CPT on same lmtline.
 539          */
 540         if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 541                 cn10k_nix_prep_sec(m, cmd, &lmt_addr, c_laddr, &lnum, &loff,
 542                                    &shft, txq->sa_base, flags);
 543
 544         /* Move NIX desc to LMT/NIXTX area */
 545         cn10k_nix_xmit_mv_lmt_base(lmt_addr, cmd, flags);
 546         if (flags & NIX_TX_MULTI_SEG_F) {
 547                 segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)lmt_addr, flags);
 548         } else {
 549                 segdw = cn10k_nix_tx_ext_subs(flags) + 2;
 550         }
 551
 552         if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 553                 pa = txq->cpt_io_addr | 3 << 4;
 554         else
 555                 pa = txq->io_addr | ((segdw - 1) << 4);
 556
 557         if (!ev->sched_type)
 558                 roc_sso_hws_head_wait(ws->tx_base + SSOW_LF_GWS_TAG);
 559
 560         roc_lmt_submit_steorl(lmt_id, pa);
 561
 562         if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
 563                 if (ref_cnt > 1)
 564                         return 1;
 565         }
 566
 567         cnxk_sso_hws_swtag_flush(ws->tx_base + SSOW_LF_GWS_TAG,
 568                                  ws->tx_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
 569         return 1;
 570 }
 571
 572 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                         \
 573         uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name(                  \
 574                 void *port, struct rte_event ev[], uint16_t nb_events);        \
 575         uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name(              \
 576                 void *port, struct rte_event ev[], uint16_t nb_events);        \
 577         uint16_t __rte_hot cn10k_sso_hws_dual_tx_adptr_enq_##name(             \
 578                 void *port, struct rte_event ev[], uint16_t nb_events);        \
 579         uint16_t __rte_hot cn10k_sso_hws_dual_tx_adptr_enq_seg_##name(         \
 580                 void *port, struct rte_event ev[], uint16_t nb_events);
 581
 582 NIX_TX_FASTPATH_MODES
 583 #undef T
 584
 585 #endif