1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CN10K_WORKER_H__
6 #define __CN10K_WORKER_H__
10 #include "cn10k_cryptodev_ops.h"
11 #include "cnxk_ethdev.h"
12 #include "cnxk_eventdev.h"
13 #include "cnxk_worker.h"
15 #include "cn10k_ethdev.h"
21 static __rte_always_inline uint8_t
22 cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
24 const uint32_t tag = (uint32_t)ev->event;
25 const uint8_t new_tt = ev->sched_type;
26 const uint64_t event_ptr = ev->u64;
27 const uint16_t grp = ev->queue_id;
29 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
30 if (ws->xaq_lmt <= *ws->fc_mem)
33 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
34 ws->grp_base + (grp << 12));
38 static __rte_always_inline void
39 cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)
41 const uint32_t tag = (uint32_t)ev->event;
42 const uint8_t new_tt = ev->sched_type;
43 const uint8_t cur_tt =
44 CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0));
47 * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
49 * SSO_TT_ORDERED norm norm untag
50 * SSO_TT_ATOMIC norm norm untag
51 * SSO_TT_UNTAGGED norm norm NOOP
54 if (new_tt == SSO_TT_UNTAGGED) {
55 if (cur_tt != SSO_TT_UNTAGGED)
56 cnxk_sso_hws_swtag_untag(ws->base +
57 SSOW_LF_GWS_OP_SWTAG_UNTAG);
59 cnxk_sso_hws_swtag_norm(tag, new_tt,
60 ws->base + SSOW_LF_GWS_OP_SWTAG_NORM);
65 static __rte_always_inline void
66 cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,
69 const uint32_t tag = (uint32_t)ev->event;
70 const uint8_t new_tt = ev->sched_type;
72 plt_write64(ev->u64, ws->base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
73 cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
74 ws->base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
77 static __rte_always_inline void
78 cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
79 const struct rte_event *ev)
81 const uint8_t grp = ev->queue_id;
83 /* Group hasn't changed, Use SWTAG to forward the event */
84 if (CNXK_GRP_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0)) == grp)
85 cn10k_sso_hws_fwd_swtag(ws, ev);
88 * Group has been changed for group based work pipelining,
89 * Use deschedule/add_work operation to transfer the event to
92 cn10k_sso_hws_fwd_group(ws, ev, grp);
95 static __rte_always_inline void
96 cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
97 const uint32_t tag, const uint32_t flags,
98 const void *const lookup_mem)
100 const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
101 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
103 cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
104 (struct rte_mbuf *)mbuf, lookup_mem,
105 mbuf_init | ((uint64_t)port_id) << 48, flags);
108 static __rte_always_inline void
109 cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
110 void *lookup_mem, void *tstamp, uintptr_t lbase)
112 uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
113 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
114 struct rte_event_vector *vec;
115 uint64_t aura_handle, laddr;
116 uint16_t nb_mbufs, non_vec;
117 uint16_t lmt_id, d_off;
118 struct rte_mbuf *mbuf;
123 mbuf_init |= ((uint64_t)port_id) << 48;
124 vec = (struct rte_event_vector *)vwqe;
127 nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
128 nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,
129 flags | NIX_RX_VWQE_F, lookup_mem,
132 non_vec = vec->nb_elem - nb_mbufs;
134 if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
135 mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -
136 sizeof(struct rte_mbuf));
137 /* Pick first mbuf's aura handle assuming all
138 * mbufs are from a vec and are from same RQ.
140 aura_handle = mbuf->pool->pool_id;
141 ROC_LMT_BASE_ID_GET(lbase, lmt_id);
144 d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);
145 d_off += (mbuf_init & 0xFFFF);
146 sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
147 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
151 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
154 mbuf = (struct rte_mbuf *)((char *)cqe -
155 sizeof(struct rte_mbuf));
157 /* Translate meta to mbuf */
158 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
159 const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
161 mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,
165 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
167 /* Extracting tstamp, if PTP enabled*/
168 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +
169 CNXK_SSO_WQE_SG_PTR);
170 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
171 flags & NIX_RX_OFFLOAD_TSTAMP_F,
172 flags & NIX_RX_MULTI_SEG_F,
173 (uint64_t *)tstamp_ptr);
174 wqe[0] = (uint64_t *)mbuf;
179 /* Free remaining meta buffers if any */
180 if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
181 nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);
186 static __rte_always_inline uint16_t
187 cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
188 const uint32_t flags, void *lookup_mem)
191 __uint128_t get_work;
197 gw.get_work = ws->gw_wdata;
198 #if defined(RTE_ARCH_ARM64) && !defined(__clang__)
200 PLT_CPU_FEATURE_PREAMBLE
201 "caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
202 "sub %[mbuf], %H[wdata], #0x80 \n"
203 : [wdata] "+r"(gw.get_work), [mbuf] "=&r"(mbuf)
204 : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
207 plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
209 roc_load_pair(gw.u64[0], gw.u64[1],
210 ws->base + SSOW_LF_GWS_WQE0);
211 } while (gw.u64[0] & BIT_ULL(63));
212 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
214 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
215 (gw.u64[0] & (0x3FFull << 36)) << 4 |
216 (gw.u64[0] & 0xffffffff);
218 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
219 if ((flags & CPT_RX_WQE_F) &&
220 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
221 RTE_EVENT_TYPE_CRYPTODEV)) {
222 gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
223 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
224 RTE_EVENT_TYPE_ETHDEV) {
225 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
227 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
235 m = (struct rte_mbuf *)mbuf;
236 d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;
237 d_off += RTE_PKTMBUF_HEADROOM;
239 cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
242 cnxk_nix_sa_base_get(port, lookup_mem);
243 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
245 mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(
246 cq_w1, sa_base, (uintptr_t)&iova, &loff,
247 (struct rte_mbuf *)mbuf, d_off);
249 roc_npa_aura_op_free(m->pool->pool_id,
253 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
254 cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
255 gw.u64[0] & 0xFFFFF, flags,
257 /* Extracting tstamp, if PTP enabled*/
258 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
260 CNXK_SSO_WQE_SG_PTR);
261 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
263 flags & NIX_RX_OFFLOAD_TSTAMP_F,
264 flags & NIX_RX_MULTI_SEG_F,
265 (uint64_t *)tstamp_ptr);
267 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
268 RTE_EVENT_TYPE_ETHDEV_VECTOR) {
269 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
270 __uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];
272 vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |
273 ((vwqe_hdr & 0xFFFF) << 48) |
274 ((uint64_t)port << 32);
275 *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
276 cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
277 ws->tstamp, ws->lmt_base);
281 ev->event = gw.u64[0];
287 /* Used in cleaning up workslot. */
288 static __rte_always_inline uint16_t
289 cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)
292 __uint128_t get_work;
297 #ifdef RTE_ARCH_ARM64
298 asm volatile(PLT_CPU_FEATURE_PREAMBLE
299 " ldp %[tag], %[wqp], [%[tag_loc]] \n"
300 " tbz %[tag], 63, done%= \n"
303 " ldp %[tag], %[wqp], [%[tag_loc]] \n"
304 " tbnz %[tag], 63, rty%= \n"
306 " sub %[mbuf], %[wqp], #0x80 \n"
307 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
309 : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0)
313 roc_load_pair(gw.u64[0], gw.u64[1],
314 ws->base + SSOW_LF_GWS_WQE0);
315 } while (gw.u64[0] & BIT_ULL(63));
316 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
319 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
320 (gw.u64[0] & (0x3FFull << 36)) << 4 |
321 (gw.u64[0] & 0xffffffff);
323 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
324 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
325 RTE_EVENT_TYPE_ETHDEV) {
326 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
328 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
329 cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
330 gw.u64[0] & 0xFFFFF, 0, NULL);
335 ev->event = gw.u64[0];
341 /* CN10K Fastpath functions. */
342 uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);
343 uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,
344 const struct rte_event ev[],
346 uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
347 const struct rte_event ev[],
349 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
350 const struct rte_event ev[],
352 uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
355 #define R(name, flags) \
356 uint16_t __rte_hot cn10k_sso_hws_deq_##name( \
357 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
358 uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \
359 void *port, struct rte_event ev[], uint16_t nb_events, \
360 uint64_t timeout_ticks); \
361 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \
362 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
363 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name( \
364 void *port, struct rte_event ev[], uint16_t nb_events, \
365 uint64_t timeout_ticks); \
366 uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name( \
367 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
368 uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name( \
369 void *port, struct rte_event ev[], uint16_t nb_events, \
370 uint64_t timeout_ticks); \
371 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_##name( \
372 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
373 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_burst_##name( \
374 void *port, struct rte_event ev[], uint16_t nb_events, \
375 uint64_t timeout_ticks); \
376 uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \
377 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
378 uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \
379 void *port, struct rte_event ev[], uint16_t nb_events, \
380 uint64_t timeout_ticks); \
381 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name( \
382 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
383 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name( \
384 void *port, struct rte_event ev[], uint16_t nb_events, \
385 uint64_t timeout_ticks); \
386 uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name( \
387 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
388 uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name( \
389 void *port, struct rte_event ev[], uint16_t nb_events, \
390 uint64_t timeout_ticks); \
391 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_##name( \
392 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
393 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_burst_##name( \
394 void *port, struct rte_event ev[], uint16_t nb_events, \
395 uint64_t timeout_ticks);
397 NIX_RX_FASTPATH_MODES
400 #define SSO_DEQ(fn, flags) \
401 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
402 uint64_t timeout_ticks) \
404 struct cn10k_sso_hws *ws = port; \
405 RTE_SET_USED(timeout_ticks); \
406 if (ws->swtag_req) { \
408 cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \
411 return cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
414 #define SSO_DEQ_SEG(fn, flags) SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
415 #define SSO_DEQ_CA(fn, flags) SSO_DEQ(fn, flags | CPT_RX_WQE_F)
416 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
418 #define SSO_DEQ_TMO(fn, flags) \
419 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
420 uint64_t timeout_ticks) \
422 struct cn10k_sso_hws *ws = port; \
425 if (ws->swtag_req) { \
427 cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \
430 ret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
431 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \
432 ret = cn10k_sso_hws_get_work(ws, ev, flags, \
437 #define SSO_DEQ_TMO_SEG(fn, flags) SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
438 #define SSO_DEQ_TMO_CA(fn, flags) SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
439 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
441 #define SSO_CMN_DEQ_BURST(fnb, fn, flags) \
442 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
443 uint16_t nb_events, uint64_t timeout_ticks) \
445 RTE_SET_USED(nb_events); \
446 return fn(port, ev, timeout_ticks); \
449 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags) \
450 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
451 uint16_t nb_events, uint64_t timeout_ticks) \
453 RTE_SET_USED(nb_events); \
454 return fn(port, ev, timeout_ticks); \
457 static __rte_always_inline struct cn10k_eth_txq *
458 cn10k_sso_hws_xtract_meta(struct rte_mbuf *m,
459 const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])
461 return (struct cn10k_eth_txq *)
462 txq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];
465 static __rte_always_inline void
466 cn10k_sso_tx_one(struct rte_mbuf *m, uint64_t *cmd, uint16_t lmt_id,
467 uintptr_t lmt_addr, uint8_t sched_type, uintptr_t base,
468 const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
469 const uint32_t flags)
471 uint8_t lnum = 0, loff = 0, shft = 0;
472 struct cn10k_eth_txq *txq;
478 txq = cn10k_sso_hws_xtract_meta(m, txq_data);
479 cn10k_nix_tx_skeleton(txq, cmd, flags);
480 /* Perform header writes before barrier
483 if (flags & NIX_TX_OFFLOAD_TSO_F)
484 cn10k_nix_xmit_prepare_tso(m, flags);
486 cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
489 /* Prepare CPT instruction and get nixtx addr if
490 * it is for CPT on same lmtline.
492 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
493 cn10k_nix_prep_sec(m, cmd, &laddr, lmt_addr, &lnum, &loff,
494 &shft, txq->sa_base, flags);
496 /* Move NIX desc to LMT/NIXTX area */
497 cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
499 if (flags & NIX_TX_MULTI_SEG_F)
500 segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)laddr, flags);
502 segdw = cn10k_nix_tx_ext_subs(flags) + 2;
504 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
505 pa = txq->cpt_io_addr | 3 << 4;
507 pa = txq->io_addr | ((segdw - 1) << 4);
510 roc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);
512 roc_lmt_submit_steorl(lmt_id, pa);
515 static __rte_always_inline void
516 cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
517 uint64_t *cmd, uint16_t lmt_id, uintptr_t lmt_addr,
518 uint8_t sched_type, uintptr_t base,
519 const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
520 const uint32_t flags)
522 uint16_t port[4], queue[4];
523 uint16_t i, j, pkts, scalar;
524 struct cn10k_eth_txq *txq;
526 scalar = nb_mbufs & (NIX_DESCS_PER_LOOP - 1);
527 pkts = RTE_ALIGN_FLOOR(nb_mbufs, NIX_DESCS_PER_LOOP);
529 for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
530 port[0] = mbufs[i]->port;
531 port[1] = mbufs[i + 1]->port;
532 port[2] = mbufs[i + 2]->port;
533 port[3] = mbufs[i + 3]->port;
535 queue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);
536 queue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);
537 queue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);
538 queue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);
540 if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
541 ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
542 for (j = 0; j < 4; j++)
543 cn10k_sso_tx_one(mbufs[i + j], cmd, lmt_id,
544 lmt_addr, sched_type, base,
547 txq = (struct cn10k_eth_txq *)
548 txq_data[port[0]][queue[0]];
549 cn10k_nix_xmit_pkts_vector(txq, &mbufs[i], 4, cmd,
550 base + SSOW_LF_GWS_TAG,
551 flags | NIX_TX_VWQE_F);
557 for (i = 0; i < scalar; i++) {
558 cn10k_sso_tx_one(mbufs[i], cmd, lmt_id, lmt_addr, sched_type,
559 base, txq_data, flags);
563 static __rte_always_inline uint16_t
564 cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
566 const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
567 const uint32_t flags)
569 struct cn10k_eth_txq *txq;
575 lmt_addr = ws->lmt_base;
576 ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
578 if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
579 struct rte_mbuf **mbufs = ev->vec->mbufs;
580 uint64_t meta = *(uint64_t *)ev->vec;
582 if (meta & BIT(31)) {
583 txq = (struct cn10k_eth_txq *)
584 txq_data[meta >> 32][meta >> 48];
586 cn10k_nix_xmit_pkts_vector(
587 txq, mbufs, meta & 0xFFFF, cmd,
588 ws->tx_base + SSOW_LF_GWS_TAG,
589 flags | NIX_TX_VWQE_F);
591 cn10k_sso_vwqe_split_tx(
592 mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,
593 ev->sched_type, ws->tx_base, txq_data, flags);
595 rte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);
596 return (meta & 0xFFFF);
601 cn10k_sso_tx_one(m, cmd, lmt_id, lmt_addr, ev->sched_type, ws->tx_base,
604 if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
609 cnxk_sso_hws_swtag_flush(ws->tx_base + SSOW_LF_GWS_TAG,
610 ws->tx_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
614 #define T(name, sz, flags) \
615 uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name( \
616 void *port, struct rte_event ev[], uint16_t nb_events); \
617 uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name( \
618 void *port, struct rte_event ev[], uint16_t nb_events);
620 NIX_TX_FASTPATH_MODES
623 #define SSO_TX(fn, sz, flags) \
624 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
625 uint16_t nb_events) \
627 struct cn10k_sso_hws *ws = port; \
629 RTE_SET_USED(nb_events); \
630 return cn10k_sso_hws_event_tx( \
632 (const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) & \
637 #define SSO_TX_SEG(fn, sz, flags) \
638 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
639 uint16_t nb_events) \
641 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
642 struct cn10k_sso_hws *ws = port; \
643 RTE_SET_USED(nb_events); \
644 return cn10k_sso_hws_event_tx( \
646 (const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) & \
648 (flags) | NIX_TX_MULTI_SEG_F); \