1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CN10K_WORKER_H__
6 #define __CN10K_WORKER_H__
10 #include "cn10k_cryptodev_ops.h"
11 #include "cnxk_ethdev.h"
12 #include "cnxk_eventdev.h"
13 #include "cnxk_worker.h"
15 #include "cn10k_ethdev.h"
21 static __rte_always_inline uint8_t
22 cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
24 const uint32_t tag = (uint32_t)ev->event;
25 const uint8_t new_tt = ev->sched_type;
26 const uint64_t event_ptr = ev->u64;
27 const uint16_t grp = ev->queue_id;
29 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
30 if (ws->xaq_lmt <= *ws->fc_mem)
33 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
34 ws->grp_base + (grp << 12));
38 static __rte_always_inline void
39 cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)
41 const uint32_t tag = (uint32_t)ev->event;
42 const uint8_t new_tt = ev->sched_type;
43 const uint8_t cur_tt = CNXK_TT_FROM_TAG(ws->gw_rdata);
46 * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
48 * SSO_TT_ORDERED norm norm untag
49 * SSO_TT_ATOMIC norm norm untag
50 * SSO_TT_UNTAGGED norm norm NOOP
53 if (new_tt == SSO_TT_UNTAGGED) {
54 if (cur_tt != SSO_TT_UNTAGGED)
55 cnxk_sso_hws_swtag_untag(ws->base +
56 SSOW_LF_GWS_OP_SWTAG_UNTAG);
58 cnxk_sso_hws_swtag_norm(tag, new_tt,
59 ws->base + SSOW_LF_GWS_OP_SWTAG_NORM);
64 static __rte_always_inline void
65 cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,
68 const uint32_t tag = (uint32_t)ev->event;
69 const uint8_t new_tt = ev->sched_type;
71 plt_write64(ev->u64, ws->base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
72 cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
73 ws->base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
76 static __rte_always_inline void
77 cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
78 const struct rte_event *ev)
80 const uint8_t grp = ev->queue_id;
82 /* Group hasn't changed, Use SWTAG to forward the event */
83 if (CNXK_GRP_FROM_TAG(ws->gw_rdata) == grp)
84 cn10k_sso_hws_fwd_swtag(ws, ev);
87 * Group has been changed for group based work pipelining,
88 * Use deschedule/add_work operation to transfer the event to
91 cn10k_sso_hws_fwd_group(ws, ev, grp);
94 static __rte_always_inline void
95 cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
96 const uint32_t tag, const uint32_t flags,
97 const void *const lookup_mem)
99 const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
100 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
102 cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
103 (struct rte_mbuf *)mbuf, lookup_mem,
104 mbuf_init | ((uint64_t)port_id) << 48, flags);
107 static __rte_always_inline void
108 cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
109 void *lookup_mem, void *tstamp, uintptr_t lbase)
111 uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
112 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
113 struct rte_event_vector *vec;
114 uint64_t aura_handle, laddr;
115 uint16_t nb_mbufs, non_vec;
116 uint16_t lmt_id, d_off;
117 struct rte_mbuf *mbuf;
123 mbuf_init |= ((uint64_t)port_id) << 48;
124 vec = (struct rte_event_vector *)vwqe;
127 rte_prefetch_non_temporal(&vec->ptrs[0]);
128 #define OBJS_PER_CLINE (RTE_CACHE_LINE_SIZE / sizeof(void *))
129 for (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE)
130 rte_prefetch_non_temporal(&vec->ptrs[i]);
132 nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
133 nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,
134 flags | NIX_RX_VWQE_F, lookup_mem,
137 non_vec = vec->nb_elem - nb_mbufs;
139 if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
140 mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -
141 sizeof(struct rte_mbuf));
142 /* Pick first mbuf's aura handle assuming all
143 * mbufs are from a vec and are from same RQ.
145 aura_handle = mbuf->pool->pool_id;
146 ROC_LMT_BASE_ID_GET(lbase, lmt_id);
149 d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);
150 d_off += (mbuf_init & 0xFFFF);
151 sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
152 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
156 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
159 mbuf = (struct rte_mbuf *)((char *)cqe -
160 sizeof(struct rte_mbuf));
162 /* Translate meta to mbuf */
163 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
164 const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
166 mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,
170 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
172 /* Extracting tstamp, if PTP enabled*/
173 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +
174 CNXK_SSO_WQE_SG_PTR);
175 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
176 flags & NIX_RX_OFFLOAD_TSTAMP_F,
177 (uint64_t *)tstamp_ptr);
178 wqe[0] = (uint64_t *)mbuf;
183 /* Free remaining meta buffers if any */
184 if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
185 nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);
190 static __rte_always_inline uint16_t
191 cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
192 const uint32_t flags, void *lookup_mem)
195 __uint128_t get_work;
200 gw.get_work = ws->gw_wdata;
201 #if defined(RTE_ARCH_ARM64) && !defined(__clang__)
203 PLT_CPU_FEATURE_PREAMBLE
204 "caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
205 : [wdata] "+r"(gw.get_work)
206 : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
209 plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
211 roc_load_pair(gw.u64[0], gw.u64[1],
212 ws->base + SSOW_LF_GWS_WQE0);
213 } while (gw.u64[0] & BIT_ULL(63));
215 ws->gw_rdata = gw.u64[0];
217 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
218 (gw.u64[0] & (0x3FFull << 36)) << 4 |
219 (gw.u64[0] & 0xffffffff);
220 if ((flags & CPT_RX_WQE_F) &&
221 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
222 RTE_EVENT_TYPE_CRYPTODEV)) {
223 gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
224 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
225 RTE_EVENT_TYPE_ETHDEV) {
226 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
229 mbuf = gw.u64[1] - sizeof(struct rte_mbuf);
230 rte_prefetch0((void *)mbuf);
231 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
239 m = (struct rte_mbuf *)mbuf;
240 d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;
241 d_off += RTE_PKTMBUF_HEADROOM;
243 cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
246 cnxk_nix_sa_base_get(port, lookup_mem);
247 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
249 mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(
250 cq_w1, sa_base, (uintptr_t)&iova, &loff,
251 (struct rte_mbuf *)mbuf, d_off);
253 roc_npa_aura_op_free(m->pool->pool_id,
257 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
258 cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
259 gw.u64[0] & 0xFFFFF, flags,
261 /* Extracting tstamp, if PTP enabled*/
262 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
264 CNXK_SSO_WQE_SG_PTR);
265 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
267 flags & NIX_RX_OFFLOAD_TSTAMP_F,
268 (uint64_t *)tstamp_ptr);
270 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
271 RTE_EVENT_TYPE_ETHDEV_VECTOR) {
272 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
273 __uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];
275 vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |
276 ((vwqe_hdr & 0xFFFF) << 48) |
277 ((uint64_t)port << 32);
278 *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
279 cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
280 ws->tstamp, ws->lmt_base);
284 ev->event = gw.u64[0];
290 /* Used in cleaning up workslot. */
291 static __rte_always_inline uint16_t
292 cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)
295 __uint128_t get_work;
300 #ifdef RTE_ARCH_ARM64
301 asm volatile(PLT_CPU_FEATURE_PREAMBLE
302 " ldp %[tag], %[wqp], [%[tag_loc]] \n"
303 " tbz %[tag], 63, done%= \n"
306 " ldp %[tag], %[wqp], [%[tag_loc]] \n"
307 " tbnz %[tag], 63, rty%= \n"
309 " sub %[mbuf], %[wqp], #0x80 \n"
310 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
312 : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0)
316 roc_load_pair(gw.u64[0], gw.u64[1],
317 ws->base + SSOW_LF_GWS_WQE0);
318 } while (gw.u64[0] & BIT_ULL(63));
319 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
322 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
323 (gw.u64[0] & (0x3FFull << 36)) << 4 |
324 (gw.u64[0] & 0xffffffff);
326 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
327 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
328 RTE_EVENT_TYPE_ETHDEV) {
329 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
331 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
332 cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
333 gw.u64[0] & 0xFFFFF, 0, NULL);
338 ev->event = gw.u64[0];
344 /* CN10K Fastpath functions. */
345 uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);
346 uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,
347 const struct rte_event ev[],
349 uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
350 const struct rte_event ev[],
352 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
353 const struct rte_event ev[],
355 uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
358 #define R(name, flags) \
359 uint16_t __rte_hot cn10k_sso_hws_deq_##name( \
360 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
361 uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \
362 void *port, struct rte_event ev[], uint16_t nb_events, \
363 uint64_t timeout_ticks); \
364 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \
365 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
366 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name( \
367 void *port, struct rte_event ev[], uint16_t nb_events, \
368 uint64_t timeout_ticks); \
369 uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name( \
370 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
371 uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name( \
372 void *port, struct rte_event ev[], uint16_t nb_events, \
373 uint64_t timeout_ticks); \
374 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_##name( \
375 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
376 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_burst_##name( \
377 void *port, struct rte_event ev[], uint16_t nb_events, \
378 uint64_t timeout_ticks); \
379 uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \
380 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
381 uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \
382 void *port, struct rte_event ev[], uint16_t nb_events, \
383 uint64_t timeout_ticks); \
384 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name( \
385 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
386 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name( \
387 void *port, struct rte_event ev[], uint16_t nb_events, \
388 uint64_t timeout_ticks); \
389 uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name( \
390 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
391 uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name( \
392 void *port, struct rte_event ev[], uint16_t nb_events, \
393 uint64_t timeout_ticks); \
394 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_##name( \
395 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
396 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_burst_##name( \
397 void *port, struct rte_event ev[], uint16_t nb_events, \
398 uint64_t timeout_ticks);
400 NIX_RX_FASTPATH_MODES
403 #define SSO_DEQ(fn, flags) \
404 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
405 uint64_t timeout_ticks) \
407 struct cn10k_sso_hws *ws = port; \
408 RTE_SET_USED(timeout_ticks); \
409 if (ws->swtag_req) { \
411 ws->gw_rdata = cnxk_sso_hws_swtag_wait( \
412 ws->base + SSOW_LF_GWS_WQE0); \
415 return cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
418 #define SSO_DEQ_SEG(fn, flags) SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
419 #define SSO_DEQ_CA(fn, flags) SSO_DEQ(fn, flags | CPT_RX_WQE_F)
420 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
422 #define SSO_DEQ_TMO(fn, flags) \
423 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
424 uint64_t timeout_ticks) \
426 struct cn10k_sso_hws *ws = port; \
429 if (ws->swtag_req) { \
431 ws->gw_rdata = cnxk_sso_hws_swtag_wait( \
432 ws->base + SSOW_LF_GWS_WQE0); \
435 ret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
436 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \
437 ret = cn10k_sso_hws_get_work(ws, ev, flags, \
442 #define SSO_DEQ_TMO_SEG(fn, flags) SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
443 #define SSO_DEQ_TMO_CA(fn, flags) SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
444 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
446 #define SSO_CMN_DEQ_BURST(fnb, fn, flags) \
447 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
448 uint16_t nb_events, uint64_t timeout_ticks) \
450 RTE_SET_USED(nb_events); \
451 return fn(port, ev, timeout_ticks); \
454 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags) \
455 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
456 uint16_t nb_events, uint64_t timeout_ticks) \
458 RTE_SET_USED(nb_events); \
459 return fn(port, ev, timeout_ticks); \
462 static __rte_always_inline struct cn10k_eth_txq *
463 cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data)
465 return (struct cn10k_eth_txq
466 *)(txq_data[(txq_data[m->port] >> 48) +
467 rte_event_eth_tx_adapter_txq_get(m)] &
471 static __rte_always_inline void
472 cn10k_sso_txq_fc_wait(const struct cn10k_eth_txq *txq)
474 while ((uint64_t)txq->nb_sqb_bufs_adj <=
475 __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
479 static __rte_always_inline void
480 cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,
481 uint16_t lmt_id, uintptr_t lmt_addr, uint8_t sched_type,
482 const uint64_t *txq_data, const uint32_t flags)
484 uint8_t lnum = 0, loff = 0, shft = 0;
485 struct cn10k_eth_txq *txq;
491 txq = cn10k_sso_hws_xtract_meta(m, txq_data);
492 cn10k_nix_tx_skeleton(txq, cmd, flags, 0);
493 /* Perform header writes before barrier
496 if (flags & NIX_TX_OFFLOAD_TSO_F)
497 cn10k_nix_xmit_prepare_tso(m, flags);
499 cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
502 /* Prepare CPT instruction and get nixtx addr if
503 * it is for CPT on same lmtline.
505 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
506 cn10k_nix_prep_sec(m, cmd, &laddr, lmt_addr, &lnum, &loff,
507 &shft, txq->sa_base, flags);
509 /* Move NIX desc to LMT/NIXTX area */
510 cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
512 if (flags & NIX_TX_MULTI_SEG_F)
513 segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)laddr, flags);
515 segdw = cn10k_nix_tx_ext_subs(flags) + 2;
517 cn10k_nix_xmit_prepare_tstamp(txq, laddr, m->ol_flags, segdw, flags);
518 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
519 pa = txq->cpt_io_addr | 3 << 4;
521 pa = txq->io_addr | ((segdw - 1) << 4);
523 if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)
524 ws->gw_rdata = roc_sso_hws_head_wait(ws->base);
526 cn10k_sso_txq_fc_wait(txq);
527 roc_lmt_submit_steorl(lmt_id, pa);
530 static __rte_always_inline void
531 cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,
532 uint16_t nb_mbufs, uint64_t *cmd, uint16_t lmt_id,
533 uintptr_t lmt_addr, uint8_t sched_type,
534 const uint64_t *txq_data, const uint32_t flags)
536 uint16_t port[4], queue[4];
537 uint16_t i, j, pkts, scalar;
538 struct cn10k_eth_txq *txq;
540 scalar = nb_mbufs & (NIX_DESCS_PER_LOOP - 1);
541 pkts = RTE_ALIGN_FLOOR(nb_mbufs, NIX_DESCS_PER_LOOP);
543 for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
544 port[0] = mbufs[i]->port;
545 port[1] = mbufs[i + 1]->port;
546 port[2] = mbufs[i + 2]->port;
547 port[3] = mbufs[i + 3]->port;
549 queue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);
550 queue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);
551 queue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);
552 queue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);
554 if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
555 ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
556 for (j = 0; j < 4; j++)
557 cn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id,
558 lmt_addr, sched_type, txq_data,
561 txq = (struct cn10k_eth_txq
562 *)(txq_data[(txq_data[port[0]] >> 48) +
565 cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws,
567 flags | NIX_TX_VWQE_F);
573 for (i = 0; i < scalar; i++) {
574 cn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr,
575 sched_type, txq_data, flags);
579 static __rte_always_inline uint16_t
580 cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
581 uint64_t *cmd, const uint64_t *txq_data,
582 const uint32_t flags)
584 struct cn10k_eth_txq *txq;
589 lmt_addr = ws->lmt_base;
590 ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
592 if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
593 struct rte_mbuf **mbufs = ev->vec->mbufs;
594 uint64_t meta = *(uint64_t *)ev->vec;
596 if (meta & BIT(31)) {
597 txq = (struct cn10k_eth_txq
598 *)(txq_data[(txq_data[meta >> 32] >>
603 cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws, mbufs,
605 flags | NIX_TX_VWQE_F);
607 cn10k_sso_vwqe_split_tx(
608 ws, mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,
609 ev->sched_type, txq_data, flags);
611 rte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);
612 return (meta & 0xFFFF);
616 cn10k_sso_tx_one(ws, m, cmd, lmt_id, lmt_addr, ev->sched_type, txq_data,
622 #define T(name, sz, flags) \
623 uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name( \
624 void *port, struct rte_event ev[], uint16_t nb_events); \
625 uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name( \
626 void *port, struct rte_event ev[], uint16_t nb_events);
628 NIX_TX_FASTPATH_MODES
631 #define SSO_TX(fn, sz, flags) \
632 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
633 uint16_t nb_events) \
635 struct cn10k_sso_hws *ws = port; \
637 RTE_SET_USED(nb_events); \
638 return cn10k_sso_hws_event_tx( \
639 ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data, \
643 #define SSO_TX_SEG(fn, sz, flags) \
644 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
645 uint16_t nb_events) \
647 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
648 struct cn10k_sso_hws *ws = port; \
649 RTE_SET_USED(nb_events); \
650 return cn10k_sso_hws_event_tx( \
651 ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data, \
652 (flags) | NIX_TX_MULTI_SEG_F); \