drivers/event/cnxk/cn10k_worker.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CN10K_WORKER_H__
   6 #define __CN10K_WORKER_H__
   7
   8 #include <rte_vect.h>
   9
  10 #include "cn10k_cryptodev_ops.h"
  11 #include "cnxk_ethdev.h"
  12 #include "cnxk_eventdev.h"
  13 #include "cnxk_worker.h"
  14
  15 #include "cn10k_ethdev.h"
  16 #include "cn10k_rx.h"
  17 #include "cn10k_tx.h"
  18
  19 /* SSO Operations */
  20
  21 static __rte_always_inline uint8_t
  22 cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
  23 {
  24         const uint32_t tag = (uint32_t)ev->event;
  25         const uint8_t new_tt = ev->sched_type;
  26         const uint64_t event_ptr = ev->u64;
  27         const uint16_t grp = ev->queue_id;
  28
  29         rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
  30         if (ws->xaq_lmt <= *ws->fc_mem)
  31                 return 0;
  32
  33         cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
  34                               ws->grp_base + (grp << 12));
  35         return 1;
  36 }
  37
  38 static __rte_always_inline void
  39 cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)
  40 {
  41         const uint32_t tag = (uint32_t)ev->event;
  42         const uint8_t new_tt = ev->sched_type;
  43         const uint8_t cur_tt = CNXK_TT_FROM_TAG(ws->gw_rdata);
  44
  45         /* CNXK model
  46          * cur_tt/new_tt     SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
  47          *
  48          * SSO_TT_ORDERED        norm           norm             untag
  49          * SSO_TT_ATOMIC         norm           norm               untag
  50          * SSO_TT_UNTAGGED       norm           norm             NOOP
  51          */
  52
  53         if (new_tt == SSO_TT_UNTAGGED) {
  54                 if (cur_tt != SSO_TT_UNTAGGED)
  55                         cnxk_sso_hws_swtag_untag(ws->base +
  56                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
  57         } else {
  58                 cnxk_sso_hws_swtag_norm(tag, new_tt,
  59                                         ws->base + SSOW_LF_GWS_OP_SWTAG_NORM);
  60         }
  61         ws->swtag_req = 1;
  62 }
  63
  64 static __rte_always_inline void
  65 cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,
  66                         const uint16_t grp)
  67 {
  68         const uint32_t tag = (uint32_t)ev->event;
  69         const uint8_t new_tt = ev->sched_type;
  70
  71         plt_write64(ev->u64, ws->base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
  72         cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
  73                                    ws->base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
  74 }
  75
  76 static __rte_always_inline void
  77 cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
  78                             const struct rte_event *ev)
  79 {
  80         const uint8_t grp = ev->queue_id;
  81
  82         /* Group hasn't changed, Use SWTAG to forward the event */
  83         if (CNXK_GRP_FROM_TAG(ws->gw_rdata) == grp)
  84                 cn10k_sso_hws_fwd_swtag(ws, ev);
  85         else
  86                 /*
  87                  * Group has been changed for group based work pipelining,
  88                  * Use deschedule/add_work operation to transfer the event to
  89                  * new group/core
  90                  */
  91                 cn10k_sso_hws_fwd_group(ws, ev, grp);
  92 }
  93
  94 static __rte_always_inline void
  95 cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id,
  96                   const uint32_t tag, const uint32_t flags,
  97                   const void *const lookup_mem)
  98 {
  99         const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 100                                    (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 101         struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
 102
 103         /* Mark mempool obj as "get" as it is alloc'ed by NIX */
 104         RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 105
 106         cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
 107                               (struct rte_mbuf *)mbuf, lookup_mem,
 108                               mbuf_init | ((uint64_t)port_id) << 48, flags);
 109 }
 110
 111 static __rte_always_inline void
 112 cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
 113                    void *lookup_mem, void *tstamp, uintptr_t lbase)
 114 {
 115         uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 116                              (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 117         struct rte_event_vector *vec;
 118         uint64_t aura_handle, laddr;
 119         uint16_t nb_mbufs, non_vec;
 120         uint16_t lmt_id, d_off;
 121         struct rte_mbuf **wqe;
 122         struct rte_mbuf *mbuf;
 123         uint8_t loff = 0;
 124         uint64_t sa_base;
 125         int i;
 126
 127         mbuf_init |= ((uint64_t)port_id) << 48;
 128         vec = (struct rte_event_vector *)vwqe;
 129         wqe = vec->mbufs;
 130
 131         rte_prefetch0(&vec->ptrs[0]);
 132 #define OBJS_PER_CLINE (RTE_CACHE_LINE_SIZE / sizeof(void *))
 133         for (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE)
 134                 rte_prefetch0(&vec->ptrs[i]);
 135
 136         nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
 137         nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs,
 138                                               flags | NIX_RX_VWQE_F, lookup_mem,
 139                                               tstamp, lbase);
 140         wqe += nb_mbufs;
 141         non_vec = vec->nb_elem - nb_mbufs;
 142
 143         if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
 144                 mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -
 145                                            sizeof(struct rte_mbuf));
 146                 /* Pick first mbuf's aura handle assuming all
 147                  * mbufs are from a vec and are from same RQ.
 148                  */
 149                 aura_handle = mbuf->pool->pool_id;
 150                 ROC_LMT_BASE_ID_GET(lbase, lmt_id);
 151                 laddr = lbase;
 152                 laddr += 8;
 153                 d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);
 154                 d_off += (mbuf_init & 0xFFFF);
 155                 sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
 156                 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
 157         }
 158
 159         while (non_vec) {
 160                 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
 161                 uint64_t tstamp_ptr;
 162
 163                 mbuf = (struct rte_mbuf *)((char *)cqe -
 164                                            sizeof(struct rte_mbuf));
 165
 166                 /* Mark mempool obj as "get" as it is alloc'ed by NIX */
 167                 RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 168
 169                 /* Translate meta to mbuf */
 170                 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 171                         const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
 172                         const uint64_t cq_w5 = *((const uint64_t *)cqe + 5);
 173
 174                         mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, cq_w5, sa_base, laddr,
 175                                                        &loff, mbuf, d_off,
 176                                                        flags, mbuf_init);
 177                 }
 178
 179                 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
 180                                       mbuf_init, flags);
 181                 /* Extracting tstamp, if PTP enabled*/
 182                 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +
 183                                            CNXK_SSO_WQE_SG_PTR);
 184                 cn10k_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
 185                                         flags & NIX_RX_OFFLOAD_TSTAMP_F,
 186                                         (uint64_t *)tstamp_ptr);
 187                 wqe[0] = (struct rte_mbuf *)mbuf;
 188                 non_vec--;
 189                 wqe++;
 190         }
 191
 192         /* Free remaining meta buffers if any */
 193         if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
 194                 nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);
 195                 plt_io_wmb();
 196         }
 197 }
 198
 199 static __rte_always_inline uint16_t
 200 cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
 201                        const uint32_t flags, void *lookup_mem)
 202 {
 203         union {
 204                 __uint128_t get_work;
 205                 uint64_t u64[2];
 206         } gw;
 207         uint64_t tstamp_ptr;
 208
 209         gw.get_work = ws->gw_wdata;
 210 #if defined(RTE_ARCH_ARM64) && !defined(__clang__)
 211         asm volatile(
 212                 PLT_CPU_FEATURE_PREAMBLE
 213                 "caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
 214                 : [wdata] "+r"(gw.get_work)
 215                 : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
 216                 : "memory");
 217 #else
 218         plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 219         do {
 220                 roc_load_pair(gw.u64[0], gw.u64[1],
 221                               ws->base + SSOW_LF_GWS_WQE0);
 222         } while (gw.u64[0] & BIT_ULL(63));
 223 #endif
 224         ws->gw_rdata = gw.u64[0];
 225         if (gw.u64[1]) {
 226                 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
 227                             (gw.u64[0] & (0x3FFull << 36)) << 4 |
 228                             (gw.u64[0] & 0xffffffff);
 229                 if ((flags & CPT_RX_WQE_F) &&
 230                     (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 231                      RTE_EVENT_TYPE_CRYPTODEV)) {
 232                         gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
 233                 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 234                            RTE_EVENT_TYPE_ETHDEV) {
 235                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 236                         uint64_t mbuf;
 237
 238                         mbuf = gw.u64[1] - sizeof(struct rte_mbuf);
 239                         rte_prefetch0((void *)mbuf);
 240                         if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 241                                 const uint64_t mbuf_init = 0x100010000ULL |
 242                                         RTE_PKTMBUF_HEADROOM |
 243                                         (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 244                                 struct rte_mbuf *m;
 245                                 uintptr_t sa_base;
 246                                 uint64_t iova = 0;
 247                                 uint8_t loff = 0;
 248                                 uint16_t d_off;
 249                                 uint64_t cq_w1;
 250                                 uint64_t cq_w5;
 251
 252                                 m = (struct rte_mbuf *)mbuf;
 253                                 d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;
 254                                 d_off += RTE_PKTMBUF_HEADROOM;
 255
 256                                 cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
 257                                 cq_w5 = *(uint64_t *)(gw.u64[1] + 40);
 258
 259                                 sa_base =
 260                                         cnxk_nix_sa_base_get(port, lookup_mem);
 261                                 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
 262
 263                                 mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(
 264                                         cq_w1, cq_w5, sa_base, (uintptr_t)&iova, &loff,
 265                                         (struct rte_mbuf *)mbuf, d_off, flags,
 266                                         mbuf_init | ((uint64_t)port) << 48);
 267                                 if (loff)
 268                                         roc_npa_aura_op_free(m->pool->pool_id,
 269                                                              0, iova);
 270                         }
 271
 272                         gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 273                         cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 274                                           gw.u64[0] & 0xFFFFF, flags,
 275                                           lookup_mem);
 276                         /* Extracting tstamp, if PTP enabled*/
 277                         tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
 278                                                             gw.u64[1]) +
 279                                                    CNXK_SSO_WQE_SG_PTR);
 280                         cn10k_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
 281                                                 ws->tstamp,
 282                                                 flags & NIX_RX_OFFLOAD_TSTAMP_F,
 283                                                 (uint64_t *)tstamp_ptr);
 284                         gw.u64[1] = mbuf;
 285                 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 286                            RTE_EVENT_TYPE_ETHDEV_VECTOR) {
 287                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 288                         __uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];
 289
 290                         vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |
 291                                    ((vwqe_hdr & 0xFFFF) << 48) |
 292                                    ((uint64_t)port << 32);
 293                         *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
 294                         cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
 295                                            ws->tstamp, ws->lmt_base);
 296                         /* Mark vector mempool object as get */
 297                         RTE_MEMPOOL_CHECK_COOKIES(
 298                                 rte_mempool_from_obj((void *)gw.u64[1]),
 299                                 (void **)&gw.u64[1], 1, 1);
 300                 }
 301         }
 302
 303         ev->event = gw.u64[0];
 304         ev->u64 = gw.u64[1];
 305
 306         return !!gw.u64[1];
 307 }
 308
 309 /* Used in cleaning up workslot. */
 310 static __rte_always_inline uint16_t
 311 cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)
 312 {
 313         union {
 314                 __uint128_t get_work;
 315                 uint64_t u64[2];
 316         } gw;
 317         uint64_t mbuf;
 318
 319 #ifdef RTE_ARCH_ARM64
 320         asm volatile(PLT_CPU_FEATURE_PREAMBLE
 321                      "          ldp %[tag], %[wqp], [%[tag_loc]]        \n"
 322                      "          tbz %[tag], 63, done%=                  \n"
 323                      "          sevl                                    \n"
 324                      "rty%=:    wfe                                     \n"
 325                      "          ldp %[tag], %[wqp], [%[tag_loc]]        \n"
 326                      "          tbnz %[tag], 63, rty%=                  \n"
 327                      "done%=:   dmb ld                                  \n"
 328                      "          sub %[mbuf], %[wqp], #0x80              \n"
 329                      : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
 330                        [mbuf] "=&r"(mbuf)
 331                      : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0)
 332                      : "memory");
 333 #else
 334         do {
 335                 roc_load_pair(gw.u64[0], gw.u64[1],
 336                               ws->base + SSOW_LF_GWS_WQE0);
 337         } while (gw.u64[0] & BIT_ULL(63));
 338         mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
 339 #endif
 340
 341         gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
 342                     (gw.u64[0] & (0x3FFull << 36)) << 4 |
 343                     (gw.u64[0] & 0xffffffff);
 344
 345         if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
 346                 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 347                     RTE_EVENT_TYPE_ETHDEV) {
 348                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 349
 350                         gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 351                         cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 352                                           gw.u64[0] & 0xFFFFF, 0, NULL);
 353                         gw.u64[1] = mbuf;
 354                 }
 355         }
 356
 357         ev->event = gw.u64[0];
 358         ev->u64 = gw.u64[1];
 359
 360         return !!gw.u64[1];
 361 }
 362
 363 /* CN10K Fastpath functions. */
 364 uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);
 365 uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,
 366                                            const struct rte_event ev[],
 367                                            uint16_t nb_events);
 368 uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
 369                                                const struct rte_event ev[],
 370                                                uint16_t nb_events);
 371 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
 372                                                const struct rte_event ev[],
 373                                                uint16_t nb_events);
 374 uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
 375                                         uint16_t nb_events);
 376
 377 #define R(name, flags)                                                         \
 378         uint16_t __rte_hot cn10k_sso_hws_deq_##name(                           \
 379                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 380         uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name(                     \
 381                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 382                 uint64_t timeout_ticks);                                       \
 383         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name(                       \
 384                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 385         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name(                 \
 386                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 387                 uint64_t timeout_ticks);                                       \
 388         uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name(                        \
 389                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 390         uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name(                  \
 391                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 392                 uint64_t timeout_ticks);                                       \
 393         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_##name(                    \
 394                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 395         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_burst_##name(              \
 396                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 397                 uint64_t timeout_ticks);                                       \
 398         uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name(                       \
 399                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 400         uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name(                 \
 401                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 402                 uint64_t timeout_ticks);                                       \
 403         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name(                   \
 404                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 405         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name(             \
 406                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 407                 uint64_t timeout_ticks);                                       \
 408         uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name(                    \
 409                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 410         uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name(              \
 411                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 412                 uint64_t timeout_ticks);                                       \
 413         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_##name(                \
 414                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 415         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_burst_##name(          \
 416                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 417                 uint64_t timeout_ticks);                                       \
 418         uint16_t __rte_hot cn10k_sso_hws_reas_deq_##name(                      \
 419                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 420         uint16_t __rte_hot cn10k_sso_hws_reas_deq_burst_##name(                \
 421                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 422                 uint64_t timeout_ticks);                                       \
 423         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_##name(                  \
 424                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 425         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_burst_##name(            \
 426                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 427                 uint64_t timeout_ticks);                                       \
 428         uint16_t __rte_hot cn10k_sso_hws_reas_deq_ca_##name(                   \
 429                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 430         uint16_t __rte_hot cn10k_sso_hws_reas_deq_ca_burst_##name(             \
 431                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 432                 uint64_t timeout_ticks);                                       \
 433         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_ca_##name(               \
 434                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 435         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_ca_burst_##name(         \
 436                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 437                 uint64_t timeout_ticks);                                       \
 438         uint16_t __rte_hot cn10k_sso_hws_reas_deq_seg_##name(                  \
 439                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 440         uint16_t __rte_hot cn10k_sso_hws_reas_deq_seg_burst_##name(            \
 441                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 442                 uint64_t timeout_ticks);                                       \
 443         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_seg_##name(              \
 444                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 445         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_seg_burst_##name(        \
 446                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 447                 uint64_t timeout_ticks);                                       \
 448         uint16_t __rte_hot cn10k_sso_hws_reas_deq_ca_seg_##name(               \
 449                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 450         uint16_t __rte_hot cn10k_sso_hws_reas_deq_ca_seg_burst_##name(         \
 451                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 452                 uint64_t timeout_ticks);                                       \
 453         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_ca_seg_##name(           \
 454                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 455         uint16_t __rte_hot cn10k_sso_hws_reas_deq_tmo_ca_seg_burst_##name(     \
 456                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 457                 uint64_t timeout_ticks);
 458
 459 NIX_RX_FASTPATH_MODES
 460 #undef R
 461
 462 #define SSO_DEQ(fn, flags)                                                     \
 463         uint16_t __rte_hot fn(void *port, struct rte_event *ev,                \
 464                               uint64_t timeout_ticks)                          \
 465         {                                                                      \
 466                 struct cn10k_sso_hws *ws = port;                               \
 467                 RTE_SET_USED(timeout_ticks);                                   \
 468                 if (ws->swtag_req) {                                           \
 469                         ws->swtag_req = 0;                                     \
 470                         ws->gw_rdata = cnxk_sso_hws_swtag_wait(                \
 471                                 ws->base + SSOW_LF_GWS_WQE0);                  \
 472                         return 1;                                              \
 473                 }                                                              \
 474                 return cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem);  \
 475         }
 476
 477 #define SSO_DEQ_SEG(fn, flags)    SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
 478 #define SSO_DEQ_CA(fn, flags)     SSO_DEQ(fn, flags | CPT_RX_WQE_F)
 479 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
 480
 481 #define SSO_DEQ_TMO(fn, flags)                                                 \
 482         uint16_t __rte_hot fn(void *port, struct rte_event *ev,                \
 483                               uint64_t timeout_ticks)                          \
 484         {                                                                      \
 485                 struct cn10k_sso_hws *ws = port;                               \
 486                 uint16_t ret = 1;                                              \
 487                 uint64_t iter;                                                 \
 488                 if (ws->swtag_req) {                                           \
 489                         ws->swtag_req = 0;                                     \
 490                         ws->gw_rdata = cnxk_sso_hws_swtag_wait(                \
 491                                 ws->base + SSOW_LF_GWS_WQE0);                  \
 492                         return ret;                                            \
 493                 }                                                              \
 494                 ret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem);   \
 495                 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++)     \
 496                         ret = cn10k_sso_hws_get_work(ws, ev, flags,            \
 497                                                      ws->lookup_mem);          \
 498                 return ret;                                                    \
 499         }
 500
 501 #define SSO_DEQ_TMO_SEG(fn, flags)    SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
 502 #define SSO_DEQ_TMO_CA(fn, flags)     SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
 503 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
 504
 505 #define SSO_CMN_DEQ_BURST(fnb, fn, flags)                                      \
 506         uint16_t __rte_hot fnb(void *port, struct rte_event ev[],              \
 507                                uint16_t nb_events, uint64_t timeout_ticks)     \
 508         {                                                                      \
 509                 RTE_SET_USED(nb_events);                                       \
 510                 return fn(port, ev, timeout_ticks);                            \
 511         }
 512
 513 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags)                                  \
 514         uint16_t __rte_hot fnb(void *port, struct rte_event ev[],              \
 515                                uint16_t nb_events, uint64_t timeout_ticks)     \
 516         {                                                                      \
 517                 RTE_SET_USED(nb_events);                                       \
 518                 return fn(port, ev, timeout_ticks);                            \
 519         }
 520
 521 static __rte_always_inline struct cn10k_eth_txq *
 522 cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data)
 523 {
 524         return (struct cn10k_eth_txq
 525                         *)(txq_data[(txq_data[m->port] >> 48) +
 526                                     rte_event_eth_tx_adapter_txq_get(m)] &
 527                            (BIT_ULL(48) - 1));
 528 }
 529
 530 static __rte_always_inline void
 531 cn10k_sso_txq_fc_wait(const struct cn10k_eth_txq *txq)
 532 {
 533         while ((uint64_t)txq->nb_sqb_bufs_adj <=
 534                __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
 535                 ;
 536 }
 537
 538 static __rte_always_inline void
 539 cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,
 540                  uint16_t lmt_id, uintptr_t lmt_addr, uint8_t sched_type,
 541                  const uint64_t *txq_data, const uint32_t flags)
 542 {
 543         uint8_t lnum = 0, loff = 0, shft = 0;
 544         struct cn10k_eth_txq *txq;
 545         uintptr_t laddr;
 546         uint16_t segdw;
 547         uintptr_t pa;
 548         bool sec;
 549
 550         txq = cn10k_sso_hws_xtract_meta(m, txq_data);
 551         cn10k_nix_tx_skeleton(txq, cmd, flags, 0);
 552         /* Perform header writes before barrier
 553          * for TSO
 554          */
 555         if (flags & NIX_TX_OFFLOAD_TSO_F)
 556                 cn10k_nix_xmit_prepare_tso(m, flags);
 557
 558         cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec,
 559                                txq->mark_flag, txq->mark_fmt);
 560
 561         laddr = lmt_addr;
 562         /* Prepare CPT instruction and get nixtx addr if
 563          * it is for CPT on same lmtline.
 564          */
 565         if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 566                 cn10k_nix_prep_sec(m, cmd, &laddr, lmt_addr, &lnum, &loff,
 567                                    &shft, txq->sa_base, flags);
 568
 569         /* Move NIX desc to LMT/NIXTX area */
 570         cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
 571
 572         if (flags & NIX_TX_MULTI_SEG_F)
 573                 segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)laddr, flags);
 574         else
 575                 segdw = cn10k_nix_tx_ext_subs(flags) + 2;
 576
 577         cn10k_nix_xmit_prepare_tstamp(txq, laddr, m->ol_flags, segdw, flags);
 578         if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 579                 pa = txq->cpt_io_addr | 3 << 4;
 580         else
 581                 pa = txq->io_addr | ((segdw - 1) << 4);
 582
 583         if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)
 584                 ws->gw_rdata = roc_sso_hws_head_wait(ws->base);
 585
 586         cn10k_sso_txq_fc_wait(txq);
 587         roc_lmt_submit_steorl(lmt_id, pa);
 588 }
 589
 590 static __rte_always_inline void
 591 cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,
 592                         uint16_t nb_mbufs, uint64_t *cmd, uint16_t lmt_id,
 593                         uintptr_t lmt_addr, uint8_t sched_type,
 594                         const uint64_t *txq_data, const uint32_t flags)
 595 {
 596         uint16_t port[4], queue[4];
 597         uint16_t i, j, pkts, scalar;
 598         struct cn10k_eth_txq *txq;
 599
 600         scalar = nb_mbufs & (NIX_DESCS_PER_LOOP - 1);
 601         pkts = RTE_ALIGN_FLOOR(nb_mbufs, NIX_DESCS_PER_LOOP);
 602
 603         for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
 604                 port[0] = mbufs[i]->port;
 605                 port[1] = mbufs[i + 1]->port;
 606                 port[2] = mbufs[i + 2]->port;
 607                 port[3] = mbufs[i + 3]->port;
 608
 609                 queue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);
 610                 queue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);
 611                 queue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);
 612                 queue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);
 613
 614                 if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
 615                     ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
 616                         for (j = 0; j < 4; j++)
 617                                 cn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id,
 618                                                  lmt_addr, sched_type, txq_data,
 619                                                  flags);
 620                 } else {
 621                         txq = (struct cn10k_eth_txq
 622                                        *)(txq_data[(txq_data[port[0]] >> 48) +
 623                                                    queue[0]] &
 624                                           (BIT_ULL(48) - 1));
 625                         cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws,
 626                                                    &mbufs[i], 4, cmd,
 627                                                    flags | NIX_TX_VWQE_F);
 628                 }
 629         }
 630
 631         mbufs += i;
 632
 633         for (i = 0; i < scalar; i++) {
 634                 cn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr,
 635                                  sched_type, txq_data, flags);
 636         }
 637 }
 638
 639 static __rte_always_inline uint16_t
 640 cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
 641                        uint64_t *cmd, const uint64_t *txq_data,
 642                        const uint32_t flags)
 643 {
 644         struct cn10k_eth_txq *txq;
 645         struct rte_mbuf *m;
 646         uintptr_t lmt_addr;
 647         uint16_t lmt_id;
 648
 649         lmt_addr = ws->lmt_base;
 650         ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
 651
 652         if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
 653                 struct rte_mbuf **mbufs = ev->vec->mbufs;
 654                 uint64_t meta = *(uint64_t *)ev->vec;
 655
 656                 if (meta & BIT(31)) {
 657                         txq = (struct cn10k_eth_txq
 658                                        *)(txq_data[(txq_data[meta >> 32] >>
 659                                                     48) +
 660                                                    (meta >> 48)] &
 661                                           (BIT_ULL(48) - 1));
 662
 663                         cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws, mbufs,
 664                                                    meta & 0xFFFF, cmd,
 665                                                    flags | NIX_TX_VWQE_F);
 666                 } else {
 667                         cn10k_sso_vwqe_split_tx(
 668                                 ws, mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,
 669                                 ev->sched_type, txq_data, flags);
 670                 }
 671                 rte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);
 672                 rte_prefetch0(ws);
 673                 return (meta & 0xFFFF);
 674         }
 675
 676         m = ev->mbuf;
 677         cn10k_sso_tx_one(ws, m, cmd, lmt_id, lmt_addr, ev->sched_type, txq_data,
 678                          flags);
 679
 680         return 1;
 681 }
 682
 683 #define T(name, sz, flags)                                                     \
 684         uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name(                  \
 685                 void *port, struct rte_event ev[], uint16_t nb_events);        \
 686         uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name(              \
 687                 void *port, struct rte_event ev[], uint16_t nb_events);
 688
 689 NIX_TX_FASTPATH_MODES
 690 #undef T
 691
 692 #define SSO_TX(fn, sz, flags)                                                  \
 693         uint16_t __rte_hot fn(void *port, struct rte_event ev[],               \
 694                               uint16_t nb_events)                              \
 695         {                                                                      \
 696                 struct cn10k_sso_hws *ws = port;                               \
 697                 uint64_t cmd[sz];                                              \
 698                 RTE_SET_USED(nb_events);                                       \
 699                 return cn10k_sso_hws_event_tx(                                 \
 700                         ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data,  \
 701                         flags);                                                \
 702         }
 703
 704 #define SSO_TX_SEG(fn, sz, flags)                                              \
 705         uint16_t __rte_hot fn(void *port, struct rte_event ev[],               \
 706                               uint16_t nb_events)                              \
 707         {                                                                      \
 708                 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2];           \
 709                 struct cn10k_sso_hws *ws = port;                               \
 710                 RTE_SET_USED(nb_events);                                       \
 711                 return cn10k_sso_hws_event_tx(                                 \
 712                         ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data,  \
 713                         (flags) | NIX_TX_MULTI_SEG_F);                         \
 714         }
 715
 716 #endif