1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CN10K_WORKER_H__
6 #define __CN10K_WORKER_H__
10 #include "cn10k_cryptodev_ops.h"
11 #include "cnxk_ethdev.h"
12 #include "cnxk_eventdev.h"
13 #include "cnxk_worker.h"
15 #include "cn10k_ethdev.h"
21 static __rte_always_inline uint8_t
22 cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
24 const uint32_t tag = (uint32_t)ev->event;
25 const uint8_t new_tt = ev->sched_type;
26 const uint64_t event_ptr = ev->u64;
27 const uint16_t grp = ev->queue_id;
29 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
30 if (ws->xaq_lmt <= *ws->fc_mem)
33 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
34 ws->grp_base + (grp << 12));
38 static __rte_always_inline void
39 cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)
41 const uint32_t tag = (uint32_t)ev->event;
42 const uint8_t new_tt = ev->sched_type;
43 const uint8_t cur_tt = CNXK_TT_FROM_TAG(ws->gw_rdata);
46 * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
48 * SSO_TT_ORDERED norm norm untag
49 * SSO_TT_ATOMIC norm norm untag
50 * SSO_TT_UNTAGGED norm norm NOOP
53 if (new_tt == SSO_TT_UNTAGGED) {
54 if (cur_tt != SSO_TT_UNTAGGED)
55 cnxk_sso_hws_swtag_untag(ws->base +
56 SSOW_LF_GWS_OP_SWTAG_UNTAG);
58 cnxk_sso_hws_swtag_norm(tag, new_tt,
59 ws->base + SSOW_LF_GWS_OP_SWTAG_NORM);
64 static __rte_always_inline void
65 cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,
68 const uint32_t tag = (uint32_t)ev->event;
69 const uint8_t new_tt = ev->sched_type;
71 plt_write64(ev->u64, ws->base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
72 cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
73 ws->base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
76 static __rte_always_inline void
77 cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
78 const struct rte_event *ev)
80 const uint8_t grp = ev->queue_id;
82 /* Group hasn't changed, Use SWTAG to forward the event */
83 if (CNXK_GRP_FROM_TAG(ws->gw_rdata) == grp)
84 cn10k_sso_hws_fwd_swtag(ws, ev);
87 * Group has been changed for group based work pipelining,
88 * Use deschedule/add_work operation to transfer the event to
91 cn10k_sso_hws_fwd_group(ws, ev, grp);
94 static __rte_always_inline void
95 cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
96 const uint32_t tag, const uint32_t flags,
97 const void *const lookup_mem)
99 const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
100 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
102 cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
103 (struct rte_mbuf *)mbuf, lookup_mem,
104 mbuf_init | ((uint64_t)port_id) << 48, flags);
107 static __rte_always_inline void
108 cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
109 void *lookup_mem, void *tstamp, uintptr_t lbase)
111 uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
112 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
113 struct rte_event_vector *vec;
114 uint64_t aura_handle, laddr;
115 uint16_t nb_mbufs, non_vec;
116 uint16_t lmt_id, d_off;
117 struct rte_mbuf *mbuf;
123 mbuf_init |= ((uint64_t)port_id) << 48;
124 vec = (struct rte_event_vector *)vwqe;
127 rte_prefetch_non_temporal(&vec->ptrs[0]);
128 #define OBJS_PER_CLINE (RTE_CACHE_LINE_SIZE / sizeof(void *))
129 for (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE)
130 rte_prefetch_non_temporal(&vec->ptrs[i]);
132 nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
133 nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,
134 flags | NIX_RX_VWQE_F, lookup_mem,
137 non_vec = vec->nb_elem - nb_mbufs;
139 if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
140 mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -
141 sizeof(struct rte_mbuf));
142 /* Pick first mbuf's aura handle assuming all
143 * mbufs are from a vec and are from same RQ.
145 aura_handle = mbuf->pool->pool_id;
146 ROC_LMT_BASE_ID_GET(lbase, lmt_id);
149 d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);
150 d_off += (mbuf_init & 0xFFFF);
151 sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
152 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
156 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
159 mbuf = (struct rte_mbuf *)((char *)cqe -
160 sizeof(struct rte_mbuf));
162 /* Translate meta to mbuf */
163 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
164 const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
166 mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,
170 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
172 /* Extracting tstamp, if PTP enabled*/
173 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +
174 CNXK_SSO_WQE_SG_PTR);
175 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
176 flags & NIX_RX_OFFLOAD_TSTAMP_F,
177 flags & NIX_RX_MULTI_SEG_F,
178 (uint64_t *)tstamp_ptr);
179 wqe[0] = (uint64_t *)mbuf;
184 /* Free remaining meta buffers if any */
185 if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
186 nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);
191 static __rte_always_inline uint16_t
192 cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
193 const uint32_t flags, void *lookup_mem)
196 __uint128_t get_work;
201 gw.get_work = ws->gw_wdata;
202 #if defined(RTE_ARCH_ARM64) && !defined(__clang__)
204 PLT_CPU_FEATURE_PREAMBLE
205 "caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
206 : [wdata] "+r"(gw.get_work)
207 : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
210 plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
212 roc_load_pair(gw.u64[0], gw.u64[1],
213 ws->base + SSOW_LF_GWS_WQE0);
214 } while (gw.u64[0] & BIT_ULL(63));
216 ws->gw_rdata = gw.u64[0];
218 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
219 (gw.u64[0] & (0x3FFull << 36)) << 4 |
220 (gw.u64[0] & 0xffffffff);
221 if ((flags & CPT_RX_WQE_F) &&
222 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
223 RTE_EVENT_TYPE_CRYPTODEV)) {
224 gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
225 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
226 RTE_EVENT_TYPE_ETHDEV) {
227 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
230 mbuf = gw.u64[1] - sizeof(struct rte_mbuf);
231 rte_prefetch0((void *)mbuf);
232 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
240 m = (struct rte_mbuf *)mbuf;
241 d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;
242 d_off += RTE_PKTMBUF_HEADROOM;
244 cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
247 cnxk_nix_sa_base_get(port, lookup_mem);
248 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
250 mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(
251 cq_w1, sa_base, (uintptr_t)&iova, &loff,
252 (struct rte_mbuf *)mbuf, d_off);
254 roc_npa_aura_op_free(m->pool->pool_id,
258 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
259 cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
260 gw.u64[0] & 0xFFFFF, flags,
262 /* Extracting tstamp, if PTP enabled*/
263 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
265 CNXK_SSO_WQE_SG_PTR);
266 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
268 flags & NIX_RX_OFFLOAD_TSTAMP_F,
269 flags & NIX_RX_MULTI_SEG_F,
270 (uint64_t *)tstamp_ptr);
272 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
273 RTE_EVENT_TYPE_ETHDEV_VECTOR) {
274 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
275 __uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];
277 vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |
278 ((vwqe_hdr & 0xFFFF) << 48) |
279 ((uint64_t)port << 32);
280 *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
281 cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
282 ws->tstamp, ws->lmt_base);
286 ev->event = gw.u64[0];
292 /* Used in cleaning up workslot. */
293 static __rte_always_inline uint16_t
294 cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)
297 __uint128_t get_work;
302 #ifdef RTE_ARCH_ARM64
303 asm volatile(PLT_CPU_FEATURE_PREAMBLE
304 " ldp %[tag], %[wqp], [%[tag_loc]] \n"
305 " tbz %[tag], 63, done%= \n"
308 " ldp %[tag], %[wqp], [%[tag_loc]] \n"
309 " tbnz %[tag], 63, rty%= \n"
311 " sub %[mbuf], %[wqp], #0x80 \n"
312 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
314 : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0)
318 roc_load_pair(gw.u64[0], gw.u64[1],
319 ws->base + SSOW_LF_GWS_WQE0);
320 } while (gw.u64[0] & BIT_ULL(63));
321 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
324 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
325 (gw.u64[0] & (0x3FFull << 36)) << 4 |
326 (gw.u64[0] & 0xffffffff);
328 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
329 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
330 RTE_EVENT_TYPE_ETHDEV) {
331 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
333 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
334 cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
335 gw.u64[0] & 0xFFFFF, 0, NULL);
340 ev->event = gw.u64[0];
346 /* CN10K Fastpath functions. */
347 uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);
348 uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,
349 const struct rte_event ev[],
351 uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
352 const struct rte_event ev[],
354 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
355 const struct rte_event ev[],
357 uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
360 #define R(name, flags) \
361 uint16_t __rte_hot cn10k_sso_hws_deq_##name( \
362 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
363 uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \
364 void *port, struct rte_event ev[], uint16_t nb_events, \
365 uint64_t timeout_ticks); \
366 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \
367 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
368 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name( \
369 void *port, struct rte_event ev[], uint16_t nb_events, \
370 uint64_t timeout_ticks); \
371 uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name( \
372 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
373 uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name( \
374 void *port, struct rte_event ev[], uint16_t nb_events, \
375 uint64_t timeout_ticks); \
376 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_##name( \
377 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
378 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_burst_##name( \
379 void *port, struct rte_event ev[], uint16_t nb_events, \
380 uint64_t timeout_ticks); \
381 uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \
382 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
383 uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \
384 void *port, struct rte_event ev[], uint16_t nb_events, \
385 uint64_t timeout_ticks); \
386 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name( \
387 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
388 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name( \
389 void *port, struct rte_event ev[], uint16_t nb_events, \
390 uint64_t timeout_ticks); \
391 uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name( \
392 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
393 uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name( \
394 void *port, struct rte_event ev[], uint16_t nb_events, \
395 uint64_t timeout_ticks); \
396 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_##name( \
397 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
398 uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_burst_##name( \
399 void *port, struct rte_event ev[], uint16_t nb_events, \
400 uint64_t timeout_ticks);
402 NIX_RX_FASTPATH_MODES
405 #define SSO_DEQ(fn, flags) \
406 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
407 uint64_t timeout_ticks) \
409 struct cn10k_sso_hws *ws = port; \
410 RTE_SET_USED(timeout_ticks); \
411 if (ws->swtag_req) { \
413 ws->gw_rdata = cnxk_sso_hws_swtag_wait( \
414 ws->base + SSOW_LF_GWS_WQE0); \
417 return cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
420 #define SSO_DEQ_SEG(fn, flags) SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
421 #define SSO_DEQ_CA(fn, flags) SSO_DEQ(fn, flags | CPT_RX_WQE_F)
422 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
424 #define SSO_DEQ_TMO(fn, flags) \
425 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
426 uint64_t timeout_ticks) \
428 struct cn10k_sso_hws *ws = port; \
431 if (ws->swtag_req) { \
433 ws->gw_rdata = cnxk_sso_hws_swtag_wait( \
434 ws->base + SSOW_LF_GWS_WQE0); \
437 ret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
438 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \
439 ret = cn10k_sso_hws_get_work(ws, ev, flags, \
444 #define SSO_DEQ_TMO_SEG(fn, flags) SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
445 #define SSO_DEQ_TMO_CA(fn, flags) SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
446 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
448 #define SSO_CMN_DEQ_BURST(fnb, fn, flags) \
449 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
450 uint16_t nb_events, uint64_t timeout_ticks) \
452 RTE_SET_USED(nb_events); \
453 return fn(port, ev, timeout_ticks); \
456 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags) \
457 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
458 uint16_t nb_events, uint64_t timeout_ticks) \
460 RTE_SET_USED(nb_events); \
461 return fn(port, ev, timeout_ticks); \
464 static __rte_always_inline struct cn10k_eth_txq *
465 cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data)
467 return (struct cn10k_eth_txq
468 *)(txq_data[(txq_data[m->port] >> 48) +
469 rte_event_eth_tx_adapter_txq_get(m)] &
473 static __rte_always_inline void
474 cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,
475 uint16_t lmt_id, uintptr_t lmt_addr, uint8_t sched_type,
476 const uint64_t *txq_data, const uint32_t flags)
478 uint8_t lnum = 0, loff = 0, shft = 0;
479 struct cn10k_eth_txq *txq;
485 txq = cn10k_sso_hws_xtract_meta(m, txq_data);
486 cn10k_nix_tx_skeleton(txq, cmd, flags, 0);
487 /* Perform header writes before barrier
490 if (flags & NIX_TX_OFFLOAD_TSO_F)
491 cn10k_nix_xmit_prepare_tso(m, flags);
493 cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
496 /* Prepare CPT instruction and get nixtx addr if
497 * it is for CPT on same lmtline.
499 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
500 cn10k_nix_prep_sec(m, cmd, &laddr, lmt_addr, &lnum, &loff,
501 &shft, txq->sa_base, flags);
503 /* Move NIX desc to LMT/NIXTX area */
504 cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
506 if (flags & NIX_TX_MULTI_SEG_F)
507 segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)laddr, flags);
509 segdw = cn10k_nix_tx_ext_subs(flags) + 2;
511 cn10k_nix_xmit_prepare_tstamp(txq, laddr, m->ol_flags, segdw, flags);
512 if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
513 pa = txq->cpt_io_addr | 3 << 4;
515 pa = txq->io_addr | ((segdw - 1) << 4);
517 if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)
518 ws->gw_rdata = roc_sso_hws_head_wait(ws->base);
520 roc_lmt_submit_steorl(lmt_id, pa);
523 static __rte_always_inline void
524 cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,
525 uint16_t nb_mbufs, uint64_t *cmd, uint16_t lmt_id,
526 uintptr_t lmt_addr, uint8_t sched_type,
527 const uint64_t *txq_data, const uint32_t flags)
529 uint16_t port[4], queue[4];
530 uint16_t i, j, pkts, scalar;
531 struct cn10k_eth_txq *txq;
533 scalar = nb_mbufs & (NIX_DESCS_PER_LOOP - 1);
534 pkts = RTE_ALIGN_FLOOR(nb_mbufs, NIX_DESCS_PER_LOOP);
536 for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
537 port[0] = mbufs[i]->port;
538 port[1] = mbufs[i + 1]->port;
539 port[2] = mbufs[i + 2]->port;
540 port[3] = mbufs[i + 3]->port;
542 queue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);
543 queue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);
544 queue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);
545 queue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);
547 if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
548 ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
549 for (j = 0; j < 4; j++)
550 cn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id,
551 lmt_addr, sched_type, txq_data,
554 txq = (struct cn10k_eth_txq
555 *)(txq_data[(txq_data[port[0]] >> 48) +
558 cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws,
560 flags | NIX_TX_VWQE_F);
566 for (i = 0; i < scalar; i++) {
567 cn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr,
568 sched_type, txq_data, flags);
572 static __rte_always_inline uint16_t
573 cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
574 uint64_t *cmd, const uint64_t *txq_data,
575 const uint32_t flags)
577 struct cn10k_eth_txq *txq;
583 lmt_addr = ws->lmt_base;
584 ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
586 if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
587 struct rte_mbuf **mbufs = ev->vec->mbufs;
588 uint64_t meta = *(uint64_t *)ev->vec;
590 if (meta & BIT(31)) {
591 txq = (struct cn10k_eth_txq
592 *)(txq_data[(txq_data[meta >> 32] >>
597 cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws, mbufs,
599 flags | NIX_TX_VWQE_F);
601 cn10k_sso_vwqe_split_tx(
602 ws, mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,
603 ev->sched_type, txq_data, flags);
605 rte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);
606 return (meta & 0xFFFF);
611 cn10k_sso_tx_one(ws, m, cmd, lmt_id, lmt_addr, ev->sched_type, txq_data,
614 if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
619 cnxk_sso_hws_swtag_flush(ws->base + SSOW_LF_GWS_TAG,
620 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
624 #define T(name, sz, flags) \
625 uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name( \
626 void *port, struct rte_event ev[], uint16_t nb_events); \
627 uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name( \
628 void *port, struct rte_event ev[], uint16_t nb_events);
630 NIX_TX_FASTPATH_MODES
633 #define SSO_TX(fn, sz, flags) \
634 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
635 uint16_t nb_events) \
637 struct cn10k_sso_hws *ws = port; \
639 RTE_SET_USED(nb_events); \
640 return cn10k_sso_hws_event_tx( \
641 ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data, \
645 #define SSO_TX_SEG(fn, sz, flags) \
646 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
647 uint16_t nb_events) \
649 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
650 struct cn10k_sso_hws *ws = port; \
651 RTE_SET_USED(nb_events); \
652 return cn10k_sso_hws_event_tx( \
653 ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data, \
654 (flags) | NIX_TX_MULTI_SEG_F); \