drivers/event/cnxk/cn10k_worker.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CN10K_WORKER_H__
   6 #define __CN10K_WORKER_H__
   7
   8 #include <rte_vect.h>
   9
  10 #include "cn10k_cryptodev_ops.h"
  11 #include "cnxk_ethdev.h"
  12 #include "cnxk_eventdev.h"
  13 #include "cnxk_worker.h"
  14
  15 #include "cn10k_ethdev.h"
  16 #include "cn10k_rx.h"
  17 #include "cn10k_tx.h"
  18
  19 /* SSO Operations */
  20
  21 static __rte_always_inline uint8_t
  22 cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
  23 {
  24         const uint32_t tag = (uint32_t)ev->event;
  25         const uint8_t new_tt = ev->sched_type;
  26         const uint64_t event_ptr = ev->u64;
  27         const uint16_t grp = ev->queue_id;
  28
  29         rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
  30         if (ws->xaq_lmt <= *ws->fc_mem)
  31                 return 0;
  32
  33         cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
  34                               ws->grp_base + (grp << 12));
  35         return 1;
  36 }
  37
  38 static __rte_always_inline void
  39 cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)
  40 {
  41         const uint32_t tag = (uint32_t)ev->event;
  42         const uint8_t new_tt = ev->sched_type;
  43         const uint8_t cur_tt = CNXK_TT_FROM_TAG(ws->gw_rdata);
  44
  45         /* CNXK model
  46          * cur_tt/new_tt     SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
  47          *
  48          * SSO_TT_ORDERED        norm           norm             untag
  49          * SSO_TT_ATOMIC         norm           norm               untag
  50          * SSO_TT_UNTAGGED       norm           norm             NOOP
  51          */
  52
  53         if (new_tt == SSO_TT_UNTAGGED) {
  54                 if (cur_tt != SSO_TT_UNTAGGED)
  55                         cnxk_sso_hws_swtag_untag(ws->base +
  56                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
  57         } else {
  58                 cnxk_sso_hws_swtag_norm(tag, new_tt,
  59                                         ws->base + SSOW_LF_GWS_OP_SWTAG_NORM);
  60         }
  61         ws->swtag_req = 1;
  62 }
  63
  64 static __rte_always_inline void
  65 cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,
  66                         const uint16_t grp)
  67 {
  68         const uint32_t tag = (uint32_t)ev->event;
  69         const uint8_t new_tt = ev->sched_type;
  70
  71         plt_write64(ev->u64, ws->base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
  72         cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
  73                                    ws->base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
  74 }
  75
  76 static __rte_always_inline void
  77 cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
  78                             const struct rte_event *ev)
  79 {
  80         const uint8_t grp = ev->queue_id;
  81
  82         /* Group hasn't changed, Use SWTAG to forward the event */
  83         if (CNXK_GRP_FROM_TAG(ws->gw_rdata) == grp)
  84                 cn10k_sso_hws_fwd_swtag(ws, ev);
  85         else
  86                 /*
  87                  * Group has been changed for group based work pipelining,
  88                  * Use deschedule/add_work operation to transfer the event to
  89                  * new group/core
  90                  */
  91                 cn10k_sso_hws_fwd_group(ws, ev, grp);
  92 }
  93
  94 static __rte_always_inline void
  95 cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id,
  96                   const uint32_t tag, const uint32_t flags,
  97                   const void *const lookup_mem)
  98 {
  99         const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 100                                    (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 101         struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
 102
 103         /* Mark mempool obj as "get" as it is alloc'ed by NIX */
 104         RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 105
 106         cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
 107                               (struct rte_mbuf *)mbuf, lookup_mem,
 108                               mbuf_init | ((uint64_t)port_id) << 48, flags);
 109 }
 110
 111 static __rte_always_inline void
 112 cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
 113                    void *lookup_mem, void *tstamp, uintptr_t lbase)
 114 {
 115         uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 116                              (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 117         struct rte_event_vector *vec;
 118         uint64_t aura_handle, laddr;
 119         uint16_t nb_mbufs, non_vec;
 120         uint16_t lmt_id, d_off;
 121         struct rte_mbuf **wqe;
 122         struct rte_mbuf *mbuf;
 123         uint8_t loff = 0;
 124         uint64_t sa_base;
 125         int i;
 126
 127         mbuf_init |= ((uint64_t)port_id) << 48;
 128         vec = (struct rte_event_vector *)vwqe;
 129         wqe = vec->mbufs;
 130
 131         rte_prefetch0(&vec->ptrs[0]);
 132 #define OBJS_PER_CLINE (RTE_CACHE_LINE_SIZE / sizeof(void *))
 133         for (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE)
 134                 rte_prefetch0(&vec->ptrs[i]);
 135
 136         nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
 137         nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs,
 138                                               flags | NIX_RX_VWQE_F, lookup_mem,
 139                                               tstamp, lbase);
 140         wqe += nb_mbufs;
 141         non_vec = vec->nb_elem - nb_mbufs;
 142
 143         if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
 144                 mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] -
 145                                            sizeof(struct rte_mbuf));
 146                 /* Pick first mbuf's aura handle assuming all
 147                  * mbufs are from a vec and are from same RQ.
 148                  */
 149                 aura_handle = mbuf->pool->pool_id;
 150                 ROC_LMT_BASE_ID_GET(lbase, lmt_id);
 151                 laddr = lbase;
 152                 laddr += 8;
 153                 d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf);
 154                 d_off += (mbuf_init & 0xFFFF);
 155                 sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
 156                 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
 157         }
 158
 159         while (non_vec) {
 160                 struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
 161                 uint64_t tstamp_ptr;
 162
 163                 mbuf = (struct rte_mbuf *)((char *)cqe -
 164                                            sizeof(struct rte_mbuf));
 165
 166                 /* Mark mempool obj as "get" as it is alloc'ed by NIX */
 167                 RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 168
 169                 /* Translate meta to mbuf */
 170                 if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 171                         const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
 172
 173                         mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr,
 174                                                        &loff, mbuf, d_off);
 175                 }
 176
 177                 cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
 178                                       mbuf_init, flags);
 179                 /* Extracting tstamp, if PTP enabled*/
 180                 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +
 181                                            CNXK_SSO_WQE_SG_PTR);
 182                 cn10k_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
 183                                         flags & NIX_RX_OFFLOAD_TSTAMP_F,
 184                                         (uint64_t *)tstamp_ptr);
 185                 wqe[0] = (struct rte_mbuf *)mbuf;
 186                 non_vec--;
 187                 wqe++;
 188         }
 189
 190         /* Free remaining meta buffers if any */
 191         if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
 192                 nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle);
 193                 plt_io_wmb();
 194         }
 195 }
 196
 197 static __rte_always_inline uint16_t
 198 cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
 199                        const uint32_t flags, void *lookup_mem)
 200 {
 201         union {
 202                 __uint128_t get_work;
 203                 uint64_t u64[2];
 204         } gw;
 205         uint64_t tstamp_ptr;
 206
 207         gw.get_work = ws->gw_wdata;
 208 #if defined(RTE_ARCH_ARM64) && !defined(__clang__)
 209         asm volatile(
 210                 PLT_CPU_FEATURE_PREAMBLE
 211                 "caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
 212                 : [wdata] "+r"(gw.get_work)
 213                 : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
 214                 : "memory");
 215 #else
 216         plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 217         do {
 218                 roc_load_pair(gw.u64[0], gw.u64[1],
 219                               ws->base + SSOW_LF_GWS_WQE0);
 220         } while (gw.u64[0] & BIT_ULL(63));
 221 #endif
 222         ws->gw_rdata = gw.u64[0];
 223         if (gw.u64[1]) {
 224                 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
 225                             (gw.u64[0] & (0x3FFull << 36)) << 4 |
 226                             (gw.u64[0] & 0xffffffff);
 227                 if ((flags & CPT_RX_WQE_F) &&
 228                     (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 229                      RTE_EVENT_TYPE_CRYPTODEV)) {
 230                         gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
 231                 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 232                            RTE_EVENT_TYPE_ETHDEV) {
 233                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 234                         uint64_t mbuf;
 235
 236                         mbuf = gw.u64[1] - sizeof(struct rte_mbuf);
 237                         rte_prefetch0((void *)mbuf);
 238                         if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 239                                 struct rte_mbuf *m;
 240                                 uintptr_t sa_base;
 241                                 uint64_t iova = 0;
 242                                 uint8_t loff = 0;
 243                                 uint16_t d_off;
 244                                 uint64_t cq_w1;
 245
 246                                 m = (struct rte_mbuf *)mbuf;
 247                                 d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m;
 248                                 d_off += RTE_PKTMBUF_HEADROOM;
 249
 250                                 cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
 251
 252                                 sa_base =
 253                                         cnxk_nix_sa_base_get(port, lookup_mem);
 254                                 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
 255
 256                                 mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(
 257                                         cq_w1, sa_base, (uintptr_t)&iova, &loff,
 258                                         (struct rte_mbuf *)mbuf, d_off);
 259                                 if (loff)
 260                                         roc_npa_aura_op_free(m->pool->pool_id,
 261                                                              0, iova);
 262                         }
 263
 264                         gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 265                         cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 266                                           gw.u64[0] & 0xFFFFF, flags,
 267                                           lookup_mem);
 268                         /* Extracting tstamp, if PTP enabled*/
 269                         tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
 270                                                             gw.u64[1]) +
 271                                                    CNXK_SSO_WQE_SG_PTR);
 272                         cn10k_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
 273                                                 ws->tstamp,
 274                                                 flags & NIX_RX_OFFLOAD_TSTAMP_F,
 275                                                 (uint64_t *)tstamp_ptr);
 276                         gw.u64[1] = mbuf;
 277                 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 278                            RTE_EVENT_TYPE_ETHDEV_VECTOR) {
 279                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 280                         __uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];
 281
 282                         vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |
 283                                    ((vwqe_hdr & 0xFFFF) << 48) |
 284                                    ((uint64_t)port << 32);
 285                         *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
 286                         cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
 287                                            ws->tstamp, ws->lmt_base);
 288                         /* Mark vector mempool object as get */
 289                         RTE_MEMPOOL_CHECK_COOKIES(
 290                                 rte_mempool_from_obj((void *)gw.u64[1]),
 291                                 (void **)&gw.u64[1], 1, 1);
 292                 }
 293         }
 294
 295         ev->event = gw.u64[0];
 296         ev->u64 = gw.u64[1];
 297
 298         return !!gw.u64[1];
 299 }
 300
 301 /* Used in cleaning up workslot. */
 302 static __rte_always_inline uint16_t
 303 cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)
 304 {
 305         union {
 306                 __uint128_t get_work;
 307                 uint64_t u64[2];
 308         } gw;
 309         uint64_t mbuf;
 310
 311 #ifdef RTE_ARCH_ARM64
 312         asm volatile(PLT_CPU_FEATURE_PREAMBLE
 313                      "          ldp %[tag], %[wqp], [%[tag_loc]]        \n"
 314                      "          tbz %[tag], 63, done%=                  \n"
 315                      "          sevl                                    \n"
 316                      "rty%=:    wfe                                     \n"
 317                      "          ldp %[tag], %[wqp], [%[tag_loc]]        \n"
 318                      "          tbnz %[tag], 63, rty%=                  \n"
 319                      "done%=:   dmb ld                                  \n"
 320                      "          sub %[mbuf], %[wqp], #0x80              \n"
 321                      : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
 322                        [mbuf] "=&r"(mbuf)
 323                      : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0)
 324                      : "memory");
 325 #else
 326         do {
 327                 roc_load_pair(gw.u64[0], gw.u64[1],
 328                               ws->base + SSOW_LF_GWS_WQE0);
 329         } while (gw.u64[0] & BIT_ULL(63));
 330         mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
 331 #endif
 332
 333         gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
 334                     (gw.u64[0] & (0x3FFull << 36)) << 4 |
 335                     (gw.u64[0] & 0xffffffff);
 336
 337         if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
 338                 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
 339                     RTE_EVENT_TYPE_ETHDEV) {
 340                         uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 341
 342                         gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 343                         cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 344                                           gw.u64[0] & 0xFFFFF, 0, NULL);
 345                         gw.u64[1] = mbuf;
 346                 }
 347         }
 348
 349         ev->event = gw.u64[0];
 350         ev->u64 = gw.u64[1];
 351
 352         return !!gw.u64[1];
 353 }
 354
 355 /* CN10K Fastpath functions. */
 356 uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);
 357 uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,
 358                                            const struct rte_event ev[],
 359                                            uint16_t nb_events);
 360 uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
 361                                                const struct rte_event ev[],
 362                                                uint16_t nb_events);
 363 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
 364                                                const struct rte_event ev[],
 365                                                uint16_t nb_events);
 366 uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
 367                                         uint16_t nb_events);
 368
 369 #define R(name, flags)                                                         \
 370         uint16_t __rte_hot cn10k_sso_hws_deq_##name(                           \
 371                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 372         uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name(                     \
 373                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 374                 uint64_t timeout_ticks);                                       \
 375         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name(                       \
 376                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 377         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name(                 \
 378                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 379                 uint64_t timeout_ticks);                                       \
 380         uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name(                        \
 381                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 382         uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name(                  \
 383                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 384                 uint64_t timeout_ticks);                                       \
 385         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_##name(                    \
 386                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 387         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_burst_##name(              \
 388                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 389                 uint64_t timeout_ticks);                                       \
 390         uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name(                       \
 391                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 392         uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name(                 \
 393                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 394                 uint64_t timeout_ticks);                                       \
 395         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name(                   \
 396                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 397         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name(             \
 398                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 399                 uint64_t timeout_ticks);                                       \
 400         uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name(                    \
 401                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 402         uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name(              \
 403                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 404                 uint64_t timeout_ticks);                                       \
 405         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_##name(                \
 406                 void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
 407         uint16_t __rte_hot cn10k_sso_hws_deq_tmo_ca_seg_burst_##name(          \
 408                 void *port, struct rte_event ev[], uint16_t nb_events,         \
 409                 uint64_t timeout_ticks);
 410
 411 NIX_RX_FASTPATH_MODES
 412 #undef R
 413
 414 #define SSO_DEQ(fn, flags)                                                     \
 415         uint16_t __rte_hot fn(void *port, struct rte_event *ev,                \
 416                               uint64_t timeout_ticks)                          \
 417         {                                                                      \
 418                 struct cn10k_sso_hws *ws = port;                               \
 419                 RTE_SET_USED(timeout_ticks);                                   \
 420                 if (ws->swtag_req) {                                           \
 421                         ws->swtag_req = 0;                                     \
 422                         ws->gw_rdata = cnxk_sso_hws_swtag_wait(                \
 423                                 ws->base + SSOW_LF_GWS_WQE0);                  \
 424                         return 1;                                              \
 425                 }                                                              \
 426                 return cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem);  \
 427         }
 428
 429 #define SSO_DEQ_SEG(fn, flags)    SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
 430 #define SSO_DEQ_CA(fn, flags)     SSO_DEQ(fn, flags | CPT_RX_WQE_F)
 431 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
 432
 433 #define SSO_DEQ_TMO(fn, flags)                                                 \
 434         uint16_t __rte_hot fn(void *port, struct rte_event *ev,                \
 435                               uint64_t timeout_ticks)                          \
 436         {                                                                      \
 437                 struct cn10k_sso_hws *ws = port;                               \
 438                 uint16_t ret = 1;                                              \
 439                 uint64_t iter;                                                 \
 440                 if (ws->swtag_req) {                                           \
 441                         ws->swtag_req = 0;                                     \
 442                         ws->gw_rdata = cnxk_sso_hws_swtag_wait(                \
 443                                 ws->base + SSOW_LF_GWS_WQE0);                  \
 444                         return ret;                                            \
 445                 }                                                              \
 446                 ret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem);   \
 447                 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++)     \
 448                         ret = cn10k_sso_hws_get_work(ws, ev, flags,            \
 449                                                      ws->lookup_mem);          \
 450                 return ret;                                                    \
 451         }
 452
 453 #define SSO_DEQ_TMO_SEG(fn, flags)    SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
 454 #define SSO_DEQ_TMO_CA(fn, flags)     SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
 455 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
 456
 457 #define SSO_CMN_DEQ_BURST(fnb, fn, flags)                                      \
 458         uint16_t __rte_hot fnb(void *port, struct rte_event ev[],              \
 459                                uint16_t nb_events, uint64_t timeout_ticks)     \
 460         {                                                                      \
 461                 RTE_SET_USED(nb_events);                                       \
 462                 return fn(port, ev, timeout_ticks);                            \
 463         }
 464
 465 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags)                                  \
 466         uint16_t __rte_hot fnb(void *port, struct rte_event ev[],              \
 467                                uint16_t nb_events, uint64_t timeout_ticks)     \
 468         {                                                                      \
 469                 RTE_SET_USED(nb_events);                                       \
 470                 return fn(port, ev, timeout_ticks);                            \
 471         }
 472
 473 static __rte_always_inline struct cn10k_eth_txq *
 474 cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data)
 475 {
 476         return (struct cn10k_eth_txq
 477                         *)(txq_data[(txq_data[m->port] >> 48) +
 478                                     rte_event_eth_tx_adapter_txq_get(m)] &
 479                            (BIT_ULL(48) - 1));
 480 }
 481
 482 static __rte_always_inline void
 483 cn10k_sso_txq_fc_wait(const struct cn10k_eth_txq *txq)
 484 {
 485         while ((uint64_t)txq->nb_sqb_bufs_adj <=
 486                __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
 487                 ;
 488 }
 489
 490 static __rte_always_inline void
 491 cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,
 492                  uint16_t lmt_id, uintptr_t lmt_addr, uint8_t sched_type,
 493                  const uint64_t *txq_data, const uint32_t flags)
 494 {
 495         uint8_t lnum = 0, loff = 0, shft = 0;
 496         struct cn10k_eth_txq *txq;
 497         uintptr_t laddr;
 498         uint16_t segdw;
 499         uintptr_t pa;
 500         bool sec;
 501
 502         txq = cn10k_sso_hws_xtract_meta(m, txq_data);
 503         cn10k_nix_tx_skeleton(txq, cmd, flags, 0);
 504         /* Perform header writes before barrier
 505          * for TSO
 506          */
 507         if (flags & NIX_TX_OFFLOAD_TSO_F)
 508                 cn10k_nix_xmit_prepare_tso(m, flags);
 509
 510         cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
 511
 512         laddr = lmt_addr;
 513         /* Prepare CPT instruction and get nixtx addr if
 514          * it is for CPT on same lmtline.
 515          */
 516         if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 517                 cn10k_nix_prep_sec(m, cmd, &laddr, lmt_addr, &lnum, &loff,
 518                                    &shft, txq->sa_base, flags);
 519
 520         /* Move NIX desc to LMT/NIXTX area */
 521         cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
 522
 523         if (flags & NIX_TX_MULTI_SEG_F)
 524                 segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)laddr, flags);
 525         else
 526                 segdw = cn10k_nix_tx_ext_subs(flags) + 2;
 527
 528         cn10k_nix_xmit_prepare_tstamp(txq, laddr, m->ol_flags, segdw, flags);
 529         if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
 530                 pa = txq->cpt_io_addr | 3 << 4;
 531         else
 532                 pa = txq->io_addr | ((segdw - 1) << 4);
 533
 534         if (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)
 535                 ws->gw_rdata = roc_sso_hws_head_wait(ws->base);
 536
 537         cn10k_sso_txq_fc_wait(txq);
 538         roc_lmt_submit_steorl(lmt_id, pa);
 539 }
 540
 541 static __rte_always_inline void
 542 cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,
 543                         uint16_t nb_mbufs, uint64_t *cmd, uint16_t lmt_id,
 544                         uintptr_t lmt_addr, uint8_t sched_type,
 545                         const uint64_t *txq_data, const uint32_t flags)
 546 {
 547         uint16_t port[4], queue[4];
 548         uint16_t i, j, pkts, scalar;
 549         struct cn10k_eth_txq *txq;
 550
 551         scalar = nb_mbufs & (NIX_DESCS_PER_LOOP - 1);
 552         pkts = RTE_ALIGN_FLOOR(nb_mbufs, NIX_DESCS_PER_LOOP);
 553
 554         for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
 555                 port[0] = mbufs[i]->port;
 556                 port[1] = mbufs[i + 1]->port;
 557                 port[2] = mbufs[i + 2]->port;
 558                 port[3] = mbufs[i + 3]->port;
 559
 560                 queue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);
 561                 queue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);
 562                 queue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);
 563                 queue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);
 564
 565                 if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
 566                     ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
 567                         for (j = 0; j < 4; j++)
 568                                 cn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id,
 569                                                  lmt_addr, sched_type, txq_data,
 570                                                  flags);
 571                 } else {
 572                         txq = (struct cn10k_eth_txq
 573                                        *)(txq_data[(txq_data[port[0]] >> 48) +
 574                                                    queue[0]] &
 575                                           (BIT_ULL(48) - 1));
 576                         cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws,
 577                                                    &mbufs[i], 4, cmd,
 578                                                    flags | NIX_TX_VWQE_F);
 579                 }
 580         }
 581
 582         mbufs += i;
 583
 584         for (i = 0; i < scalar; i++) {
 585                 cn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr,
 586                                  sched_type, txq_data, flags);
 587         }
 588 }
 589
 590 static __rte_always_inline uint16_t
 591 cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
 592                        uint64_t *cmd, const uint64_t *txq_data,
 593                        const uint32_t flags)
 594 {
 595         struct cn10k_eth_txq *txq;
 596         struct rte_mbuf *m;
 597         uintptr_t lmt_addr;
 598         uint16_t lmt_id;
 599
 600         lmt_addr = ws->lmt_base;
 601         ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
 602
 603         if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
 604                 struct rte_mbuf **mbufs = ev->vec->mbufs;
 605                 uint64_t meta = *(uint64_t *)ev->vec;
 606
 607                 if (meta & BIT(31)) {
 608                         txq = (struct cn10k_eth_txq
 609                                        *)(txq_data[(txq_data[meta >> 32] >>
 610                                                     48) +
 611                                                    (meta >> 48)] &
 612                                           (BIT_ULL(48) - 1));
 613
 614                         cn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws, mbufs,
 615                                                    meta & 0xFFFF, cmd,
 616                                                    flags | NIX_TX_VWQE_F);
 617                 } else {
 618                         cn10k_sso_vwqe_split_tx(
 619                                 ws, mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,
 620                                 ev->sched_type, txq_data, flags);
 621                 }
 622                 rte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);
 623                 rte_prefetch0(ws);
 624                 return (meta & 0xFFFF);
 625         }
 626
 627         m = ev->mbuf;
 628         cn10k_sso_tx_one(ws, m, cmd, lmt_id, lmt_addr, ev->sched_type, txq_data,
 629                          flags);
 630
 631         return 1;
 632 }
 633
 634 #define T(name, sz, flags)                                                     \
 635         uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name(                  \
 636                 void *port, struct rte_event ev[], uint16_t nb_events);        \
 637         uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name(              \
 638                 void *port, struct rte_event ev[], uint16_t nb_events);
 639
 640 NIX_TX_FASTPATH_MODES
 641 #undef T
 642
 643 #define SSO_TX(fn, sz, flags)                                                  \
 644         uint16_t __rte_hot fn(void *port, struct rte_event ev[],               \
 645                               uint16_t nb_events)                              \
 646         {                                                                      \
 647                 struct cn10k_sso_hws *ws = port;                               \
 648                 uint64_t cmd[sz];                                              \
 649                 RTE_SET_USED(nb_events);                                       \
 650                 return cn10k_sso_hws_event_tx(                                 \
 651                         ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data,  \
 652                         flags);                                                \
 653         }
 654
 655 #define SSO_TX_SEG(fn, sz, flags)                                              \
 656         uint16_t __rte_hot fn(void *port, struct rte_event ev[],               \
 657                               uint16_t nb_events)                              \
 658         {                                                                      \
 659                 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2];           \
 660                 struct cn10k_sso_hws *ws = port;                               \
 661                 RTE_SET_USED(nb_events);                                       \
 662                 return cn10k_sso_hws_event_tx(                                 \
 663                         ws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data,  \
 664                         (flags) | NIX_TX_MULTI_SEG_F);                         \
 665         }
 666
 667 #endif