1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn9k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN9K_DUAL_WS_NB_WS 2
10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
12 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
13 (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \
14 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \
15 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
16 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \
17 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)] \
18 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
20 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
22 enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
23 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \
24 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \
25 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \
26 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
27 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
30 cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base)
32 ws->tag_op = base + SSOW_LF_GWS_TAG;
33 ws->wqp_op = base + SSOW_LF_GWS_WQP;
34 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0;
35 ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;
36 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
37 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
41 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
43 struct cnxk_sso_evdev *dev = arg;
44 struct cn9k_sso_hws_dual *dws;
45 struct cn9k_sso_hws *ws;
50 rc = roc_sso_hws_link(&dev->sso,
51 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
53 rc |= roc_sso_hws_link(&dev->sso,
54 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
58 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
65 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
67 struct cnxk_sso_evdev *dev = arg;
68 struct cn9k_sso_hws_dual *dws;
69 struct cn9k_sso_hws *ws;
74 rc = roc_sso_hws_unlink(&dev->sso,
75 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
77 rc |= roc_sso_hws_unlink(&dev->sso,
78 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
82 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
89 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
91 struct cnxk_sso_evdev *dev = arg;
92 struct cn9k_sso_hws_dual *dws;
93 struct cn9k_sso_hws *ws;
96 /* Set get_work tmo for HWS */
97 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
100 rte_memcpy(dws->grps_base, grps_base,
101 sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
102 dws->fc_mem = dev->fc_mem;
103 dws->xaq_lmt = dev->xaq_lmt;
105 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
106 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
109 rte_memcpy(ws->grps_base, grps_base,
110 sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
111 ws->fc_mem = dev->fc_mem;
112 ws->xaq_lmt = dev->xaq_lmt;
114 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
119 cn9k_sso_hws_release(void *arg, void *hws)
121 struct cnxk_sso_evdev *dev = arg;
122 struct cn9k_sso_hws_dual *dws;
123 struct cn9k_sso_hws *ws;
128 for (i = 0; i < dev->nb_event_queues; i++) {
129 roc_sso_hws_unlink(&dev->sso,
130 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
132 roc_sso_hws_unlink(&dev->sso,
133 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
136 memset(dws, 0, sizeof(*dws));
139 for (i = 0; i < dev->nb_event_queues; i++)
140 roc_sso_hws_unlink(&dev->sso, ws->hws_id,
142 memset(ws, 0, sizeof(*ws));
147 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
148 cnxk_handle_event_t fn, void *arg)
150 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
151 struct cn9k_sso_hws_dual *dws;
152 struct cn9k_sso_hws_state *st;
153 struct cn9k_sso_hws *ws;
154 uint64_t cq_ds_cnt = 1;
161 plt_write64(0, base + SSO_LF_GGRP_QCTL);
163 req = queue_id; /* GGRP ID */
164 req |= BIT_ULL(18); /* Grouped */
165 req |= BIT_ULL(16); /* WAIT */
167 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
168 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
169 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
170 cq_ds_cnt &= 0x3FFF3FFF0000;
174 st = &dws->ws_state[0];
175 ws_base = dws->base[0];
178 st = (struct cn9k_sso_hws_state *)ws;
182 while (aq_cnt || cq_ds_cnt || ds_cnt) {
183 plt_write64(req, st->getwrk_op);
184 cn9k_sso_hws_get_work_empty(st, &ev);
185 if (fn != NULL && ev.u64 != 0)
187 if (ev.sched_type != SSO_TT_EMPTY)
188 cnxk_sso_hws_swtag_flush(st->tag_op,
191 val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
192 } while (val & BIT_ULL(56));
193 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
194 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
195 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
196 /* Extract cq and ds count */
197 cq_ds_cnt &= 0x3FFF3FFF0000;
200 plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
204 cn9k_sso_hws_reset(void *arg, void *hws)
206 struct cnxk_sso_evdev *dev = arg;
207 struct cn9k_sso_hws_dual *dws;
208 struct cn9k_sso_hws *ws;
217 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
218 base = dev->dual_ws ? dws->base[i] : ws->base;
219 /* Wait till getwork/swtp/waitw/desched completes. */
221 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
222 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
225 tag = plt_read64(base + SSOW_LF_GWS_TAG);
226 pend_tt = (tag >> 32) & 0x3;
227 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
228 if (pend_tt == SSO_TT_ATOMIC ||
229 pend_tt == SSO_TT_ORDERED)
230 cnxk_sso_hws_swtag_untag(
231 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
232 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
235 /* Wait for desched to complete. */
237 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
238 } while (pend_state & BIT_ULL(58));
243 cn9k_sso_set_rsrc(void *arg)
245 struct cnxk_sso_evdev *dev = arg;
248 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
250 dev->max_event_ports = dev->sso.max_hws;
251 dev->max_event_queues =
252 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
253 RTE_EVENT_MAX_QUEUES_PER_DEV :
258 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
260 struct cnxk_sso_evdev *dev = arg;
263 hws = hws * CN9K_DUAL_WS_NB_WS;
265 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
269 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
271 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
274 if (dev->tx_adptr_data == NULL)
277 for (i = 0; i < dev->nb_event_ports; i++) {
279 struct cn9k_sso_hws_dual *dws =
280 event_dev->data->ports[i];
283 ws_cookie = cnxk_sso_hws_get_cookie(dws);
284 ws_cookie = rte_realloc_socket(
286 sizeof(struct cnxk_sso_hws_cookie) +
287 sizeof(struct cn9k_sso_hws_dual) +
289 (dev->max_port_id + 1) *
290 RTE_MAX_QUEUES_PER_PORT),
291 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
292 if (ws_cookie == NULL)
294 dws = RTE_PTR_ADD(ws_cookie,
295 sizeof(struct cnxk_sso_hws_cookie));
296 memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
297 sizeof(uint64_t) * (dev->max_port_id + 1) *
298 RTE_MAX_QUEUES_PER_PORT);
299 event_dev->data->ports[i] = dws;
301 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
304 ws_cookie = cnxk_sso_hws_get_cookie(ws);
305 ws_cookie = rte_realloc_socket(
307 sizeof(struct cnxk_sso_hws_cookie) +
308 sizeof(struct cn9k_sso_hws_dual) +
310 (dev->max_port_id + 1) *
311 RTE_MAX_QUEUES_PER_PORT),
312 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
313 if (ws_cookie == NULL)
315 ws = RTE_PTR_ADD(ws_cookie,
316 sizeof(struct cnxk_sso_hws_cookie));
317 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
318 sizeof(uint64_t) * (dev->max_port_id + 1) *
319 RTE_MAX_QUEUES_PER_PORT);
320 event_dev->data->ports[i] = ws;
329 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
331 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
332 /* Single WS modes */
333 const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {
334 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
335 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
336 NIX_RX_FASTPATH_MODES
340 const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {
341 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
342 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
343 NIX_RX_FASTPATH_MODES
347 const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {
348 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
349 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
350 NIX_RX_FASTPATH_MODES
354 const event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {
355 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
356 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
357 NIX_RX_FASTPATH_MODES
361 const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = {
362 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
363 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name,
364 NIX_RX_FASTPATH_MODES
368 const event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = {
369 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
370 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name,
371 NIX_RX_FASTPATH_MODES
375 const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
376 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
377 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
378 NIX_RX_FASTPATH_MODES
382 const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {
383 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
384 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
385 NIX_RX_FASTPATH_MODES
389 const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {
390 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
391 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
392 NIX_RX_FASTPATH_MODES
396 const event_dequeue_burst_t
397 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {
398 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
399 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
400 NIX_RX_FASTPATH_MODES
404 const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = {
405 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
406 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name,
407 NIX_RX_FASTPATH_MODES
411 const event_dequeue_burst_t
412 sso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = {
413 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
414 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name,
415 NIX_RX_FASTPATH_MODES
420 const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2] = {
421 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
422 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
423 NIX_RX_FASTPATH_MODES
427 const event_dequeue_burst_t sso_hws_dual_deq_burst[2][2][2][2][2][2] = {
428 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
429 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
430 NIX_RX_FASTPATH_MODES
434 const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2] = {
435 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
436 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
437 NIX_RX_FASTPATH_MODES
441 const event_dequeue_burst_t
442 sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2] = {
443 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
444 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
445 NIX_RX_FASTPATH_MODES
449 const event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2] = {
450 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
451 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name,
452 NIX_RX_FASTPATH_MODES
456 const event_dequeue_burst_t
457 sso_hws_dual_deq_ca_burst[2][2][2][2][2][2] = {
458 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
459 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name,
460 NIX_RX_FASTPATH_MODES
464 const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2] = {
465 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
466 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
467 NIX_RX_FASTPATH_MODES
471 const event_dequeue_burst_t
472 sso_hws_dual_deq_seg_burst[2][2][2][2][2][2] = {
473 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
474 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
475 NIX_RX_FASTPATH_MODES
479 const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2] = {
480 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
481 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
482 NIX_RX_FASTPATH_MODES
486 const event_dequeue_burst_t
487 sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2] = {
488 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
489 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
490 NIX_RX_FASTPATH_MODES
494 const event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2] = {
495 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
496 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name,
497 NIX_RX_FASTPATH_MODES
501 const event_dequeue_burst_t
502 sso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2] = {
503 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
504 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
505 NIX_RX_FASTPATH_MODES
510 const event_tx_adapter_enqueue
511 sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
512 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
513 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_##name,
514 NIX_TX_FASTPATH_MODES
518 const event_tx_adapter_enqueue
519 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
520 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
521 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
522 NIX_TX_FASTPATH_MODES
526 const event_tx_adapter_enqueue
527 sso_hws_dual_tx_adptr_enq[2][2][2][2][2][2] = {
528 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
529 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
530 NIX_TX_FASTPATH_MODES
534 const event_tx_adapter_enqueue
535 sso_hws_dual_tx_adptr_enq_seg[2][2][2][2][2][2] = {
536 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
537 [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
538 NIX_TX_FASTPATH_MODES
542 event_dev->enqueue = cn9k_sso_hws_enq;
543 event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
544 event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
545 event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
546 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
547 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);
548 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
549 sso_hws_deq_seg_burst);
550 if (dev->is_timeout_deq) {
551 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
552 sso_hws_deq_tmo_seg);
553 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
554 sso_hws_deq_tmo_seg_burst);
556 if (dev->is_ca_internal_port) {
557 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
559 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
560 sso_hws_deq_ca_seg_burst);
563 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
564 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
566 if (dev->is_timeout_deq) {
567 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
569 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
570 sso_hws_deq_tmo_burst);
572 if (dev->is_ca_internal_port) {
573 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
575 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
576 sso_hws_deq_ca_burst);
579 event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
581 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
582 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
583 sso_hws_tx_adptr_enq_seg);
585 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
586 sso_hws_tx_adptr_enq);
589 event_dev->enqueue = cn9k_sso_hws_dual_enq;
590 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
591 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
592 event_dev->enqueue_forward_burst =
593 cn9k_sso_hws_dual_enq_fwd_burst;
594 event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
596 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
597 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
598 sso_hws_dual_deq_seg);
599 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
600 sso_hws_dual_deq_seg_burst);
601 if (dev->is_timeout_deq) {
602 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
603 sso_hws_dual_deq_tmo_seg);
604 CN9K_SET_EVDEV_DEQ_OP(
605 dev, event_dev->dequeue_burst,
606 sso_hws_dual_deq_tmo_seg_burst);
608 if (dev->is_ca_internal_port) {
609 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
610 sso_hws_dual_deq_ca_seg);
611 CN9K_SET_EVDEV_DEQ_OP(
612 dev, event_dev->dequeue_burst,
613 sso_hws_dual_deq_ca_seg_burst);
616 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
618 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
619 sso_hws_dual_deq_burst);
620 if (dev->is_timeout_deq) {
621 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
622 sso_hws_dual_deq_tmo);
623 CN9K_SET_EVDEV_DEQ_OP(
624 dev, event_dev->dequeue_burst,
625 sso_hws_dual_deq_tmo_burst);
627 if (dev->is_ca_internal_port) {
628 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
629 sso_hws_dual_deq_ca);
630 CN9K_SET_EVDEV_DEQ_OP(
631 dev, event_dev->dequeue_burst,
632 sso_hws_dual_deq_ca_burst);
636 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
637 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
638 sso_hws_dual_tx_adptr_enq_seg);
640 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
641 sso_hws_dual_tx_adptr_enq);
644 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
649 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
651 struct cnxk_sso_evdev *dev = arg;
652 struct cn9k_sso_hws_dual *dws;
653 struct cn9k_sso_hws *ws;
657 dws = rte_zmalloc("cn9k_dual_ws",
658 sizeof(struct cn9k_sso_hws_dual) +
660 RTE_CACHE_LINE_SIZE);
662 plt_err("Failed to alloc memory for port=%d", port_id);
666 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
667 dws->base[0] = roc_sso_hws_base_get(
668 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
669 dws->base[1] = roc_sso_hws_base_get(
670 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
671 cn9k_init_hws_ops(&dws->ws_state[0], dws->base[0]);
672 cn9k_init_hws_ops(&dws->ws_state[1], dws->base[1]);
673 dws->hws_id = port_id;
679 /* Allocate event port memory */
680 ws = rte_zmalloc("cn9k_ws",
681 sizeof(struct cn9k_sso_hws) +
683 RTE_CACHE_LINE_SIZE);
685 plt_err("Failed to alloc memory for port=%d", port_id);
689 /* First cache line is reserved for cookie */
690 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
691 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
692 cn9k_init_hws_ops((struct cn9k_sso_hws_state *)ws, ws->base);
693 ws->hws_id = port_id;
703 cn9k_sso_info_get(struct rte_eventdev *event_dev,
704 struct rte_event_dev_info *dev_info)
706 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
708 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
709 cnxk_sso_info_get(dev, dev_info);
713 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
715 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
718 rc = cnxk_sso_dev_validate(event_dev);
720 plt_err("Invalid event device configuration");
724 roc_sso_rsrc_fini(&dev->sso);
726 rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
728 plt_err("Failed to initialize SSO resources");
732 rc = cnxk_sso_xaq_allocate(dev);
736 rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
741 /* Restore any prior port-queue mapping. */
742 cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
749 roc_sso_rsrc_fini(&dev->sso);
750 dev->nb_event_ports = 0;
755 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
756 const struct rte_event_port_conf *port_conf)
759 RTE_SET_USED(port_conf);
760 return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
764 cn9k_sso_port_release(void *port)
766 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
767 struct cnxk_sso_evdev *dev;
772 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
773 if (!gws_cookie->configured)
776 cn9k_sso_hws_release(dev, port);
777 memset(gws_cookie, 0, sizeof(*gws_cookie));
779 rte_free(gws_cookie);
783 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
784 const uint8_t queues[], const uint8_t priorities[],
787 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
788 uint16_t hwgrp_ids[nb_links];
791 RTE_SET_USED(priorities);
792 for (link = 0; link < nb_links; link++)
793 hwgrp_ids[link] = queues[link];
794 nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
796 return (int)nb_links;
800 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
801 uint8_t queues[], uint16_t nb_unlinks)
803 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
804 uint16_t hwgrp_ids[nb_unlinks];
807 for (unlink = 0; unlink < nb_unlinks; unlink++)
808 hwgrp_ids[unlink] = queues[unlink];
809 nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
811 return (int)nb_unlinks;
815 cn9k_sso_start(struct rte_eventdev *event_dev)
819 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
823 rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
824 cn9k_sso_hws_flush_events);
828 cn9k_sso_fp_fns_set(event_dev);
834 cn9k_sso_stop(struct rte_eventdev *event_dev)
836 cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
840 cn9k_sso_close(struct rte_eventdev *event_dev)
842 return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
846 cn9k_sso_selftest(void)
848 return cnxk_sso_selftest(RTE_STR(event_cn9k));
852 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
853 const struct rte_eth_dev *eth_dev, uint32_t *caps)
857 RTE_SET_USED(event_dev);
858 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
860 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
862 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
863 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
864 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
870 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
873 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
876 for (i = 0; i < dev->nb_event_ports; i++) {
878 struct cn9k_sso_hws_dual *dws =
879 event_dev->data->ports[i];
880 dws->lookup_mem = lookup_mem;
881 dws->tstamp = tstmp_info;
883 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
884 ws->lookup_mem = lookup_mem;
885 ws->tstamp = tstmp_info;
891 cn9k_sso_rx_adapter_queue_add(
892 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
894 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
896 struct cn9k_eth_rxq *rxq;
901 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
905 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
910 rxq = eth_dev->data->rx_queues[0];
911 lookup_mem = rxq->lookup_mem;
912 tstmp_info = rxq->tstamp;
913 cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
914 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
920 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
921 const struct rte_eth_dev *eth_dev,
926 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
930 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
934 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
935 const struct rte_eth_dev *eth_dev, uint32_t *caps)
940 ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
944 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
950 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id,
953 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
954 struct cn9k_eth_txq *txq;
955 struct roc_nix_sq *sq;
958 if (tx_queue_id < 0) {
959 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
960 cn9k_sso_txq_fc_update(eth_dev, i, ena);
964 sq = &cnxk_eth_dev->sqs[tx_queue_id];
965 txq = eth_dev->data->tx_queues[tx_queue_id];
967 ena ? RTE_MIN(CNXK_SSO_SQB_LIMIT, sq->aura_sqb_bufs) :
969 txq->nb_sqb_bufs_adj =
971 RTE_ALIGN_MUL_CEIL(sq_limit,
972 (1ULL << txq->sqes_per_sqb_log2)) /
973 (1ULL << txq->sqes_per_sqb_log2);
974 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
979 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
980 const struct rte_eth_dev *eth_dev,
986 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
989 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);
990 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
993 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
999 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
1000 const struct rte_eth_dev *eth_dev,
1001 int32_t tx_queue_id)
1006 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
1009 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, false);
1010 return cn9k_sso_updt_tx_adptr_data(event_dev);
1014 cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
1015 const struct rte_cryptodev *cdev, uint32_t *caps)
1017 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1018 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1020 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
1021 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
1027 cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
1028 const struct rte_cryptodev *cdev,
1029 int32_t queue_pair_id, const struct rte_event *event)
1031 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1033 RTE_SET_USED(event);
1035 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1036 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1038 dev->is_ca_internal_port = 1;
1039 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1041 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
1045 cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
1046 const struct rte_cryptodev *cdev,
1047 int32_t queue_pair_id)
1049 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1050 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1052 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
1055 static struct rte_eventdev_ops cn9k_sso_dev_ops = {
1056 .dev_infos_get = cn9k_sso_info_get,
1057 .dev_configure = cn9k_sso_dev_configure,
1058 .queue_def_conf = cnxk_sso_queue_def_conf,
1059 .queue_setup = cnxk_sso_queue_setup,
1060 .queue_release = cnxk_sso_queue_release,
1061 .port_def_conf = cnxk_sso_port_def_conf,
1062 .port_setup = cn9k_sso_port_setup,
1063 .port_release = cn9k_sso_port_release,
1064 .port_link = cn9k_sso_port_link,
1065 .port_unlink = cn9k_sso_port_unlink,
1066 .timeout_ticks = cnxk_sso_timeout_ticks,
1068 .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1069 .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1070 .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1071 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1072 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1074 .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1075 .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1076 .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1078 .timer_adapter_caps_get = cnxk_tim_caps_get,
1080 .crypto_adapter_caps_get = cn9k_crypto_adapter_caps_get,
1081 .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add,
1082 .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del,
1084 .dump = cnxk_sso_dump,
1085 .dev_start = cn9k_sso_start,
1086 .dev_stop = cn9k_sso_stop,
1087 .dev_close = cn9k_sso_close,
1088 .dev_selftest = cn9k_sso_selftest,
1092 cn9k_sso_init(struct rte_eventdev *event_dev)
1094 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1097 if (RTE_CACHE_LINE_SIZE != 128) {
1098 plt_err("Driver not compiled for CN9K");
1102 rc = roc_plt_init();
1104 plt_err("Failed to initialize platform model");
1108 event_dev->dev_ops = &cn9k_sso_dev_ops;
1109 /* For secondary processes, the primary has done all the work */
1110 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1111 cn9k_sso_fp_fns_set(event_dev);
1115 rc = cnxk_sso_init(event_dev);
1119 cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1120 if (!dev->max_event_ports || !dev->max_event_queues) {
1121 plt_err("Not enough eventdev resource queues=%d ports=%d",
1122 dev->max_event_queues, dev->max_event_ports);
1123 cnxk_sso_fini(event_dev);
1127 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1128 event_dev->data->name, dev->max_event_queues,
1129 dev->max_event_ports);
1135 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1137 return rte_event_pmd_pci_probe(
1138 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1141 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1147 static struct rte_pci_driver cn9k_pci_sso = {
1148 .id_table = cn9k_pci_sso_map,
1149 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1150 .probe = cn9k_sso_probe,
1151 .remove = cnxk_sso_remove,
1154 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1155 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1156 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1157 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1158 CNXK_SSO_GGRP_QOS "=<string>"
1159 CNXK_SSO_FORCE_BP "=1"
1160 CN9K_SSO_SINGLE_WS "=1"
1161 CNXK_TIM_DISABLE_NPA "=1"
1162 CNXK_TIM_CHNK_SLOTS "=<int>"
1163 CNXK_TIM_RINGS_LMT "=<int>"
1164 CNXK_TIM_STATS_ENA "=1");