1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn9k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN9K_DUAL_WS_NB_WS 2
10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
12 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
13 (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)] \
14 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \
15 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \
16 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
17 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \
18 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)] \
19 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
21 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
22 (enq_op = enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)] \
23 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
24 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \
25 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \
26 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \
27 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
28 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
31 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
33 struct cnxk_sso_evdev *dev = arg;
34 struct cn9k_sso_hws_dual *dws;
35 struct cn9k_sso_hws *ws;
40 rc = roc_sso_hws_link(&dev->sso,
41 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
43 rc |= roc_sso_hws_link(&dev->sso,
44 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
48 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
55 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
57 struct cnxk_sso_evdev *dev = arg;
58 struct cn9k_sso_hws_dual *dws;
59 struct cn9k_sso_hws *ws;
64 rc = roc_sso_hws_unlink(&dev->sso,
65 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
67 rc |= roc_sso_hws_unlink(&dev->sso,
68 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
72 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
79 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
81 struct cnxk_sso_evdev *dev = arg;
82 struct cn9k_sso_hws_dual *dws;
83 struct cn9k_sso_hws *ws;
86 /* Set get_work tmo for HWS */
87 val = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0;
90 dws->grp_base = grp_base;
91 dws->fc_mem = (uint64_t *)dev->fc_iova;
92 dws->xaq_lmt = dev->xaq_lmt;
94 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
95 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
98 ws->grp_base = grp_base;
99 ws->fc_mem = (uint64_t *)dev->fc_iova;
100 ws->xaq_lmt = dev->xaq_lmt;
102 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
107 cn9k_sso_hws_release(void *arg, void *hws)
109 struct cnxk_sso_evdev *dev = arg;
110 struct cn9k_sso_hws_dual *dws;
111 struct cn9k_sso_hws *ws;
116 for (i = 0; i < dev->nb_event_queues; i++) {
117 roc_sso_hws_unlink(&dev->sso,
118 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
120 roc_sso_hws_unlink(&dev->sso,
121 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
124 memset(dws, 0, sizeof(*dws));
127 for (i = 0; i < dev->nb_event_queues; i++)
128 roc_sso_hws_unlink(&dev->sso, ws->hws_id,
130 memset(ws, 0, sizeof(*ws));
135 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
136 cnxk_handle_event_t fn, void *arg)
138 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
139 struct cn9k_sso_hws_dual *dws;
140 struct cn9k_sso_hws *ws;
141 uint64_t cq_ds_cnt = 1;
148 plt_write64(0, base + SSO_LF_GGRP_QCTL);
150 req = queue_id; /* GGRP ID */
151 req |= BIT_ULL(18); /* Grouped */
152 req |= BIT_ULL(16); /* WAIT */
154 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
155 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
156 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
157 cq_ds_cnt &= 0x3FFF3FFF0000;
161 ws_base = dws->base[0];
167 while (aq_cnt || cq_ds_cnt || ds_cnt) {
168 plt_write64(req, ws_base + SSOW_LF_GWS_OP_GET_WORK0);
169 cn9k_sso_hws_get_work_empty(ws_base, &ev);
170 if (fn != NULL && ev.u64 != 0)
172 if (ev.sched_type != SSO_TT_EMPTY)
173 cnxk_sso_hws_swtag_flush(
174 ws_base + SSOW_LF_GWS_TAG,
175 ws_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
177 val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
178 } while (val & BIT_ULL(56));
179 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
180 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
181 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
182 /* Extract cq and ds count */
183 cq_ds_cnt &= 0x3FFF3FFF0000;
186 plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
190 cn9k_sso_hws_reset(void *arg, void *hws)
192 struct cnxk_sso_evdev *dev = arg;
193 struct cn9k_sso_hws_dual *dws;
194 struct cn9k_sso_hws *ws;
203 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
204 base = dev->dual_ws ? dws->base[i] : ws->base;
205 /* Wait till getwork/swtp/waitw/desched completes. */
207 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
208 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
211 tag = plt_read64(base + SSOW_LF_GWS_TAG);
212 pend_tt = (tag >> 32) & 0x3;
213 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
214 if (pend_tt == SSO_TT_ATOMIC ||
215 pend_tt == SSO_TT_ORDERED)
216 cnxk_sso_hws_swtag_untag(
217 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
218 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
221 /* Wait for desched to complete. */
223 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
224 } while (pend_state & BIT_ULL(58));
229 cn9k_sso_set_rsrc(void *arg)
231 struct cnxk_sso_evdev *dev = arg;
234 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
236 dev->max_event_ports = dev->sso.max_hws;
237 dev->max_event_queues =
238 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
239 RTE_EVENT_MAX_QUEUES_PER_DEV :
244 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
246 struct cnxk_sso_evdev *dev = arg;
249 hws = hws * CN9K_DUAL_WS_NB_WS;
251 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
255 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
257 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
260 if (dev->tx_adptr_data == NULL)
263 for (i = 0; i < dev->nb_event_ports; i++) {
265 struct cn9k_sso_hws_dual *dws =
266 event_dev->data->ports[i];
269 ws_cookie = cnxk_sso_hws_get_cookie(dws);
270 ws_cookie = rte_realloc_socket(
272 sizeof(struct cnxk_sso_hws_cookie) +
273 sizeof(struct cn9k_sso_hws_dual) +
275 (dev->max_port_id + 1) *
276 RTE_MAX_QUEUES_PER_PORT),
277 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
278 if (ws_cookie == NULL)
280 dws = RTE_PTR_ADD(ws_cookie,
281 sizeof(struct cnxk_sso_hws_cookie));
282 memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
283 sizeof(uint64_t) * (dev->max_port_id + 1) *
284 RTE_MAX_QUEUES_PER_PORT);
285 event_dev->data->ports[i] = dws;
287 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
290 ws_cookie = cnxk_sso_hws_get_cookie(ws);
291 ws_cookie = rte_realloc_socket(
293 sizeof(struct cnxk_sso_hws_cookie) +
294 sizeof(struct cn9k_sso_hws_dual) +
296 (dev->max_port_id + 1) *
297 RTE_MAX_QUEUES_PER_PORT),
298 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
299 if (ws_cookie == NULL)
301 ws = RTE_PTR_ADD(ws_cookie,
302 sizeof(struct cnxk_sso_hws_cookie));
303 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
304 sizeof(uint64_t) * (dev->max_port_id + 1) *
305 RTE_MAX_QUEUES_PER_PORT);
306 event_dev->data->ports[i] = ws;
315 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
317 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
318 /* Single WS modes */
319 const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {
320 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
321 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
322 NIX_RX_FASTPATH_MODES
326 const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {
327 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
328 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
329 NIX_RX_FASTPATH_MODES
333 const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {
334 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
335 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
336 NIX_RX_FASTPATH_MODES
340 const event_dequeue_burst_t
341 sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {
342 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
343 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
344 NIX_RX_FASTPATH_MODES
348 const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {
349 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
350 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name,
351 NIX_RX_FASTPATH_MODES
355 const event_dequeue_burst_t
356 sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {
357 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
358 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name,
359 NIX_RX_FASTPATH_MODES
363 const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {
364 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
365 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
366 NIX_RX_FASTPATH_MODES
370 const event_dequeue_burst_t
371 sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {
372 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
373 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
374 NIX_RX_FASTPATH_MODES
378 const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {
379 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
380 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
381 NIX_RX_FASTPATH_MODES
385 const event_dequeue_burst_t
386 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
387 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
388 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
389 NIX_RX_FASTPATH_MODES
393 const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {
394 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
395 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name,
396 NIX_RX_FASTPATH_MODES
400 const event_dequeue_burst_t
401 sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
402 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
403 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name,
404 NIX_RX_FASTPATH_MODES
409 const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2][2] = {
410 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
411 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
412 NIX_RX_FASTPATH_MODES
416 const event_dequeue_burst_t
417 sso_hws_dual_deq_burst[2][2][2][2][2][2][2] = {
418 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
419 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
420 NIX_RX_FASTPATH_MODES
424 const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2][2] = {
425 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
426 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
427 NIX_RX_FASTPATH_MODES
431 const event_dequeue_burst_t
432 sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2][2] = {
433 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
434 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
435 NIX_RX_FASTPATH_MODES
439 const event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2][2] = {
440 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
441 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name,
442 NIX_RX_FASTPATH_MODES
446 const event_dequeue_burst_t
447 sso_hws_dual_deq_ca_burst[2][2][2][2][2][2][2] = {
448 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
449 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name,
450 NIX_RX_FASTPATH_MODES
454 const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2][2] = {
455 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
456 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
457 NIX_RX_FASTPATH_MODES
461 const event_dequeue_burst_t
462 sso_hws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
463 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
464 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
465 NIX_RX_FASTPATH_MODES
469 const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2][2] = {
470 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
471 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
472 NIX_RX_FASTPATH_MODES
476 const event_dequeue_burst_t
477 sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
478 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
479 [f6][f5][f4][f3][f2][f1][f0] = \
480 cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
481 NIX_RX_FASTPATH_MODES
485 const event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2][2] = {
486 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
487 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name,
488 NIX_RX_FASTPATH_MODES
492 const event_dequeue_burst_t
493 sso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
494 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
495 [f6][f5][f4][f3][f2][f1][f0] = \
496 cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
497 NIX_RX_FASTPATH_MODES
502 const event_tx_adapter_enqueue_t
503 sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
504 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
505 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_##name,
506 NIX_TX_FASTPATH_MODES
510 const event_tx_adapter_enqueue_t
511 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
512 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
513 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
514 NIX_TX_FASTPATH_MODES
518 const event_tx_adapter_enqueue_t
519 sso_hws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
520 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
521 [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
522 NIX_TX_FASTPATH_MODES
526 const event_tx_adapter_enqueue_t
527 sso_hws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
528 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
529 [f6][f5][f4][f3][f2][f1][f0] = \
530 cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
531 NIX_TX_FASTPATH_MODES
535 event_dev->enqueue = cn9k_sso_hws_enq;
536 event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
537 event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
538 event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
539 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
540 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);
541 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
542 sso_hws_deq_seg_burst);
543 if (dev->is_timeout_deq) {
544 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
545 sso_hws_deq_tmo_seg);
546 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
547 sso_hws_deq_tmo_seg_burst);
549 if (dev->is_ca_internal_port) {
550 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
552 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
553 sso_hws_deq_ca_seg_burst);
556 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
557 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
559 if (dev->is_timeout_deq) {
560 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
562 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
563 sso_hws_deq_tmo_burst);
565 if (dev->is_ca_internal_port) {
566 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
568 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
569 sso_hws_deq_ca_burst);
572 event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
574 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
575 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
576 sso_hws_tx_adptr_enq_seg);
578 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
579 sso_hws_tx_adptr_enq);
582 event_dev->enqueue = cn9k_sso_hws_dual_enq;
583 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
584 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
585 event_dev->enqueue_forward_burst =
586 cn9k_sso_hws_dual_enq_fwd_burst;
587 event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
589 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
590 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
591 sso_hws_dual_deq_seg);
592 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
593 sso_hws_dual_deq_seg_burst);
594 if (dev->is_timeout_deq) {
595 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
596 sso_hws_dual_deq_tmo_seg);
597 CN9K_SET_EVDEV_DEQ_OP(
598 dev, event_dev->dequeue_burst,
599 sso_hws_dual_deq_tmo_seg_burst);
601 if (dev->is_ca_internal_port) {
602 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
603 sso_hws_dual_deq_ca_seg);
604 CN9K_SET_EVDEV_DEQ_OP(
605 dev, event_dev->dequeue_burst,
606 sso_hws_dual_deq_ca_seg_burst);
609 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
611 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
612 sso_hws_dual_deq_burst);
613 if (dev->is_timeout_deq) {
614 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
615 sso_hws_dual_deq_tmo);
616 CN9K_SET_EVDEV_DEQ_OP(
617 dev, event_dev->dequeue_burst,
618 sso_hws_dual_deq_tmo_burst);
620 if (dev->is_ca_internal_port) {
621 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
622 sso_hws_dual_deq_ca);
623 CN9K_SET_EVDEV_DEQ_OP(
624 dev, event_dev->dequeue_burst,
625 sso_hws_dual_deq_ca_burst);
629 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
630 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
631 sso_hws_dual_tx_adptr_enq_seg);
633 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
634 sso_hws_dual_tx_adptr_enq);
637 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
642 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
644 struct cnxk_sso_evdev *dev = arg;
645 struct cn9k_sso_hws_dual *dws;
646 struct cn9k_sso_hws *ws;
650 dws = rte_zmalloc("cn9k_dual_ws",
651 sizeof(struct cn9k_sso_hws_dual) +
653 RTE_CACHE_LINE_SIZE);
655 plt_err("Failed to alloc memory for port=%d", port_id);
659 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
660 dws->base[0] = roc_sso_hws_base_get(
661 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
662 dws->base[1] = roc_sso_hws_base_get(
663 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
664 dws->hws_id = port_id;
670 /* Allocate event port memory */
671 ws = rte_zmalloc("cn9k_ws",
672 sizeof(struct cn9k_sso_hws) +
674 RTE_CACHE_LINE_SIZE);
676 plt_err("Failed to alloc memory for port=%d", port_id);
680 /* First cache line is reserved for cookie */
681 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
682 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
683 ws->hws_id = port_id;
693 cn9k_sso_info_get(struct rte_eventdev *event_dev,
694 struct rte_event_dev_info *dev_info)
696 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
698 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
699 cnxk_sso_info_get(dev, dev_info);
703 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
705 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
708 rc = cnxk_sso_dev_validate(event_dev);
710 plt_err("Invalid event device configuration");
714 rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
716 plt_err("Failed to initialize SSO resources");
720 rc = cnxk_sso_xaq_allocate(dev);
724 rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
729 /* Restore any prior port-queue mapping. */
730 cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
737 roc_sso_rsrc_fini(&dev->sso);
738 dev->nb_event_ports = 0;
743 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
744 const struct rte_event_port_conf *port_conf)
747 RTE_SET_USED(port_conf);
748 return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
752 cn9k_sso_port_release(void *port)
754 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
755 struct cnxk_sso_evdev *dev;
760 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
761 if (!gws_cookie->configured)
764 cn9k_sso_hws_release(dev, port);
765 memset(gws_cookie, 0, sizeof(*gws_cookie));
767 rte_free(gws_cookie);
771 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
772 const uint8_t queues[], const uint8_t priorities[],
775 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
776 uint16_t hwgrp_ids[nb_links];
779 RTE_SET_USED(priorities);
780 for (link = 0; link < nb_links; link++)
781 hwgrp_ids[link] = queues[link];
782 nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
784 return (int)nb_links;
788 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
789 uint8_t queues[], uint16_t nb_unlinks)
791 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
792 uint16_t hwgrp_ids[nb_unlinks];
795 for (unlink = 0; unlink < nb_unlinks; unlink++)
796 hwgrp_ids[unlink] = queues[unlink];
797 nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
799 return (int)nb_unlinks;
803 cn9k_sso_start(struct rte_eventdev *event_dev)
807 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
811 rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
812 cn9k_sso_hws_flush_events);
816 cn9k_sso_fp_fns_set(event_dev);
822 cn9k_sso_stop(struct rte_eventdev *event_dev)
824 cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
828 cn9k_sso_close(struct rte_eventdev *event_dev)
830 return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
834 cn9k_sso_selftest(void)
836 return cnxk_sso_selftest(RTE_STR(event_cn9k));
840 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
841 const struct rte_eth_dev *eth_dev, uint32_t *caps)
845 RTE_SET_USED(event_dev);
846 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
848 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
850 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
851 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
852 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
858 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
861 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
864 for (i = 0; i < dev->nb_event_ports; i++) {
866 struct cn9k_sso_hws_dual *dws =
867 event_dev->data->ports[i];
868 dws->lookup_mem = lookup_mem;
869 dws->tstamp = tstmp_info;
871 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
872 ws->lookup_mem = lookup_mem;
873 ws->tstamp = tstmp_info;
879 cn9k_sso_rx_adapter_queue_add(
880 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
882 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
884 struct cn9k_eth_rxq *rxq;
889 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
893 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
898 rxq = eth_dev->data->rx_queues[0];
899 lookup_mem = rxq->lookup_mem;
900 tstmp_info = rxq->tstamp;
901 cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
902 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
908 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
909 const struct rte_eth_dev *eth_dev,
914 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
918 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
922 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
923 const struct rte_eth_dev *eth_dev, uint32_t *caps)
928 ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
932 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
938 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id,
941 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
942 struct cn9k_eth_txq *txq;
943 struct roc_nix_sq *sq;
946 if (tx_queue_id < 0) {
947 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
948 cn9k_sso_txq_fc_update(eth_dev, i, ena);
952 sq = &cnxk_eth_dev->sqs[tx_queue_id];
953 txq = eth_dev->data->tx_queues[tx_queue_id];
955 ena ? RTE_MIN(CNXK_SSO_SQB_LIMIT, sq->aura_sqb_bufs) :
957 txq->nb_sqb_bufs_adj =
959 RTE_ALIGN_MUL_CEIL(sq_limit,
960 (1ULL << txq->sqes_per_sqb_log2)) /
961 (1ULL << txq->sqes_per_sqb_log2);
962 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
967 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
968 const struct rte_eth_dev *eth_dev,
974 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
977 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);
978 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
981 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
987 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
988 const struct rte_eth_dev *eth_dev,
994 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
997 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, false);
998 return cn9k_sso_updt_tx_adptr_data(event_dev);
1002 cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
1003 const struct rte_cryptodev *cdev, uint32_t *caps)
1005 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1006 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1008 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
1009 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
1015 cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
1016 const struct rte_cryptodev *cdev,
1017 int32_t queue_pair_id, const struct rte_event *event)
1019 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1021 RTE_SET_USED(event);
1023 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1024 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1026 dev->is_ca_internal_port = 1;
1027 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1029 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
1033 cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
1034 const struct rte_cryptodev *cdev,
1035 int32_t queue_pair_id)
1037 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1038 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1040 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
1043 static struct eventdev_ops cn9k_sso_dev_ops = {
1044 .dev_infos_get = cn9k_sso_info_get,
1045 .dev_configure = cn9k_sso_dev_configure,
1046 .queue_def_conf = cnxk_sso_queue_def_conf,
1047 .queue_setup = cnxk_sso_queue_setup,
1048 .queue_release = cnxk_sso_queue_release,
1049 .port_def_conf = cnxk_sso_port_def_conf,
1050 .port_setup = cn9k_sso_port_setup,
1051 .port_release = cn9k_sso_port_release,
1052 .port_link = cn9k_sso_port_link,
1053 .port_unlink = cn9k_sso_port_unlink,
1054 .timeout_ticks = cnxk_sso_timeout_ticks,
1056 .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1057 .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1058 .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1059 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1060 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1062 .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1063 .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1064 .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1066 .timer_adapter_caps_get = cnxk_tim_caps_get,
1068 .crypto_adapter_caps_get = cn9k_crypto_adapter_caps_get,
1069 .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add,
1070 .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del,
1072 .dump = cnxk_sso_dump,
1073 .dev_start = cn9k_sso_start,
1074 .dev_stop = cn9k_sso_stop,
1075 .dev_close = cn9k_sso_close,
1076 .dev_selftest = cn9k_sso_selftest,
1080 cn9k_sso_init(struct rte_eventdev *event_dev)
1082 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1085 if (RTE_CACHE_LINE_SIZE != 128) {
1086 plt_err("Driver not compiled for CN9K");
1090 rc = roc_plt_init();
1092 plt_err("Failed to initialize platform model");
1096 event_dev->dev_ops = &cn9k_sso_dev_ops;
1097 /* For secondary processes, the primary has done all the work */
1098 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1099 cn9k_sso_fp_fns_set(event_dev);
1103 rc = cnxk_sso_init(event_dev);
1107 cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1108 if (!dev->max_event_ports || !dev->max_event_queues) {
1109 plt_err("Not enough eventdev resource queues=%d ports=%d",
1110 dev->max_event_queues, dev->max_event_ports);
1111 cnxk_sso_fini(event_dev);
1115 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1116 event_dev->data->name, dev->max_event_queues,
1117 dev->max_event_ports);
1123 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1125 return rte_event_pmd_pci_probe(
1126 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1129 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1130 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1131 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1132 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1133 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1134 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1135 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1136 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1137 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1138 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1139 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1145 static struct rte_pci_driver cn9k_pci_sso = {
1146 .id_table = cn9k_pci_sso_map,
1147 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1148 .probe = cn9k_sso_probe,
1149 .remove = cnxk_sso_remove,
1152 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1153 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1154 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1155 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1156 CNXK_SSO_GGRP_QOS "=<string>"
1157 CNXK_SSO_FORCE_BP "=1"
1158 CN9K_SSO_SINGLE_WS "=1"
1159 CNXK_TIM_DISABLE_NPA "=1"
1160 CNXK_TIM_CHNK_SLOTS "=<int>"
1161 CNXK_TIM_RINGS_LMT "=<int>"
1162 CNXK_TIM_STATS_ENA "=1");