1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn9k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN9K_DUAL_WS_NB_WS 2
10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
12 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
13 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
15 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
16 enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
19 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
21 struct cnxk_sso_evdev *dev = arg;
22 struct cn9k_sso_hws_dual *dws;
23 struct cn9k_sso_hws *ws;
28 rc = roc_sso_hws_link(&dev->sso,
29 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
31 rc |= roc_sso_hws_link(&dev->sso,
32 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
36 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
43 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
45 struct cnxk_sso_evdev *dev = arg;
46 struct cn9k_sso_hws_dual *dws;
47 struct cn9k_sso_hws *ws;
52 rc = roc_sso_hws_unlink(&dev->sso,
53 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
55 rc |= roc_sso_hws_unlink(&dev->sso,
56 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
60 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
67 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
69 struct cnxk_sso_evdev *dev = arg;
70 struct cn9k_sso_hws_dual *dws;
71 struct cn9k_sso_hws *ws;
74 /* Set get_work tmo for HWS */
75 val = NSEC2USEC(dev->deq_tmo_ns);
76 val = val ? val - 1 : 0;
79 dws->grp_base = grp_base;
80 dws->fc_mem = (uint64_t *)dev->fc_iova;
81 dws->xaq_lmt = dev->xaq_lmt;
83 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
84 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
87 ws->grp_base = grp_base;
88 ws->fc_mem = (uint64_t *)dev->fc_iova;
89 ws->xaq_lmt = dev->xaq_lmt;
91 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
96 cn9k_sso_hws_release(void *arg, void *hws)
98 struct cnxk_sso_evdev *dev = arg;
99 struct cn9k_sso_hws_dual *dws;
100 struct cn9k_sso_hws *ws;
105 for (i = 0; i < dev->nb_event_queues; i++) {
106 roc_sso_hws_unlink(&dev->sso,
107 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), &i, 1);
108 roc_sso_hws_unlink(&dev->sso,
109 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), &i, 1);
111 memset(dws, 0, sizeof(*dws));
114 for (i = 0; i < dev->nb_event_queues; i++)
115 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
116 memset(ws, 0, sizeof(*ws));
121 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
122 cnxk_handle_event_t fn, void *arg)
124 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
125 struct cn9k_sso_hws_dual *dws;
126 struct cn9k_sso_hws *ws;
127 uint64_t cq_ds_cnt = 1;
134 plt_write64(0, base + SSO_LF_GGRP_QCTL);
136 req = queue_id; /* GGRP ID */
137 req |= BIT_ULL(18); /* Grouped */
138 req |= BIT_ULL(16); /* WAIT */
140 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
141 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
142 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
143 cq_ds_cnt &= 0x3FFF3FFF0000;
147 ws_base = dws->base[0];
153 while (aq_cnt || cq_ds_cnt || ds_cnt) {
154 plt_write64(req, ws_base + SSOW_LF_GWS_OP_GET_WORK0);
155 cn9k_sso_hws_get_work_empty(ws_base, &ev);
156 if (fn != NULL && ev.u64 != 0)
158 if (ev.sched_type != SSO_TT_EMPTY)
159 cnxk_sso_hws_swtag_flush(
160 ws_base + SSOW_LF_GWS_TAG,
161 ws_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
163 val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
164 } while (val & BIT_ULL(56));
165 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
166 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
167 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
168 /* Extract cq and ds count */
169 cq_ds_cnt &= 0x3FFF3FFF0000;
172 plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
176 cn9k_sso_hws_reset(void *arg, void *hws)
178 struct cnxk_sso_evdev *dev = arg;
179 struct cn9k_sso_hws_dual *dws;
180 struct cn9k_sso_hws *ws;
189 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
190 base = dev->dual_ws ? dws->base[i] : ws->base;
191 /* Wait till getwork/swtp/waitw/desched completes. */
193 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
194 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
197 tag = plt_read64(base + SSOW_LF_GWS_TAG);
198 pend_tt = (tag >> 32) & 0x3;
199 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
200 if (pend_tt == SSO_TT_ATOMIC ||
201 pend_tt == SSO_TT_ORDERED)
202 cnxk_sso_hws_swtag_untag(
203 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
204 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
207 /* Wait for desched to complete. */
209 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
210 } while (pend_state & BIT_ULL(58));
215 cn9k_sso_set_rsrc(void *arg)
217 struct cnxk_sso_evdev *dev = arg;
220 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
222 dev->max_event_ports = dev->sso.max_hws;
223 dev->max_event_queues =
224 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
225 RTE_EVENT_MAX_QUEUES_PER_DEV :
230 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
232 struct cnxk_sso_evdev *dev = arg;
235 hws = hws * CN9K_DUAL_WS_NB_WS;
237 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
241 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
243 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
246 if (dev->tx_adptr_data == NULL)
249 for (i = 0; i < dev->nb_event_ports; i++) {
251 struct cn9k_sso_hws_dual *dws =
252 event_dev->data->ports[i];
255 ws_cookie = cnxk_sso_hws_get_cookie(dws);
256 ws_cookie = rte_realloc_socket(
258 sizeof(struct cnxk_sso_hws_cookie) +
259 sizeof(struct cn9k_sso_hws_dual) +
260 dev->tx_adptr_data_sz,
261 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
262 if (ws_cookie == NULL)
264 dws = RTE_PTR_ADD(ws_cookie,
265 sizeof(struct cnxk_sso_hws_cookie));
266 memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
267 dev->tx_adptr_data_sz);
268 event_dev->data->ports[i] = dws;
270 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
273 ws_cookie = cnxk_sso_hws_get_cookie(ws);
274 ws_cookie = rte_realloc_socket(
276 sizeof(struct cnxk_sso_hws_cookie) +
277 sizeof(struct cn9k_sso_hws_dual) +
278 dev->tx_adptr_data_sz,
279 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
280 if (ws_cookie == NULL)
282 ws = RTE_PTR_ADD(ws_cookie,
283 sizeof(struct cnxk_sso_hws_cookie));
284 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
285 dev->tx_adptr_data_sz);
286 event_dev->data->ports[i] = ws;
295 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
297 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
298 /* Single WS modes */
299 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
300 #define R(name, flags)[flags] = cn9k_sso_hws_deq_##name,
301 NIX_RX_FASTPATH_MODES
305 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
306 #define R(name, flags)[flags] = cn9k_sso_hws_deq_burst_##name,
307 NIX_RX_FASTPATH_MODES
311 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
312 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_##name,
313 NIX_RX_FASTPATH_MODES
317 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
318 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_burst_##name,
319 NIX_RX_FASTPATH_MODES
323 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
324 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_##name,
325 NIX_RX_FASTPATH_MODES
329 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
330 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_burst_##name,
331 NIX_RX_FASTPATH_MODES
335 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
336 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_##name,
337 NIX_RX_FASTPATH_MODES
341 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
342 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_burst_##name,
343 NIX_RX_FASTPATH_MODES
347 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
348 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_##name,
349 NIX_RX_FASTPATH_MODES
353 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
354 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_burst_##name,
355 NIX_RX_FASTPATH_MODES
359 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
360 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_##name,
361 NIX_RX_FASTPATH_MODES
365 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
366 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
367 NIX_RX_FASTPATH_MODES
371 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
372 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_##name,
373 NIX_RX_FASTPATH_MODES
377 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
378 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_burst_##name,
379 NIX_RX_FASTPATH_MODES
383 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
384 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_##name,
385 NIX_RX_FASTPATH_MODES
389 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
390 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_burst_##name,
391 NIX_RX_FASTPATH_MODES
396 const event_dequeue_t sso_hws_dual_deq[NIX_RX_OFFLOAD_MAX] = {
397 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_##name,
398 NIX_RX_FASTPATH_MODES
402 const event_dequeue_burst_t sso_hws_dual_deq_burst[NIX_RX_OFFLOAD_MAX] = {
403 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_burst_##name,
404 NIX_RX_FASTPATH_MODES
408 const event_dequeue_t sso_hws_dual_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
409 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_##name,
410 NIX_RX_FASTPATH_MODES
414 const event_dequeue_burst_t sso_hws_dual_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
415 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
416 NIX_RX_FASTPATH_MODES
420 const event_dequeue_t sso_hws_dual_deq_ca[NIX_RX_OFFLOAD_MAX] = {
421 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_##name,
422 NIX_RX_FASTPATH_MODES
426 const event_dequeue_burst_t sso_hws_dual_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
427 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_burst_##name,
428 NIX_RX_FASTPATH_MODES
432 const event_dequeue_t sso_hws_dual_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
433 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_##name,
434 NIX_RX_FASTPATH_MODES
438 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
439 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_burst_##name,
440 NIX_RX_FASTPATH_MODES
444 const event_dequeue_t sso_hws_dual_deq_seg[NIX_RX_OFFLOAD_MAX] = {
445 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_##name,
446 NIX_RX_FASTPATH_MODES
450 const event_dequeue_burst_t sso_hws_dual_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
451 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_burst_##name,
452 NIX_RX_FASTPATH_MODES
456 const event_dequeue_t sso_hws_dual_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
457 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
458 NIX_RX_FASTPATH_MODES
462 const event_dequeue_burst_t sso_hws_dual_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
463 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
464 NIX_RX_FASTPATH_MODES
468 const event_dequeue_t sso_hws_dual_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
469 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_##name,
470 NIX_RX_FASTPATH_MODES
474 const event_dequeue_burst_t sso_hws_dual_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
475 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
476 NIX_RX_FASTPATH_MODES
480 const event_dequeue_t sso_hws_dual_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
481 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_##name,
482 NIX_RX_FASTPATH_MODES
486 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
487 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name,
488 NIX_RX_FASTPATH_MODES
493 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
494 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_##name,
495 NIX_TX_FASTPATH_MODES
499 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
500 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
501 NIX_TX_FASTPATH_MODES
505 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
506 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
507 NIX_TX_FASTPATH_MODES
511 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
512 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
513 NIX_TX_FASTPATH_MODES
517 event_dev->enqueue = cn9k_sso_hws_enq;
518 event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
519 event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
520 event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
521 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
522 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);
523 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
524 sso_hws_deq_seg_burst);
525 if (dev->is_timeout_deq) {
526 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
527 sso_hws_deq_tmo_seg);
528 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
529 sso_hws_deq_tmo_seg_burst);
531 if (dev->is_ca_internal_port) {
532 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
534 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
535 sso_hws_deq_ca_seg_burst);
538 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
539 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
540 sso_hws_deq_tmo_ca_seg);
541 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
542 sso_hws_deq_tmo_ca_seg_burst);
545 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
546 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
548 if (dev->is_timeout_deq) {
549 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
551 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
552 sso_hws_deq_tmo_burst);
554 if (dev->is_ca_internal_port) {
555 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
557 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
558 sso_hws_deq_ca_burst);
561 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
562 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
564 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
565 sso_hws_deq_tmo_ca_burst);
568 event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
570 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
571 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
572 sso_hws_tx_adptr_enq_seg);
574 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
575 sso_hws_tx_adptr_enq);
578 event_dev->enqueue = cn9k_sso_hws_dual_enq;
579 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
580 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
581 event_dev->enqueue_forward_burst =
582 cn9k_sso_hws_dual_enq_fwd_burst;
583 event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
585 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
586 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
587 sso_hws_dual_deq_seg);
588 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
589 sso_hws_dual_deq_seg_burst);
590 if (dev->is_timeout_deq) {
591 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
592 sso_hws_dual_deq_tmo_seg);
593 CN9K_SET_EVDEV_DEQ_OP(
594 dev, event_dev->dequeue_burst,
595 sso_hws_dual_deq_tmo_seg_burst);
597 if (dev->is_ca_internal_port) {
598 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
599 sso_hws_dual_deq_ca_seg);
600 CN9K_SET_EVDEV_DEQ_OP(
601 dev, event_dev->dequeue_burst,
602 sso_hws_dual_deq_ca_seg_burst);
604 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
605 CN9K_SET_EVDEV_DEQ_OP(
606 dev, event_dev->dequeue,
607 sso_hws_dual_deq_tmo_ca_seg);
608 CN9K_SET_EVDEV_DEQ_OP(
609 dev, event_dev->dequeue_burst,
610 sso_hws_dual_deq_tmo_ca_seg_burst);
613 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
615 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
616 sso_hws_dual_deq_burst);
617 if (dev->is_timeout_deq) {
618 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
619 sso_hws_dual_deq_tmo);
620 CN9K_SET_EVDEV_DEQ_OP(
621 dev, event_dev->dequeue_burst,
622 sso_hws_dual_deq_tmo_burst);
624 if (dev->is_ca_internal_port) {
625 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
626 sso_hws_dual_deq_ca);
627 CN9K_SET_EVDEV_DEQ_OP(
628 dev, event_dev->dequeue_burst,
629 sso_hws_dual_deq_ca_burst);
631 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
632 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
633 sso_hws_dual_deq_tmo_ca);
634 CN9K_SET_EVDEV_DEQ_OP(
635 dev, event_dev->dequeue_burst,
636 sso_hws_dual_deq_tmo_ca_burst);
640 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
641 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
642 sso_hws_dual_tx_adptr_enq_seg);
644 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
645 sso_hws_dual_tx_adptr_enq);
648 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
653 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
655 struct cnxk_sso_evdev *dev = arg;
656 struct cn9k_sso_hws_dual *dws;
657 struct cn9k_sso_hws *ws;
661 dws = rte_zmalloc("cn9k_dual_ws",
662 sizeof(struct cn9k_sso_hws_dual) +
664 RTE_CACHE_LINE_SIZE);
666 plt_err("Failed to alloc memory for port=%d", port_id);
670 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
671 dws->base[0] = roc_sso_hws_base_get(
672 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
673 dws->base[1] = roc_sso_hws_base_get(
674 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
675 dws->hws_id = port_id;
679 dws->gw_wdata = BIT_ULL(16);
684 /* Allocate event port memory */
685 ws = rte_zmalloc("cn9k_ws",
686 sizeof(struct cn9k_sso_hws) +
688 RTE_CACHE_LINE_SIZE);
690 plt_err("Failed to alloc memory for port=%d", port_id);
694 /* First cache line is reserved for cookie */
695 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
696 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
697 ws->hws_id = port_id;
700 ws->gw_wdata = BIT_ULL(16);
710 cn9k_sso_info_get(struct rte_eventdev *event_dev,
711 struct rte_event_dev_info *dev_info)
713 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
715 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
716 cnxk_sso_info_get(dev, dev_info);
720 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
722 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
725 rc = cnxk_sso_dev_validate(event_dev);
727 plt_err("Invalid event device configuration");
731 rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
733 plt_err("Failed to initialize SSO resources");
737 rc = cnxk_sso_xaq_allocate(dev);
741 rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
746 /* Restore any prior port-queue mapping. */
747 cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
754 roc_sso_rsrc_fini(&dev->sso);
755 dev->nb_event_ports = 0;
760 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
761 const struct rte_event_port_conf *port_conf)
764 RTE_SET_USED(port_conf);
765 return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
769 cn9k_sso_port_release(void *port)
771 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
772 struct cnxk_sso_evdev *dev;
777 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
778 if (!gws_cookie->configured)
781 cn9k_sso_hws_release(dev, port);
782 memset(gws_cookie, 0, sizeof(*gws_cookie));
784 rte_free(gws_cookie);
788 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
789 const uint8_t queues[], const uint8_t priorities[],
792 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
793 uint16_t hwgrp_ids[nb_links];
796 RTE_SET_USED(priorities);
797 for (link = 0; link < nb_links; link++)
798 hwgrp_ids[link] = queues[link];
799 nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
801 return (int)nb_links;
805 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
806 uint8_t queues[], uint16_t nb_unlinks)
808 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
809 uint16_t hwgrp_ids[nb_unlinks];
812 for (unlink = 0; unlink < nb_unlinks; unlink++)
813 hwgrp_ids[unlink] = queues[unlink];
814 nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
816 return (int)nb_unlinks;
820 cn9k_sso_start(struct rte_eventdev *event_dev)
824 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
828 rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
829 cn9k_sso_hws_flush_events);
833 cn9k_sso_fp_fns_set(event_dev);
839 cn9k_sso_stop(struct rte_eventdev *event_dev)
841 cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
845 cn9k_sso_close(struct rte_eventdev *event_dev)
847 return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
851 cn9k_sso_selftest(void)
853 return cnxk_sso_selftest(RTE_STR(event_cn9k));
857 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
858 const struct rte_eth_dev *eth_dev, uint32_t *caps)
862 RTE_SET_USED(event_dev);
863 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
865 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
867 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
868 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
869 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
875 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
878 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
881 for (i = 0; i < dev->nb_event_ports; i++) {
883 struct cn9k_sso_hws_dual *dws =
884 event_dev->data->ports[i];
885 dws->lookup_mem = lookup_mem;
886 dws->tstamp = tstmp_info;
888 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
889 ws->lookup_mem = lookup_mem;
890 ws->tstamp = tstmp_info;
896 cn9k_sso_rx_adapter_queue_add(
897 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
899 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
901 struct cn9k_eth_rxq *rxq;
906 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
910 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
915 rxq = eth_dev->data->rx_queues[0];
916 lookup_mem = rxq->lookup_mem;
917 tstmp_info = rxq->tstamp;
918 cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
919 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
925 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
926 const struct rte_eth_dev *eth_dev,
931 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
935 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
939 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
940 const struct rte_eth_dev *eth_dev, uint32_t *caps)
945 ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
949 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
955 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id,
958 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
959 struct cn9k_eth_txq *txq;
960 struct roc_nix_sq *sq;
963 if (tx_queue_id < 0) {
964 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
965 cn9k_sso_txq_fc_update(eth_dev, i, ena);
969 sq = &cnxk_eth_dev->sqs[tx_queue_id];
970 txq = eth_dev->data->tx_queues[tx_queue_id];
972 ena ? RTE_MIN(CNXK_SSO_SQB_LIMIT, sq->aura_sqb_bufs) :
974 txq->nb_sqb_bufs_adj =
976 RTE_ALIGN_MUL_CEIL(sq_limit,
977 (1ULL << txq->sqes_per_sqb_log2)) /
978 (1ULL << txq->sqes_per_sqb_log2);
979 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
984 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
985 const struct rte_eth_dev *eth_dev,
988 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
989 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
990 uint64_t tx_offloads;
994 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
998 /* Can't enable tstamp if all the ports don't have it enabled. */
999 tx_offloads = cnxk_eth_dev->tx_offload_flags;
1000 if (dev->tx_adptr_configured) {
1001 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
1003 !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
1005 if (tstmp_ena && !tstmp_req)
1006 dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
1007 else if (!tstmp_ena && tstmp_req)
1008 tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
1011 dev->tx_offloads |= tx_offloads;
1012 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);
1013 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
1016 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1017 dev->tx_adptr_configured = 1;
1023 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
1024 const struct rte_eth_dev *eth_dev,
1025 int32_t tx_queue_id)
1030 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
1033 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, false);
1034 return cn9k_sso_updt_tx_adptr_data(event_dev);
1038 cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
1039 const struct rte_cryptodev *cdev, uint32_t *caps)
1041 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1042 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1044 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
1045 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
1051 cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
1052 const struct rte_cryptodev *cdev,
1053 int32_t queue_pair_id, const struct rte_event *event)
1055 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1057 RTE_SET_USED(event);
1059 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1060 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1062 dev->is_ca_internal_port = 1;
1063 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1065 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
1069 cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
1070 const struct rte_cryptodev *cdev,
1071 int32_t queue_pair_id)
1073 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1074 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1076 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
1079 static struct eventdev_ops cn9k_sso_dev_ops = {
1080 .dev_infos_get = cn9k_sso_info_get,
1081 .dev_configure = cn9k_sso_dev_configure,
1082 .queue_def_conf = cnxk_sso_queue_def_conf,
1083 .queue_setup = cnxk_sso_queue_setup,
1084 .queue_release = cnxk_sso_queue_release,
1085 .port_def_conf = cnxk_sso_port_def_conf,
1086 .port_setup = cn9k_sso_port_setup,
1087 .port_release = cn9k_sso_port_release,
1088 .port_link = cn9k_sso_port_link,
1089 .port_unlink = cn9k_sso_port_unlink,
1090 .timeout_ticks = cnxk_sso_timeout_ticks,
1092 .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1093 .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1094 .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1095 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1096 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1098 .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1099 .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1100 .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1102 .timer_adapter_caps_get = cnxk_tim_caps_get,
1104 .crypto_adapter_caps_get = cn9k_crypto_adapter_caps_get,
1105 .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add,
1106 .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del,
1108 .dump = cnxk_sso_dump,
1109 .dev_start = cn9k_sso_start,
1110 .dev_stop = cn9k_sso_stop,
1111 .dev_close = cn9k_sso_close,
1112 .dev_selftest = cn9k_sso_selftest,
1116 cn9k_sso_init(struct rte_eventdev *event_dev)
1118 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1121 if (RTE_CACHE_LINE_SIZE != 128) {
1122 plt_err("Driver not compiled for CN9K");
1126 rc = roc_plt_init();
1128 plt_err("Failed to initialize platform model");
1132 event_dev->dev_ops = &cn9k_sso_dev_ops;
1133 /* For secondary processes, the primary has done all the work */
1134 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1135 cn9k_sso_fp_fns_set(event_dev);
1139 rc = cnxk_sso_init(event_dev);
1143 cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1144 if (!dev->max_event_ports || !dev->max_event_queues) {
1145 plt_err("Not enough eventdev resource queues=%d ports=%d",
1146 dev->max_event_queues, dev->max_event_ports);
1147 cnxk_sso_fini(event_dev);
1151 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1152 event_dev->data->name, dev->max_event_queues,
1153 dev->max_event_ports);
1159 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1161 return rte_event_pmd_pci_probe(
1162 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1165 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1166 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1167 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1168 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1169 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1170 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1171 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1172 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1173 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1174 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1175 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1181 static struct rte_pci_driver cn9k_pci_sso = {
1182 .id_table = cn9k_pci_sso_map,
1183 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1184 .probe = cn9k_sso_probe,
1185 .remove = cnxk_sso_remove,
1188 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1189 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1190 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1191 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1192 CNXK_SSO_GGRP_QOS "=<string>"
1193 CNXK_SSO_FORCE_BP "=1"
1194 CN9K_SSO_SINGLE_WS "=1"
1195 CNXK_TIM_DISABLE_NPA "=1"
1196 CNXK_TIM_CHNK_SLOTS "=<int>"
1197 CNXK_TIM_RINGS_LMT "=<int>"
1198 CNXK_TIM_STATS_ENA "=1");