1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn9k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN9K_DUAL_WS_NB_WS 2
10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
12 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
13 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
15 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
16 enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
19 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
21 struct cnxk_sso_evdev *dev = arg;
22 struct cn9k_sso_hws_dual *dws;
23 struct cn9k_sso_hws *ws;
28 rc = roc_sso_hws_link(&dev->sso,
29 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
31 rc |= roc_sso_hws_link(&dev->sso,
32 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
36 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
43 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
45 struct cnxk_sso_evdev *dev = arg;
46 struct cn9k_sso_hws_dual *dws;
47 struct cn9k_sso_hws *ws;
52 rc = roc_sso_hws_unlink(&dev->sso,
53 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
55 rc |= roc_sso_hws_unlink(&dev->sso,
56 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
60 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
67 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
69 struct cnxk_sso_evdev *dev = arg;
70 struct cn9k_sso_hws_dual *dws;
71 struct cn9k_sso_hws *ws;
74 /* Set get_work tmo for HWS */
75 val = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0;
78 dws->grp_base = grp_base;
79 dws->fc_mem = (uint64_t *)dev->fc_iova;
80 dws->xaq_lmt = dev->xaq_lmt;
82 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
83 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
86 ws->grp_base = grp_base;
87 ws->fc_mem = (uint64_t *)dev->fc_iova;
88 ws->xaq_lmt = dev->xaq_lmt;
90 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
95 cn9k_sso_hws_release(void *arg, void *hws)
97 struct cnxk_sso_evdev *dev = arg;
98 struct cn9k_sso_hws_dual *dws;
99 struct cn9k_sso_hws *ws;
104 for (i = 0; i < dev->nb_event_queues; i++) {
105 roc_sso_hws_unlink(&dev->sso,
106 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
108 roc_sso_hws_unlink(&dev->sso,
109 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
112 memset(dws, 0, sizeof(*dws));
115 for (i = 0; i < dev->nb_event_queues; i++)
116 roc_sso_hws_unlink(&dev->sso, ws->hws_id,
118 memset(ws, 0, sizeof(*ws));
123 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
124 cnxk_handle_event_t fn, void *arg)
126 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
127 struct cn9k_sso_hws_dual *dws;
128 struct cn9k_sso_hws *ws;
129 uint64_t cq_ds_cnt = 1;
136 plt_write64(0, base + SSO_LF_GGRP_QCTL);
138 req = queue_id; /* GGRP ID */
139 req |= BIT_ULL(18); /* Grouped */
140 req |= BIT_ULL(16); /* WAIT */
142 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
143 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
144 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
145 cq_ds_cnt &= 0x3FFF3FFF0000;
149 ws_base = dws->base[0];
155 while (aq_cnt || cq_ds_cnt || ds_cnt) {
156 plt_write64(req, ws_base + SSOW_LF_GWS_OP_GET_WORK0);
157 cn9k_sso_hws_get_work_empty(ws_base, &ev);
158 if (fn != NULL && ev.u64 != 0)
160 if (ev.sched_type != SSO_TT_EMPTY)
161 cnxk_sso_hws_swtag_flush(
162 ws_base + SSOW_LF_GWS_TAG,
163 ws_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
165 val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
166 } while (val & BIT_ULL(56));
167 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
168 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
169 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
170 /* Extract cq and ds count */
171 cq_ds_cnt &= 0x3FFF3FFF0000;
174 plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
178 cn9k_sso_hws_reset(void *arg, void *hws)
180 struct cnxk_sso_evdev *dev = arg;
181 struct cn9k_sso_hws_dual *dws;
182 struct cn9k_sso_hws *ws;
191 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
192 base = dev->dual_ws ? dws->base[i] : ws->base;
193 /* Wait till getwork/swtp/waitw/desched completes. */
195 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
196 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
199 tag = plt_read64(base + SSOW_LF_GWS_TAG);
200 pend_tt = (tag >> 32) & 0x3;
201 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
202 if (pend_tt == SSO_TT_ATOMIC ||
203 pend_tt == SSO_TT_ORDERED)
204 cnxk_sso_hws_swtag_untag(
205 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
206 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
209 /* Wait for desched to complete. */
211 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
212 } while (pend_state & BIT_ULL(58));
217 cn9k_sso_set_rsrc(void *arg)
219 struct cnxk_sso_evdev *dev = arg;
222 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
224 dev->max_event_ports = dev->sso.max_hws;
225 dev->max_event_queues =
226 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
227 RTE_EVENT_MAX_QUEUES_PER_DEV :
232 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
234 struct cnxk_sso_evdev *dev = arg;
237 hws = hws * CN9K_DUAL_WS_NB_WS;
239 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
243 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
245 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
248 if (dev->tx_adptr_data == NULL)
251 for (i = 0; i < dev->nb_event_ports; i++) {
253 struct cn9k_sso_hws_dual *dws =
254 event_dev->data->ports[i];
257 ws_cookie = cnxk_sso_hws_get_cookie(dws);
258 ws_cookie = rte_realloc_socket(
260 sizeof(struct cnxk_sso_hws_cookie) +
261 sizeof(struct cn9k_sso_hws_dual) +
262 dev->tx_adptr_data_sz,
263 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
264 if (ws_cookie == NULL)
266 dws = RTE_PTR_ADD(ws_cookie,
267 sizeof(struct cnxk_sso_hws_cookie));
268 memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
269 dev->tx_adptr_data_sz);
270 event_dev->data->ports[i] = dws;
272 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
275 ws_cookie = cnxk_sso_hws_get_cookie(ws);
276 ws_cookie = rte_realloc_socket(
278 sizeof(struct cnxk_sso_hws_cookie) +
279 sizeof(struct cn9k_sso_hws_dual) +
280 dev->tx_adptr_data_sz,
281 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
282 if (ws_cookie == NULL)
284 ws = RTE_PTR_ADD(ws_cookie,
285 sizeof(struct cnxk_sso_hws_cookie));
286 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
287 dev->tx_adptr_data_sz);
288 event_dev->data->ports[i] = ws;
297 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
299 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
300 /* Single WS modes */
301 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
302 #define R(name, flags)[flags] = cn9k_sso_hws_deq_##name,
303 NIX_RX_FASTPATH_MODES
307 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
308 #define R(name, flags)[flags] = cn9k_sso_hws_deq_burst_##name,
309 NIX_RX_FASTPATH_MODES
313 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
314 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_##name,
315 NIX_RX_FASTPATH_MODES
319 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
320 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_burst_##name,
321 NIX_RX_FASTPATH_MODES
325 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
326 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_##name,
327 NIX_RX_FASTPATH_MODES
331 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
332 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_burst_##name,
333 NIX_RX_FASTPATH_MODES
337 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
338 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_##name,
339 NIX_RX_FASTPATH_MODES
343 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
344 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_burst_##name,
345 NIX_RX_FASTPATH_MODES
349 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
350 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_##name,
351 NIX_RX_FASTPATH_MODES
355 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
356 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_burst_##name,
357 NIX_RX_FASTPATH_MODES
361 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
362 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_##name,
363 NIX_RX_FASTPATH_MODES
367 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
368 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
369 NIX_RX_FASTPATH_MODES
373 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
374 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_##name,
375 NIX_RX_FASTPATH_MODES
379 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
380 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_burst_##name,
381 NIX_RX_FASTPATH_MODES
385 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
386 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_##name,
387 NIX_RX_FASTPATH_MODES
391 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
392 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_burst_##name,
393 NIX_RX_FASTPATH_MODES
398 const event_dequeue_t sso_hws_dual_deq[NIX_RX_OFFLOAD_MAX] = {
399 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_##name,
400 NIX_RX_FASTPATH_MODES
404 const event_dequeue_burst_t sso_hws_dual_deq_burst[NIX_RX_OFFLOAD_MAX] = {
405 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_burst_##name,
406 NIX_RX_FASTPATH_MODES
410 const event_dequeue_t sso_hws_dual_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
411 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_##name,
412 NIX_RX_FASTPATH_MODES
416 const event_dequeue_burst_t sso_hws_dual_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
417 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
418 NIX_RX_FASTPATH_MODES
422 const event_dequeue_t sso_hws_dual_deq_ca[NIX_RX_OFFLOAD_MAX] = {
423 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_##name,
424 NIX_RX_FASTPATH_MODES
428 const event_dequeue_burst_t sso_hws_dual_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
429 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_burst_##name,
430 NIX_RX_FASTPATH_MODES
434 const event_dequeue_t sso_hws_dual_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
435 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_##name,
436 NIX_RX_FASTPATH_MODES
440 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
441 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_burst_##name,
442 NIX_RX_FASTPATH_MODES
446 const event_dequeue_t sso_hws_dual_deq_seg[NIX_RX_OFFLOAD_MAX] = {
447 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_##name,
448 NIX_RX_FASTPATH_MODES
452 const event_dequeue_burst_t sso_hws_dual_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
453 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_burst_##name,
454 NIX_RX_FASTPATH_MODES
458 const event_dequeue_t sso_hws_dual_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
459 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
460 NIX_RX_FASTPATH_MODES
464 const event_dequeue_burst_t sso_hws_dual_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
465 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
466 NIX_RX_FASTPATH_MODES
470 const event_dequeue_t sso_hws_dual_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
471 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_##name,
472 NIX_RX_FASTPATH_MODES
476 const event_dequeue_burst_t sso_hws_dual_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
477 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
478 NIX_RX_FASTPATH_MODES
482 const event_dequeue_t sso_hws_dual_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
483 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_##name,
484 NIX_RX_FASTPATH_MODES
488 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
489 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name,
490 NIX_RX_FASTPATH_MODES
495 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
496 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_##name,
497 NIX_TX_FASTPATH_MODES
501 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
502 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
503 NIX_TX_FASTPATH_MODES
507 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
508 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
509 NIX_TX_FASTPATH_MODES
513 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
514 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
515 NIX_TX_FASTPATH_MODES
519 event_dev->enqueue = cn9k_sso_hws_enq;
520 event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
521 event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
522 event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
523 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
524 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);
525 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
526 sso_hws_deq_seg_burst);
527 if (dev->is_timeout_deq) {
528 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
529 sso_hws_deq_tmo_seg);
530 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
531 sso_hws_deq_tmo_seg_burst);
533 if (dev->is_ca_internal_port) {
534 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
536 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
537 sso_hws_deq_ca_seg_burst);
540 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
541 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
542 sso_hws_deq_tmo_ca_seg);
543 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
544 sso_hws_deq_tmo_ca_seg_burst);
547 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
548 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
550 if (dev->is_timeout_deq) {
551 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
553 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
554 sso_hws_deq_tmo_burst);
556 if (dev->is_ca_internal_port) {
557 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
559 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
560 sso_hws_deq_ca_burst);
563 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
564 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
566 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
567 sso_hws_deq_tmo_ca_burst);
570 event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
572 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
573 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
574 sso_hws_tx_adptr_enq_seg);
576 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
577 sso_hws_tx_adptr_enq);
580 event_dev->enqueue = cn9k_sso_hws_dual_enq;
581 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
582 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
583 event_dev->enqueue_forward_burst =
584 cn9k_sso_hws_dual_enq_fwd_burst;
585 event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
587 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
588 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
589 sso_hws_dual_deq_seg);
590 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
591 sso_hws_dual_deq_seg_burst);
592 if (dev->is_timeout_deq) {
593 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
594 sso_hws_dual_deq_tmo_seg);
595 CN9K_SET_EVDEV_DEQ_OP(
596 dev, event_dev->dequeue_burst,
597 sso_hws_dual_deq_tmo_seg_burst);
599 if (dev->is_ca_internal_port) {
600 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
601 sso_hws_dual_deq_ca_seg);
602 CN9K_SET_EVDEV_DEQ_OP(
603 dev, event_dev->dequeue_burst,
604 sso_hws_dual_deq_ca_seg_burst);
606 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
607 CN9K_SET_EVDEV_DEQ_OP(
608 dev, event_dev->dequeue,
609 sso_hws_dual_deq_tmo_ca_seg);
610 CN9K_SET_EVDEV_DEQ_OP(
611 dev, event_dev->dequeue_burst,
612 sso_hws_dual_deq_tmo_ca_seg_burst);
615 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
617 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
618 sso_hws_dual_deq_burst);
619 if (dev->is_timeout_deq) {
620 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
621 sso_hws_dual_deq_tmo);
622 CN9K_SET_EVDEV_DEQ_OP(
623 dev, event_dev->dequeue_burst,
624 sso_hws_dual_deq_tmo_burst);
626 if (dev->is_ca_internal_port) {
627 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
628 sso_hws_dual_deq_ca);
629 CN9K_SET_EVDEV_DEQ_OP(
630 dev, event_dev->dequeue_burst,
631 sso_hws_dual_deq_ca_burst);
633 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
634 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
635 sso_hws_dual_deq_tmo_ca);
636 CN9K_SET_EVDEV_DEQ_OP(
637 dev, event_dev->dequeue_burst,
638 sso_hws_dual_deq_tmo_ca_burst);
642 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
643 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
644 sso_hws_dual_tx_adptr_enq_seg);
646 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
647 sso_hws_dual_tx_adptr_enq);
650 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
655 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
657 struct cnxk_sso_evdev *dev = arg;
658 struct cn9k_sso_hws_dual *dws;
659 struct cn9k_sso_hws *ws;
663 dws = rte_zmalloc("cn9k_dual_ws",
664 sizeof(struct cn9k_sso_hws_dual) +
666 RTE_CACHE_LINE_SIZE);
668 plt_err("Failed to alloc memory for port=%d", port_id);
672 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
673 dws->base[0] = roc_sso_hws_base_get(
674 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
675 dws->base[1] = roc_sso_hws_base_get(
676 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
677 dws->hws_id = port_id;
683 /* Allocate event port memory */
684 ws = rte_zmalloc("cn9k_ws",
685 sizeof(struct cn9k_sso_hws) +
687 RTE_CACHE_LINE_SIZE);
689 plt_err("Failed to alloc memory for port=%d", port_id);
693 /* First cache line is reserved for cookie */
694 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
695 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
696 ws->hws_id = port_id;
706 cn9k_sso_info_get(struct rte_eventdev *event_dev,
707 struct rte_event_dev_info *dev_info)
709 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
711 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
712 cnxk_sso_info_get(dev, dev_info);
716 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
718 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
721 rc = cnxk_sso_dev_validate(event_dev);
723 plt_err("Invalid event device configuration");
727 rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
729 plt_err("Failed to initialize SSO resources");
733 rc = cnxk_sso_xaq_allocate(dev);
737 rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
742 /* Restore any prior port-queue mapping. */
743 cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
750 roc_sso_rsrc_fini(&dev->sso);
751 dev->nb_event_ports = 0;
756 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
757 const struct rte_event_port_conf *port_conf)
760 RTE_SET_USED(port_conf);
761 return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
765 cn9k_sso_port_release(void *port)
767 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
768 struct cnxk_sso_evdev *dev;
773 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
774 if (!gws_cookie->configured)
777 cn9k_sso_hws_release(dev, port);
778 memset(gws_cookie, 0, sizeof(*gws_cookie));
780 rte_free(gws_cookie);
784 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
785 const uint8_t queues[], const uint8_t priorities[],
788 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
789 uint16_t hwgrp_ids[nb_links];
792 RTE_SET_USED(priorities);
793 for (link = 0; link < nb_links; link++)
794 hwgrp_ids[link] = queues[link];
795 nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
797 return (int)nb_links;
801 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
802 uint8_t queues[], uint16_t nb_unlinks)
804 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
805 uint16_t hwgrp_ids[nb_unlinks];
808 for (unlink = 0; unlink < nb_unlinks; unlink++)
809 hwgrp_ids[unlink] = queues[unlink];
810 nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
812 return (int)nb_unlinks;
816 cn9k_sso_start(struct rte_eventdev *event_dev)
820 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
824 rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
825 cn9k_sso_hws_flush_events);
829 cn9k_sso_fp_fns_set(event_dev);
835 cn9k_sso_stop(struct rte_eventdev *event_dev)
837 cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
841 cn9k_sso_close(struct rte_eventdev *event_dev)
843 return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
847 cn9k_sso_selftest(void)
849 return cnxk_sso_selftest(RTE_STR(event_cn9k));
853 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
854 const struct rte_eth_dev *eth_dev, uint32_t *caps)
858 RTE_SET_USED(event_dev);
859 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
861 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
863 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
864 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
865 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
871 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
874 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
877 for (i = 0; i < dev->nb_event_ports; i++) {
879 struct cn9k_sso_hws_dual *dws =
880 event_dev->data->ports[i];
881 dws->lookup_mem = lookup_mem;
882 dws->tstamp = tstmp_info;
884 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
885 ws->lookup_mem = lookup_mem;
886 ws->tstamp = tstmp_info;
892 cn9k_sso_rx_adapter_queue_add(
893 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
895 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
897 struct cn9k_eth_rxq *rxq;
902 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
906 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
911 rxq = eth_dev->data->rx_queues[0];
912 lookup_mem = rxq->lookup_mem;
913 tstmp_info = rxq->tstamp;
914 cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
915 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
921 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
922 const struct rte_eth_dev *eth_dev,
927 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
931 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
935 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
936 const struct rte_eth_dev *eth_dev, uint32_t *caps)
941 ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
945 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
951 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id,
954 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
955 struct cn9k_eth_txq *txq;
956 struct roc_nix_sq *sq;
959 if (tx_queue_id < 0) {
960 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
961 cn9k_sso_txq_fc_update(eth_dev, i, ena);
965 sq = &cnxk_eth_dev->sqs[tx_queue_id];
966 txq = eth_dev->data->tx_queues[tx_queue_id];
968 ena ? RTE_MIN(CNXK_SSO_SQB_LIMIT, sq->aura_sqb_bufs) :
970 txq->nb_sqb_bufs_adj =
972 RTE_ALIGN_MUL_CEIL(sq_limit,
973 (1ULL << txq->sqes_per_sqb_log2)) /
974 (1ULL << txq->sqes_per_sqb_log2);
975 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
980 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
981 const struct rte_eth_dev *eth_dev,
984 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
985 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
986 uint64_t tx_offloads;
990 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
994 /* Can't enable tstamp if all the ports don't have it enabled. */
995 tx_offloads = cnxk_eth_dev->tx_offload_flags;
996 if (dev->tx_adptr_configured) {
997 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
999 !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
1001 if (tstmp_ena && !tstmp_req)
1002 dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
1003 else if (!tstmp_ena && tstmp_req)
1004 tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
1007 dev->tx_offloads |= tx_offloads;
1008 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);
1009 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
1012 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1013 dev->tx_adptr_configured = 1;
1019 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
1020 const struct rte_eth_dev *eth_dev,
1021 int32_t tx_queue_id)
1026 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
1029 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, false);
1030 return cn9k_sso_updt_tx_adptr_data(event_dev);
1034 cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
1035 const struct rte_cryptodev *cdev, uint32_t *caps)
1037 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1038 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1040 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
1041 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
1047 cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
1048 const struct rte_cryptodev *cdev,
1049 int32_t queue_pair_id, const struct rte_event *event)
1051 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1053 RTE_SET_USED(event);
1055 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1056 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1058 dev->is_ca_internal_port = 1;
1059 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1061 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
1065 cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
1066 const struct rte_cryptodev *cdev,
1067 int32_t queue_pair_id)
1069 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1070 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1072 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
1075 static struct eventdev_ops cn9k_sso_dev_ops = {
1076 .dev_infos_get = cn9k_sso_info_get,
1077 .dev_configure = cn9k_sso_dev_configure,
1078 .queue_def_conf = cnxk_sso_queue_def_conf,
1079 .queue_setup = cnxk_sso_queue_setup,
1080 .queue_release = cnxk_sso_queue_release,
1081 .port_def_conf = cnxk_sso_port_def_conf,
1082 .port_setup = cn9k_sso_port_setup,
1083 .port_release = cn9k_sso_port_release,
1084 .port_link = cn9k_sso_port_link,
1085 .port_unlink = cn9k_sso_port_unlink,
1086 .timeout_ticks = cnxk_sso_timeout_ticks,
1088 .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1089 .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1090 .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1091 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1092 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1094 .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1095 .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1096 .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1098 .timer_adapter_caps_get = cnxk_tim_caps_get,
1100 .crypto_adapter_caps_get = cn9k_crypto_adapter_caps_get,
1101 .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add,
1102 .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del,
1104 .dump = cnxk_sso_dump,
1105 .dev_start = cn9k_sso_start,
1106 .dev_stop = cn9k_sso_stop,
1107 .dev_close = cn9k_sso_close,
1108 .dev_selftest = cn9k_sso_selftest,
1112 cn9k_sso_init(struct rte_eventdev *event_dev)
1114 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1117 if (RTE_CACHE_LINE_SIZE != 128) {
1118 plt_err("Driver not compiled for CN9K");
1122 rc = roc_plt_init();
1124 plt_err("Failed to initialize platform model");
1128 event_dev->dev_ops = &cn9k_sso_dev_ops;
1129 /* For secondary processes, the primary has done all the work */
1130 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1131 cn9k_sso_fp_fns_set(event_dev);
1135 rc = cnxk_sso_init(event_dev);
1139 cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1140 if (!dev->max_event_ports || !dev->max_event_queues) {
1141 plt_err("Not enough eventdev resource queues=%d ports=%d",
1142 dev->max_event_queues, dev->max_event_ports);
1143 cnxk_sso_fini(event_dev);
1147 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1148 event_dev->data->name, dev->max_event_queues,
1149 dev->max_event_ports);
1155 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1157 return rte_event_pmd_pci_probe(
1158 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1161 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1162 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1163 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1164 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1165 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1166 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1167 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1168 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1169 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1170 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1171 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1177 static struct rte_pci_driver cn9k_pci_sso = {
1178 .id_table = cn9k_pci_sso_map,
1179 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1180 .probe = cn9k_sso_probe,
1181 .remove = cnxk_sso_remove,
1184 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1185 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1186 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1187 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1188 CNXK_SSO_GGRP_QOS "=<string>"
1189 CNXK_SSO_FORCE_BP "=1"
1190 CN9K_SSO_SINGLE_WS "=1"
1191 CNXK_TIM_DISABLE_NPA "=1"
1192 CNXK_TIM_CHNK_SLOTS "=<int>"
1193 CNXK_TIM_RINGS_LMT "=<int>"
1194 CNXK_TIM_STATS_ENA "=1");