drivers/event/cnxk/cn9k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn9k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN9K_DUAL_WS_NB_WS          2
  10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
  11
  12 static void
  13 cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base)
  14 {
  15         ws->tag_op = base + SSOW_LF_GWS_TAG;
  16         ws->wqp_op = base + SSOW_LF_GWS_WQP;
  17         ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0;
  18         ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;
  19         ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
  20         ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
  21 }
  22
  23 static int
  24 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  25 {
  26         struct cnxk_sso_evdev *dev = arg;
  27         struct cn9k_sso_hws_dual *dws;
  28         struct cn9k_sso_hws *ws;
  29         int rc;
  30
  31         if (dev->dual_ws) {
  32                 dws = port;
  33                 rc = roc_sso_hws_link(&dev->sso,
  34                                       CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
  35                                       nb_link);
  36                 rc |= roc_sso_hws_link(&dev->sso,
  37                                        CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
  38                                        map, nb_link);
  39         } else {
  40                 ws = port;
  41                 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  42         }
  43
  44         return rc;
  45 }
  46
  47 static int
  48 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  49 {
  50         struct cnxk_sso_evdev *dev = arg;
  51         struct cn9k_sso_hws_dual *dws;
  52         struct cn9k_sso_hws *ws;
  53         int rc;
  54
  55         if (dev->dual_ws) {
  56                 dws = port;
  57                 rc = roc_sso_hws_unlink(&dev->sso,
  58                                         CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
  59                                         map, nb_link);
  60                 rc |= roc_sso_hws_unlink(&dev->sso,
  61                                          CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
  62                                          map, nb_link);
  63         } else {
  64                 ws = port;
  65                 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  66         }
  67
  68         return rc;
  69 }
  70
  71 static void
  72 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
  73 {
  74         struct cnxk_sso_evdev *dev = arg;
  75         struct cn9k_sso_hws_dual *dws;
  76         struct cn9k_sso_hws *ws;
  77         uint64_t val;
  78
  79         /* Set get_work tmo for HWS */
  80         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
  81         if (dev->dual_ws) {
  82                 dws = hws;
  83                 rte_memcpy(dws->grps_base, grps_base,
  84                            sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
  85                 dws->fc_mem = dev->fc_mem;
  86                 dws->xaq_lmt = dev->xaq_lmt;
  87
  88                 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
  89                 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
  90         } else {
  91                 ws = hws;
  92                 rte_memcpy(ws->grps_base, grps_base,
  93                            sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
  94                 ws->fc_mem = dev->fc_mem;
  95                 ws->xaq_lmt = dev->xaq_lmt;
  96
  97                 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  98         }
  99 }
 100
 101 static void
 102 cn9k_sso_hws_release(void *arg, void *hws)
 103 {
 104         struct cnxk_sso_evdev *dev = arg;
 105         struct cn9k_sso_hws_dual *dws;
 106         struct cn9k_sso_hws *ws;
 107         int i;
 108
 109         if (dev->dual_ws) {
 110                 dws = hws;
 111                 for (i = 0; i < dev->nb_event_queues; i++) {
 112                         roc_sso_hws_unlink(&dev->sso,
 113                                            CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
 114                                            (uint16_t *)&i, 1);
 115                         roc_sso_hws_unlink(&dev->sso,
 116                                            CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
 117                                            (uint16_t *)&i, 1);
 118                 }
 119                 memset(dws, 0, sizeof(*dws));
 120         } else {
 121                 ws = hws;
 122                 for (i = 0; i < dev->nb_event_queues; i++)
 123                         roc_sso_hws_unlink(&dev->sso, ws->hws_id,
 124                                            (uint16_t *)&i, 1);
 125                 memset(ws, 0, sizeof(*ws));
 126         }
 127 }
 128
 129 static void
 130 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 131                           cnxk_handle_event_t fn, void *arg)
 132 {
 133         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
 134         struct cn9k_sso_hws_dual *dws;
 135         struct cn9k_sso_hws_state *st;
 136         struct cn9k_sso_hws *ws;
 137         uint64_t cq_ds_cnt = 1;
 138         uint64_t aq_cnt = 1;
 139         uint64_t ds_cnt = 1;
 140         struct rte_event ev;
 141         uintptr_t ws_base;
 142         uint64_t val, req;
 143
 144         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 145
 146         req = queue_id;     /* GGRP ID */
 147         req |= BIT_ULL(18); /* Grouped */
 148         req |= BIT_ULL(16); /* WAIT */
 149
 150         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 151         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 152         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 153         cq_ds_cnt &= 0x3FFF3FFF0000;
 154
 155         if (dev->dual_ws) {
 156                 dws = hws;
 157                 st = &dws->ws_state[0];
 158                 ws_base = dws->base[0];
 159         } else {
 160                 ws = hws;
 161                 st = (struct cn9k_sso_hws_state *)ws;
 162                 ws_base = ws->base;
 163         }
 164
 165         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 166                 plt_write64(req, st->getwrk_op);
 167                 cn9k_sso_hws_get_work_empty(st, &ev);
 168                 if (fn != NULL && ev.u64 != 0)
 169                         fn(arg, ev);
 170                 if (ev.sched_type != SSO_TT_EMPTY)
 171                         cnxk_sso_hws_swtag_flush(st->tag_op,
 172                                                  st->swtag_flush_op);
 173                 do {
 174                         val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
 175                 } while (val & BIT_ULL(56));
 176                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 177                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 178                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 179                 /* Extract cq and ds count */
 180                 cq_ds_cnt &= 0x3FFF3FFF0000;
 181         }
 182
 183         plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
 184 }
 185
 186 static void
 187 cn9k_sso_hws_reset(void *arg, void *hws)
 188 {
 189         struct cnxk_sso_evdev *dev = arg;
 190         struct cn9k_sso_hws_dual *dws;
 191         struct cn9k_sso_hws *ws;
 192         uint64_t pend_state;
 193         uint8_t pend_tt;
 194         uintptr_t base;
 195         uint64_t tag;
 196         uint8_t i;
 197
 198         dws = hws;
 199         ws = hws;
 200         for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
 201                 base = dev->dual_ws ? dws->base[i] : ws->base;
 202                 /* Wait till getwork/swtp/waitw/desched completes. */
 203                 do {
 204                         pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 205                 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 206                                        BIT_ULL(56)));
 207
 208                 tag = plt_read64(base + SSOW_LF_GWS_TAG);
 209                 pend_tt = (tag >> 32) & 0x3;
 210                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 211                         if (pend_tt == SSO_TT_ATOMIC ||
 212                             pend_tt == SSO_TT_ORDERED)
 213                                 cnxk_sso_hws_swtag_untag(
 214                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 215                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 216                 }
 217
 218                 /* Wait for desched to complete. */
 219                 do {
 220                         pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 221                 } while (pend_state & BIT_ULL(58));
 222         }
 223 }
 224
 225 void
 226 cn9k_sso_set_rsrc(void *arg)
 227 {
 228         struct cnxk_sso_evdev *dev = arg;
 229
 230         if (dev->dual_ws)
 231                 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
 232         else
 233                 dev->max_event_ports = dev->sso.max_hws;
 234         dev->max_event_queues =
 235                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 236                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 237                               dev->sso.max_hwgrp;
 238 }
 239
 240 static int
 241 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 242 {
 243         struct cnxk_sso_evdev *dev = arg;
 244
 245         if (dev->dual_ws)
 246                 hws = hws * CN9K_DUAL_WS_NB_WS;
 247
 248         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 249 }
 250
 251 static int
 252 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 253 {
 254         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 255         int i;
 256
 257         if (dev->tx_adptr_data == NULL)
 258                 return 0;
 259
 260         for (i = 0; i < dev->nb_event_ports; i++) {
 261                 if (dev->dual_ws) {
 262                         struct cn9k_sso_hws_dual *dws =
 263                                 event_dev->data->ports[i];
 264                         void *ws_cookie;
 265
 266                         ws_cookie = cnxk_sso_hws_get_cookie(dws);
 267                         ws_cookie = rte_realloc_socket(
 268                                 ws_cookie,
 269                                 sizeof(struct cnxk_sso_hws_cookie) +
 270                                         sizeof(struct cn9k_sso_hws_dual) +
 271                                         (sizeof(uint64_t) *
 272                                          (dev->max_port_id + 1) *
 273                                          RTE_MAX_QUEUES_PER_PORT),
 274                                 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 275                         if (ws_cookie == NULL)
 276                                 return -ENOMEM;
 277                         dws = RTE_PTR_ADD(ws_cookie,
 278                                           sizeof(struct cnxk_sso_hws_cookie));
 279                         memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
 280                                sizeof(uint64_t) * (dev->max_port_id + 1) *
 281                                        RTE_MAX_QUEUES_PER_PORT);
 282                         event_dev->data->ports[i] = dws;
 283                 } else {
 284                         struct cn9k_sso_hws *ws = event_dev->data->ports[i];
 285                         void *ws_cookie;
 286
 287                         ws_cookie = cnxk_sso_hws_get_cookie(ws);
 288                         ws_cookie = rte_realloc_socket(
 289                                 ws_cookie,
 290                                 sizeof(struct cnxk_sso_hws_cookie) +
 291                                         sizeof(struct cn9k_sso_hws_dual) +
 292                                         (sizeof(uint64_t) *
 293                                          (dev->max_port_id + 1) *
 294                                          RTE_MAX_QUEUES_PER_PORT),
 295                                 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 296                         if (ws_cookie == NULL)
 297                                 return -ENOMEM;
 298                         ws = RTE_PTR_ADD(ws_cookie,
 299                                          sizeof(struct cnxk_sso_hws_cookie));
 300                         memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 301                                sizeof(uint64_t) * (dev->max_port_id + 1) *
 302                                        RTE_MAX_QUEUES_PER_PORT);
 303                         event_dev->data->ports[i] = ws;
 304                 }
 305         }
 306         rte_mb();
 307
 308         return 0;
 309 }
 310
 311 static void
 312 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 313 {
 314         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 315         /* Single WS modes */
 316         const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {
 317 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 318         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
 319                 NIX_RX_FASTPATH_MODES
 320 #undef R
 321         };
 322
 323         const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {
 324 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 325         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
 326                 NIX_RX_FASTPATH_MODES
 327 #undef R
 328         };
 329
 330         const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {
 331 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 332         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
 333                 NIX_RX_FASTPATH_MODES
 334 #undef R
 335         };
 336
 337         const event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {
 338 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 339         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
 340                 NIX_RX_FASTPATH_MODES
 341 #undef R
 342         };
 343
 344         const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
 345 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 346         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
 347                 NIX_RX_FASTPATH_MODES
 348 #undef R
 349         };
 350
 351         const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {
 352 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 353         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
 354                 NIX_RX_FASTPATH_MODES
 355 #undef R
 356         };
 357
 358         const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {
 359 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 360         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
 361                 NIX_RX_FASTPATH_MODES
 362 #undef R
 363         };
 364
 365         const event_dequeue_burst_t
 366                 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {
 367 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 368         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
 369                         NIX_RX_FASTPATH_MODES
 370 #undef R
 371                 };
 372
 373         /* Dual WS modes */
 374         const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2] = {
 375 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 376         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
 377                 NIX_RX_FASTPATH_MODES
 378 #undef R
 379         };
 380
 381         const event_dequeue_burst_t sso_hws_dual_deq_burst[2][2][2][2][2][2] = {
 382 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 383         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
 384                 NIX_RX_FASTPATH_MODES
 385 #undef R
 386         };
 387
 388         const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2] = {
 389 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 390         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
 391                 NIX_RX_FASTPATH_MODES
 392 #undef R
 393         };
 394
 395         const event_dequeue_burst_t
 396                 sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2] = {
 397 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 398         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
 399                         NIX_RX_FASTPATH_MODES
 400 #undef R
 401                 };
 402
 403         const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2] = {
 404 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 405         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
 406                 NIX_RX_FASTPATH_MODES
 407 #undef R
 408         };
 409
 410         const event_dequeue_burst_t
 411                 sso_hws_dual_deq_seg_burst[2][2][2][2][2][2] = {
 412 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 413         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
 414                         NIX_RX_FASTPATH_MODES
 415 #undef R
 416                 };
 417
 418         const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2] = {
 419 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 420         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
 421                 NIX_RX_FASTPATH_MODES
 422 #undef R
 423         };
 424
 425         const event_dequeue_burst_t
 426                 sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2] = {
 427 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 428         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
 429                         NIX_RX_FASTPATH_MODES
 430 #undef R
 431                 };
 432
 433         /* Tx modes */
 434         const event_tx_adapter_enqueue
 435                 sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
 436 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
 437         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_##name,
 438                         NIX_TX_FASTPATH_MODES
 439 #undef T
 440                 };
 441
 442         const event_tx_adapter_enqueue
 443                 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
 444 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
 445         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
 446                         NIX_TX_FASTPATH_MODES
 447 #undef T
 448                 };
 449
 450         const event_tx_adapter_enqueue
 451                 sso_hws_dual_tx_adptr_enq[2][2][2][2][2][2] = {
 452 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
 453         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
 454                         NIX_TX_FASTPATH_MODES
 455 #undef T
 456                 };
 457
 458         const event_tx_adapter_enqueue
 459                 sso_hws_dual_tx_adptr_enq_seg[2][2][2][2][2][2] = {
 460 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags)                             \
 461         [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
 462                         NIX_TX_FASTPATH_MODES
 463 #undef T
 464                 };
 465
 466         event_dev->enqueue = cn9k_sso_hws_enq;
 467         event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
 468         event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
 469         event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
 470         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 471                 event_dev->dequeue = sso_hws_deq_seg
 472                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 473                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 474                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 475                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 476                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 477                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 478                 event_dev->dequeue_burst = sso_hws_deq_seg_burst
 479                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 480                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 481                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 482                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 483                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 484                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 485                 if (dev->is_timeout_deq) {
 486                         event_dev->dequeue = sso_hws_deq_tmo_seg
 487                                 [!!(dev->rx_offloads &
 488                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 489                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 490                                 [!!(dev->rx_offloads &
 491                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 492                                 [!!(dev->rx_offloads &
 493                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 494                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 495                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 496                         event_dev->dequeue_burst = sso_hws_deq_tmo_seg_burst
 497                                 [!!(dev->rx_offloads &
 498                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 499                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 500                                 [!!(dev->rx_offloads &
 501                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 502                                 [!!(dev->rx_offloads &
 503                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 504                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 505                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 506                 }
 507         } else {
 508                 event_dev->dequeue = sso_hws_deq
 509                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 510                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 511                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 512                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 513                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 514                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 515                 event_dev->dequeue_burst = sso_hws_deq_burst
 516                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 517                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 518                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 519                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 520                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 521                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 522                 if (dev->is_timeout_deq) {
 523                         event_dev->dequeue = sso_hws_deq_tmo
 524                                 [!!(dev->rx_offloads &
 525                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 526                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 527                                 [!!(dev->rx_offloads &
 528                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 529                                 [!!(dev->rx_offloads &
 530                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 531                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 532                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 533                         event_dev->dequeue_burst = sso_hws_deq_tmo_burst
 534                                 [!!(dev->rx_offloads &
 535                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 536                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 537                                 [!!(dev->rx_offloads &
 538                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 539                                 [!!(dev->rx_offloads &
 540                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 541                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 542                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 543                 }
 544         }
 545
 546         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 547                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 548                 event_dev->txa_enqueue = sso_hws_tx_adptr_enq_seg
 549                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 550                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 551                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 552                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 553                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 554                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 555         } else {
 556                 event_dev->txa_enqueue = sso_hws_tx_adptr_enq
 557                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 558                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 559                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 560                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 561                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 562                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 563         }
 564
 565         if (dev->dual_ws) {
 566                 event_dev->enqueue = cn9k_sso_hws_dual_enq;
 567                 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
 568                 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
 569                 event_dev->enqueue_forward_burst =
 570                         cn9k_sso_hws_dual_enq_fwd_burst;
 571
 572                 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 573                         event_dev->dequeue = sso_hws_dual_deq_seg
 574                                 [!!(dev->rx_offloads &
 575                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 576                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 577                                 [!!(dev->rx_offloads &
 578                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 579                                 [!!(dev->rx_offloads &
 580                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 581                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 582                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 583                         event_dev->dequeue_burst = sso_hws_dual_deq_seg_burst
 584                                 [!!(dev->rx_offloads &
 585                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 586                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 587                                 [!!(dev->rx_offloads &
 588                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 589                                 [!!(dev->rx_offloads &
 590                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 591                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 592                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 593                         if (dev->is_timeout_deq) {
 594                                 event_dev->dequeue = sso_hws_dual_deq_tmo_seg
 595                                         [!!(dev->rx_offloads &
 596                                             NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 597                                         [!!(dev->rx_offloads &
 598                                             NIX_RX_OFFLOAD_TSTAMP_F)]
 599                                         [!!(dev->rx_offloads &
 600                                             NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 601                                         [!!(dev->rx_offloads &
 602                                             NIX_RX_OFFLOAD_CHECKSUM_F)]
 603                                         [!!(dev->rx_offloads &
 604                                             NIX_RX_OFFLOAD_PTYPE_F)]
 605                                         [!!(dev->rx_offloads &
 606                                             NIX_RX_OFFLOAD_RSS_F)];
 607                                 event_dev->dequeue_burst =
 608                                         sso_hws_dual_deq_tmo_seg_burst
 609                                                 [!!(dev->rx_offloads &
 610                                                   NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 611                                                 [!!(dev->rx_offloads &
 612                                                     NIX_RX_OFFLOAD_TSTAMP_F)]
 613                                                 [!!(dev->rx_offloads &
 614                                                   NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 615                                                 [!!(dev->rx_offloads &
 616                                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 617                                                 [!!(dev->rx_offloads &
 618                                                     NIX_RX_OFFLOAD_PTYPE_F)]
 619                                                 [!!(dev->rx_offloads &
 620                                                     NIX_RX_OFFLOAD_RSS_F)];
 621                         }
 622                 } else {
 623                         event_dev->dequeue = sso_hws_dual_deq
 624                                 [!!(dev->rx_offloads &
 625                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 626                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 627                                 [!!(dev->rx_offloads &
 628                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 629                                 [!!(dev->rx_offloads &
 630                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 631                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 632                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 633                         event_dev->dequeue_burst = sso_hws_dual_deq_burst
 634                                 [!!(dev->rx_offloads &
 635                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 636                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 637                                 [!!(dev->rx_offloads &
 638                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 639                                 [!!(dev->rx_offloads &
 640                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 641                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 642                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 643                         if (dev->is_timeout_deq) {
 644                                 event_dev->dequeue = sso_hws_dual_deq_tmo
 645                                         [!!(dev->rx_offloads &
 646                                             NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 647                                         [!!(dev->rx_offloads &
 648                                             NIX_RX_OFFLOAD_TSTAMP_F)]
 649                                         [!!(dev->rx_offloads &
 650                                             NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 651                                         [!!(dev->rx_offloads &
 652                                             NIX_RX_OFFLOAD_CHECKSUM_F)]
 653                                         [!!(dev->rx_offloads &
 654                                             NIX_RX_OFFLOAD_PTYPE_F)]
 655                                         [!!(dev->rx_offloads &
 656                                             NIX_RX_OFFLOAD_RSS_F)];
 657                                 event_dev->dequeue_burst =
 658                                         sso_hws_dual_deq_tmo_burst
 659                                                 [!!(dev->rx_offloads &
 660                                                   NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 661                                                 [!!(dev->rx_offloads &
 662                                                   NIX_RX_OFFLOAD_TSTAMP_F)]
 663                                                 [!!(dev->rx_offloads &
 664                                                   NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 665                                                 [!!(dev->rx_offloads &
 666                                                   NIX_RX_OFFLOAD_CHECKSUM_F)]
 667                                                 [!!(dev->rx_offloads &
 668                                                   NIX_RX_OFFLOAD_PTYPE_F)]
 669                                                 [!!(dev->rx_offloads &
 670                                                   NIX_RX_OFFLOAD_RSS_F)];
 671                         }
 672                 }
 673
 674                 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 675                         /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM]
 676                          */
 677                         event_dev->txa_enqueue = sso_hws_dual_tx_adptr_enq_seg
 678                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 679                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 680                                 [!!(dev->tx_offloads &
 681                                     NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 682                                 [!!(dev->tx_offloads &
 683                                     NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 684                                 [!!(dev->tx_offloads &
 685                                     NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 686                                 [!!(dev->tx_offloads &
 687                                     NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 688                 } else {
 689                         event_dev->txa_enqueue = sso_hws_dual_tx_adptr_enq
 690                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 691                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 692                                 [!!(dev->tx_offloads &
 693                                     NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 694                                 [!!(dev->tx_offloads &
 695                                     NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 696                                 [!!(dev->tx_offloads &
 697                                     NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 698                                 [!!(dev->tx_offloads &
 699                                     NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 700                 }
 701         }
 702
 703         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 704         rte_mb();
 705 }
 706
 707 static void *
 708 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
 709 {
 710         struct cnxk_sso_evdev *dev = arg;
 711         struct cn9k_sso_hws_dual *dws;
 712         struct cn9k_sso_hws *ws;
 713         void *data;
 714
 715         if (dev->dual_ws) {
 716                 dws = rte_zmalloc("cn9k_dual_ws",
 717                                   sizeof(struct cn9k_sso_hws_dual) +
 718                                           RTE_CACHE_LINE_SIZE,
 719                                   RTE_CACHE_LINE_SIZE);
 720                 if (dws == NULL) {
 721                         plt_err("Failed to alloc memory for port=%d", port_id);
 722                         return NULL;
 723                 }
 724
 725                 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
 726                 dws->base[0] = roc_sso_hws_base_get(
 727                         &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
 728                 dws->base[1] = roc_sso_hws_base_get(
 729                         &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
 730                 cn9k_init_hws_ops(&dws->ws_state[0], dws->base[0]);
 731                 cn9k_init_hws_ops(&dws->ws_state[1], dws->base[1]);
 732                 dws->hws_id = port_id;
 733                 dws->swtag_req = 0;
 734                 dws->vws = 0;
 735
 736                 data = dws;
 737         } else {
 738                 /* Allocate event port memory */
 739                 ws = rte_zmalloc("cn9k_ws",
 740                                  sizeof(struct cn9k_sso_hws) +
 741                                          RTE_CACHE_LINE_SIZE,
 742                                  RTE_CACHE_LINE_SIZE);
 743                 if (ws == NULL) {
 744                         plt_err("Failed to alloc memory for port=%d", port_id);
 745                         return NULL;
 746                 }
 747
 748                 /* First cache line is reserved for cookie */
 749                 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
 750                 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
 751                 cn9k_init_hws_ops((struct cn9k_sso_hws_state *)ws, ws->base);
 752                 ws->hws_id = port_id;
 753                 ws->swtag_req = 0;
 754
 755                 data = ws;
 756         }
 757
 758         return data;
 759 }
 760
 761 static void
 762 cn9k_sso_info_get(struct rte_eventdev *event_dev,
 763                   struct rte_event_dev_info *dev_info)
 764 {
 765         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 766
 767         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
 768         cnxk_sso_info_get(dev, dev_info);
 769 }
 770
 771 static int
 772 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
 773 {
 774         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 775         int rc;
 776
 777         rc = cnxk_sso_dev_validate(event_dev);
 778         if (rc < 0) {
 779                 plt_err("Invalid event device configuration");
 780                 return -EINVAL;
 781         }
 782
 783         roc_sso_rsrc_fini(&dev->sso);
 784
 785         rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
 786         if (rc < 0) {
 787                 plt_err("Failed to initialize SSO resources");
 788                 return -ENODEV;
 789         }
 790
 791         rc = cnxk_sso_xaq_allocate(dev);
 792         if (rc < 0)
 793                 goto cnxk_rsrc_fini;
 794
 795         rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
 796                                     cn9k_sso_hws_setup);
 797         if (rc < 0)
 798                 goto cnxk_rsrc_fini;
 799
 800         /* Restore any prior port-queue mapping. */
 801         cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
 802
 803         dev->configured = 1;
 804         rte_mb();
 805
 806         return 0;
 807 cnxk_rsrc_fini:
 808         roc_sso_rsrc_fini(&dev->sso);
 809         dev->nb_event_ports = 0;
 810         return rc;
 811 }
 812
 813 static int
 814 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 815                     const struct rte_event_port_conf *port_conf)
 816 {
 817
 818         RTE_SET_USED(port_conf);
 819         return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
 820 }
 821
 822 static void
 823 cn9k_sso_port_release(void *port)
 824 {
 825         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 826         struct cnxk_sso_evdev *dev;
 827
 828         if (port == NULL)
 829                 return;
 830
 831         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 832         if (!gws_cookie->configured)
 833                 goto free;
 834
 835         cn9k_sso_hws_release(dev, port);
 836         memset(gws_cookie, 0, sizeof(*gws_cookie));
 837 free:
 838         rte_free(gws_cookie);
 839 }
 840
 841 static int
 842 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 843                    const uint8_t queues[], const uint8_t priorities[],
 844                    uint16_t nb_links)
 845 {
 846         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 847         uint16_t hwgrp_ids[nb_links];
 848         uint16_t link;
 849
 850         RTE_SET_USED(priorities);
 851         for (link = 0; link < nb_links; link++)
 852                 hwgrp_ids[link] = queues[link];
 853         nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 854
 855         return (int)nb_links;
 856 }
 857
 858 static int
 859 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 860                      uint8_t queues[], uint16_t nb_unlinks)
 861 {
 862         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 863         uint16_t hwgrp_ids[nb_unlinks];
 864         uint16_t unlink;
 865
 866         for (unlink = 0; unlink < nb_unlinks; unlink++)
 867                 hwgrp_ids[unlink] = queues[unlink];
 868         nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 869
 870         return (int)nb_unlinks;
 871 }
 872
 873 static int
 874 cn9k_sso_start(struct rte_eventdev *event_dev)
 875 {
 876         int rc;
 877
 878         rc = cn9k_sso_updt_tx_adptr_data(event_dev);
 879         if (rc < 0)
 880                 return rc;
 881
 882         rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
 883                             cn9k_sso_hws_flush_events);
 884         if (rc < 0)
 885                 return rc;
 886
 887         cn9k_sso_fp_fns_set(event_dev);
 888
 889         return rc;
 890 }
 891
 892 static void
 893 cn9k_sso_stop(struct rte_eventdev *event_dev)
 894 {
 895         cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
 896 }
 897
 898 static int
 899 cn9k_sso_close(struct rte_eventdev *event_dev)
 900 {
 901         return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
 902 }
 903
 904 static int
 905 cn9k_sso_selftest(void)
 906 {
 907         return cnxk_sso_selftest(RTE_STR(event_cn9k));
 908 }
 909
 910 static int
 911 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 912                              const struct rte_eth_dev *eth_dev, uint32_t *caps)
 913 {
 914         int rc;
 915
 916         RTE_SET_USED(event_dev);
 917         rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
 918         if (rc)
 919                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 920         else
 921                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 922                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 923                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
 924
 925         return 0;
 926 }
 927
 928 static void
 929 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 930                       void *tstmp_info)
 931 {
 932         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 933         int i;
 934
 935         for (i = 0; i < dev->nb_event_ports; i++) {
 936                 if (dev->dual_ws) {
 937                         struct cn9k_sso_hws_dual *dws =
 938                                 event_dev->data->ports[i];
 939                         dws->lookup_mem = lookup_mem;
 940                         dws->tstamp = tstmp_info;
 941                 } else {
 942                         struct cn9k_sso_hws *ws = event_dev->data->ports[i];
 943                         ws->lookup_mem = lookup_mem;
 944                         ws->tstamp = tstmp_info;
 945                 }
 946         }
 947 }
 948
 949 static int
 950 cn9k_sso_rx_adapter_queue_add(
 951         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 952         int32_t rx_queue_id,
 953         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 954 {
 955         struct cn9k_eth_rxq *rxq;
 956         void *lookup_mem;
 957         void *tstmp_info;
 958         int rc;
 959
 960         rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
 961         if (rc)
 962                 return -EINVAL;
 963
 964         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 965                                            queue_conf);
 966         if (rc)
 967                 return -EINVAL;
 968
 969         rxq = eth_dev->data->rx_queues[0];
 970         lookup_mem = rxq->lookup_mem;
 971         tstmp_info = rxq->tstamp;
 972         cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 973         cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 974
 975         return 0;
 976 }
 977
 978 static int
 979 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 980                               const struct rte_eth_dev *eth_dev,
 981                               int32_t rx_queue_id)
 982 {
 983         int rc;
 984
 985         rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
 986         if (rc)
 987                 return -EINVAL;
 988
 989         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 990 }
 991
 992 static int
 993 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 994                              const struct rte_eth_dev *eth_dev, uint32_t *caps)
 995 {
 996         int ret;
 997
 998         RTE_SET_USED(dev);
 999         ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
1000         if (ret)
1001                 *caps = 0;
1002         else
1003                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
1004
1005         return 0;
1006 }
1007
1008 static void
1009 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id,
1010                        bool ena)
1011 {
1012         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
1013         struct cn9k_eth_txq *txq;
1014         struct roc_nix_sq *sq;
1015         int i;
1016
1017         if (tx_queue_id < 0) {
1018                 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1019                         cn9k_sso_txq_fc_update(eth_dev, i, ena);
1020         } else {
1021                 uint16_t sq_limit;
1022
1023                 sq = &cnxk_eth_dev->sqs[tx_queue_id];
1024                 txq = eth_dev->data->tx_queues[tx_queue_id];
1025                 sq_limit =
1026                         ena ? RTE_MIN(CNXK_SSO_SQB_LIMIT, sq->aura_sqb_bufs) :
1027                                     sq->nb_sqb_bufs;
1028                 txq->nb_sqb_bufs_adj =
1029                         sq_limit -
1030                         RTE_ALIGN_MUL_CEIL(sq_limit,
1031                                            (1ULL << txq->sqes_per_sqb_log2)) /
1032                                 (1ULL << txq->sqes_per_sqb_log2);
1033                 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
1034         }
1035 }
1036
1037 static int
1038 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
1039                               const struct rte_eth_dev *eth_dev,
1040                               int32_t tx_queue_id)
1041 {
1042         int rc;
1043
1044         RTE_SET_USED(id);
1045         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
1046         if (rc < 0)
1047                 return rc;
1048         cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);
1049         rc = cn9k_sso_updt_tx_adptr_data(event_dev);
1050         if (rc < 0)
1051                 return rc;
1052         cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1053
1054         return 0;
1055 }
1056
1057 static int
1058 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
1059                               const struct rte_eth_dev *eth_dev,
1060                               int32_t tx_queue_id)
1061 {
1062         int rc;
1063
1064         RTE_SET_USED(id);
1065         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
1066         if (rc < 0)
1067                 return rc;
1068         cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, false);
1069         return cn9k_sso_updt_tx_adptr_data(event_dev);
1070 }
1071
1072 static struct rte_eventdev_ops cn9k_sso_dev_ops = {
1073         .dev_infos_get = cn9k_sso_info_get,
1074         .dev_configure = cn9k_sso_dev_configure,
1075         .queue_def_conf = cnxk_sso_queue_def_conf,
1076         .queue_setup = cnxk_sso_queue_setup,
1077         .queue_release = cnxk_sso_queue_release,
1078         .port_def_conf = cnxk_sso_port_def_conf,
1079         .port_setup = cn9k_sso_port_setup,
1080         .port_release = cn9k_sso_port_release,
1081         .port_link = cn9k_sso_port_link,
1082         .port_unlink = cn9k_sso_port_unlink,
1083         .timeout_ticks = cnxk_sso_timeout_ticks,
1084
1085         .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1086         .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1087         .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1088         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1089         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1090
1091         .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1092         .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1093         .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1094
1095         .timer_adapter_caps_get = cnxk_tim_caps_get,
1096
1097         .dump = cnxk_sso_dump,
1098         .dev_start = cn9k_sso_start,
1099         .dev_stop = cn9k_sso_stop,
1100         .dev_close = cn9k_sso_close,
1101         .dev_selftest = cn9k_sso_selftest,
1102 };
1103
1104 static int
1105 cn9k_sso_init(struct rte_eventdev *event_dev)
1106 {
1107         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1108         int rc;
1109
1110         if (RTE_CACHE_LINE_SIZE != 128) {
1111                 plt_err("Driver not compiled for CN9K");
1112                 return -EFAULT;
1113         }
1114
1115         rc = roc_plt_init();
1116         if (rc < 0) {
1117                 plt_err("Failed to initialize platform model");
1118                 return rc;
1119         }
1120
1121         event_dev->dev_ops = &cn9k_sso_dev_ops;
1122         /* For secondary processes, the primary has done all the work */
1123         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1124                 cn9k_sso_fp_fns_set(event_dev);
1125                 return 0;
1126         }
1127
1128         rc = cnxk_sso_init(event_dev);
1129         if (rc < 0)
1130                 return rc;
1131
1132         cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1133         if (!dev->max_event_ports || !dev->max_event_queues) {
1134                 plt_err("Not enough eventdev resource queues=%d ports=%d",
1135                         dev->max_event_queues, dev->max_event_ports);
1136                 cnxk_sso_fini(event_dev);
1137                 return -ENODEV;
1138         }
1139
1140         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1141                     event_dev->data->name, dev->max_event_queues,
1142                     dev->max_event_ports);
1143
1144         return 0;
1145 }
1146
1147 static int
1148 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1149 {
1150         return rte_event_pmd_pci_probe(
1151                 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1152 }
1153
1154 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1155         {
1156                 .vendor_id = 0,
1157         },
1158 };
1159
1160 static struct rte_pci_driver cn9k_pci_sso = {
1161         .id_table = cn9k_pci_sso_map,
1162         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1163         .probe = cn9k_sso_probe,
1164         .remove = cnxk_sso_remove,
1165 };
1166
1167 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1168 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1169 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1170 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1171                               CNXK_SSO_GGRP_QOS "=<string>"
1172                               CNXK_SSO_FORCE_BP "=1"
1173                               CN9K_SSO_SINGLE_WS "=1"
1174                               CNXK_TIM_DISABLE_NPA "=1"
1175                               CNXK_TIM_CHNK_SLOTS "=<int>"
1176                               CNXK_TIM_RINGS_LMT "=<int>"
1177                               CNXK_TIM_STATS_ENA "=1");