1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn9k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN9K_DUAL_WS_NB_WS 2
10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
12 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
13 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
15 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
16 enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
19 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
21 struct cnxk_sso_evdev *dev = arg;
22 struct cn9k_sso_hws_dual *dws;
23 struct cn9k_sso_hws *ws;
28 rc = roc_sso_hws_link(&dev->sso,
29 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
31 rc |= roc_sso_hws_link(&dev->sso,
32 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
36 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
43 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
45 struct cnxk_sso_evdev *dev = arg;
46 struct cn9k_sso_hws_dual *dws;
47 struct cn9k_sso_hws *ws;
52 rc = roc_sso_hws_unlink(&dev->sso,
53 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
55 rc |= roc_sso_hws_unlink(&dev->sso,
56 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
60 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
67 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
69 struct cnxk_sso_evdev *dev = arg;
70 struct cn9k_sso_hws_dual *dws;
71 struct cn9k_sso_hws *ws;
74 /* Set get_work tmo for HWS */
75 val = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0;
78 dws->grp_base = grp_base;
79 dws->fc_mem = (uint64_t *)dev->fc_iova;
80 dws->xaq_lmt = dev->xaq_lmt;
82 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
83 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
86 ws->grp_base = grp_base;
87 ws->fc_mem = (uint64_t *)dev->fc_iova;
88 ws->xaq_lmt = dev->xaq_lmt;
90 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
95 cn9k_sso_hws_release(void *arg, void *hws)
97 struct cnxk_sso_evdev *dev = arg;
98 struct cn9k_sso_hws_dual *dws;
99 struct cn9k_sso_hws *ws;
104 for (i = 0; i < dev->nb_event_queues; i++) {
105 roc_sso_hws_unlink(&dev->sso,
106 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
108 roc_sso_hws_unlink(&dev->sso,
109 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
112 memset(dws, 0, sizeof(*dws));
115 for (i = 0; i < dev->nb_event_queues; i++)
116 roc_sso_hws_unlink(&dev->sso, ws->hws_id,
118 memset(ws, 0, sizeof(*ws));
123 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
124 cnxk_handle_event_t fn, void *arg)
126 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
127 struct cn9k_sso_hws_dual *dws;
128 struct cn9k_sso_hws *ws;
129 uint64_t cq_ds_cnt = 1;
136 plt_write64(0, base + SSO_LF_GGRP_QCTL);
138 req = queue_id; /* GGRP ID */
139 req |= BIT_ULL(18); /* Grouped */
140 req |= BIT_ULL(16); /* WAIT */
142 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
143 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
144 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
145 cq_ds_cnt &= 0x3FFF3FFF0000;
149 ws_base = dws->base[0];
155 while (aq_cnt || cq_ds_cnt || ds_cnt) {
156 plt_write64(req, ws_base + SSOW_LF_GWS_OP_GET_WORK0);
157 cn9k_sso_hws_get_work_empty(ws_base, &ev);
158 if (fn != NULL && ev.u64 != 0)
160 if (ev.sched_type != SSO_TT_EMPTY)
161 cnxk_sso_hws_swtag_flush(
162 ws_base + SSOW_LF_GWS_TAG,
163 ws_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
165 val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
166 } while (val & BIT_ULL(56));
167 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
168 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
169 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
170 /* Extract cq and ds count */
171 cq_ds_cnt &= 0x3FFF3FFF0000;
174 plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
178 cn9k_sso_hws_reset(void *arg, void *hws)
180 struct cnxk_sso_evdev *dev = arg;
181 struct cn9k_sso_hws_dual *dws;
182 struct cn9k_sso_hws *ws;
191 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
192 base = dev->dual_ws ? dws->base[i] : ws->base;
193 /* Wait till getwork/swtp/waitw/desched completes. */
195 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
196 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
199 tag = plt_read64(base + SSOW_LF_GWS_TAG);
200 pend_tt = (tag >> 32) & 0x3;
201 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
202 if (pend_tt == SSO_TT_ATOMIC ||
203 pend_tt == SSO_TT_ORDERED)
204 cnxk_sso_hws_swtag_untag(
205 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
206 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
209 /* Wait for desched to complete. */
211 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
212 } while (pend_state & BIT_ULL(58));
217 cn9k_sso_set_rsrc(void *arg)
219 struct cnxk_sso_evdev *dev = arg;
222 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
224 dev->max_event_ports = dev->sso.max_hws;
225 dev->max_event_queues =
226 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
227 RTE_EVENT_MAX_QUEUES_PER_DEV :
232 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
234 struct cnxk_sso_evdev *dev = arg;
237 hws = hws * CN9K_DUAL_WS_NB_WS;
239 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
243 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
245 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
248 if (dev->tx_adptr_data == NULL)
251 for (i = 0; i < dev->nb_event_ports; i++) {
253 struct cn9k_sso_hws_dual *dws =
254 event_dev->data->ports[i];
257 ws_cookie = cnxk_sso_hws_get_cookie(dws);
258 ws_cookie = rte_realloc_socket(
260 sizeof(struct cnxk_sso_hws_cookie) +
261 sizeof(struct cn9k_sso_hws_dual) +
263 (dev->max_port_id + 1) *
264 RTE_MAX_QUEUES_PER_PORT),
265 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
266 if (ws_cookie == NULL)
268 dws = RTE_PTR_ADD(ws_cookie,
269 sizeof(struct cnxk_sso_hws_cookie));
270 memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
271 sizeof(uint64_t) * (dev->max_port_id + 1) *
272 RTE_MAX_QUEUES_PER_PORT);
273 event_dev->data->ports[i] = dws;
275 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
278 ws_cookie = cnxk_sso_hws_get_cookie(ws);
279 ws_cookie = rte_realloc_socket(
281 sizeof(struct cnxk_sso_hws_cookie) +
282 sizeof(struct cn9k_sso_hws_dual) +
284 (dev->max_port_id + 1) *
285 RTE_MAX_QUEUES_PER_PORT),
286 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
287 if (ws_cookie == NULL)
289 ws = RTE_PTR_ADD(ws_cookie,
290 sizeof(struct cnxk_sso_hws_cookie));
291 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
292 sizeof(uint64_t) * (dev->max_port_id + 1) *
293 RTE_MAX_QUEUES_PER_PORT);
294 event_dev->data->ports[i] = ws;
303 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
305 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
306 /* Single WS modes */
307 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
308 #define R(name, flags)[flags] = cn9k_sso_hws_deq_##name,
309 NIX_RX_FASTPATH_MODES
313 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
314 #define R(name, flags)[flags] = cn9k_sso_hws_deq_burst_##name,
315 NIX_RX_FASTPATH_MODES
319 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
320 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_##name,
321 NIX_RX_FASTPATH_MODES
325 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
326 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_burst_##name,
327 NIX_RX_FASTPATH_MODES
331 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
332 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_##name,
333 NIX_RX_FASTPATH_MODES
337 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
338 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_burst_##name,
339 NIX_RX_FASTPATH_MODES
343 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
344 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_##name,
345 NIX_RX_FASTPATH_MODES
349 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
350 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_burst_##name,
351 NIX_RX_FASTPATH_MODES
355 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
356 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_##name,
357 NIX_RX_FASTPATH_MODES
361 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
362 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_burst_##name,
363 NIX_RX_FASTPATH_MODES
367 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
368 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_##name,
369 NIX_RX_FASTPATH_MODES
373 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
374 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
375 NIX_RX_FASTPATH_MODES
379 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
380 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_##name,
381 NIX_RX_FASTPATH_MODES
385 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
386 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_burst_##name,
387 NIX_RX_FASTPATH_MODES
391 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
392 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_##name,
393 NIX_RX_FASTPATH_MODES
397 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
398 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_burst_##name,
399 NIX_RX_FASTPATH_MODES
404 const event_dequeue_t sso_hws_dual_deq[NIX_RX_OFFLOAD_MAX] = {
405 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_##name,
406 NIX_RX_FASTPATH_MODES
410 const event_dequeue_burst_t sso_hws_dual_deq_burst[NIX_RX_OFFLOAD_MAX] = {
411 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_burst_##name,
412 NIX_RX_FASTPATH_MODES
416 const event_dequeue_t sso_hws_dual_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
417 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_##name,
418 NIX_RX_FASTPATH_MODES
422 const event_dequeue_burst_t sso_hws_dual_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
423 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
424 NIX_RX_FASTPATH_MODES
428 const event_dequeue_t sso_hws_dual_deq_ca[NIX_RX_OFFLOAD_MAX] = {
429 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_##name,
430 NIX_RX_FASTPATH_MODES
434 const event_dequeue_burst_t sso_hws_dual_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
435 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_burst_##name,
436 NIX_RX_FASTPATH_MODES
440 const event_dequeue_t sso_hws_dual_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
441 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_##name,
442 NIX_RX_FASTPATH_MODES
446 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
447 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_burst_##name,
448 NIX_RX_FASTPATH_MODES
452 const event_dequeue_t sso_hws_dual_deq_seg[NIX_RX_OFFLOAD_MAX] = {
453 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_##name,
454 NIX_RX_FASTPATH_MODES
458 const event_dequeue_burst_t sso_hws_dual_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
459 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_burst_##name,
460 NIX_RX_FASTPATH_MODES
464 const event_dequeue_t sso_hws_dual_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
465 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
466 NIX_RX_FASTPATH_MODES
470 const event_dequeue_burst_t sso_hws_dual_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
471 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
472 NIX_RX_FASTPATH_MODES
476 const event_dequeue_t sso_hws_dual_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
477 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_##name,
478 NIX_RX_FASTPATH_MODES
482 const event_dequeue_burst_t sso_hws_dual_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
483 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
484 NIX_RX_FASTPATH_MODES
488 const event_dequeue_t sso_hws_dual_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
489 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_##name,
490 NIX_RX_FASTPATH_MODES
494 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
495 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name,
496 NIX_RX_FASTPATH_MODES
501 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
502 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_##name,
503 NIX_TX_FASTPATH_MODES
507 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
508 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
509 NIX_TX_FASTPATH_MODES
513 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
514 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
515 NIX_TX_FASTPATH_MODES
519 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
520 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
521 NIX_TX_FASTPATH_MODES
525 event_dev->enqueue = cn9k_sso_hws_enq;
526 event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
527 event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
528 event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
529 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
530 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);
531 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
532 sso_hws_deq_seg_burst);
533 if (dev->is_timeout_deq) {
534 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
535 sso_hws_deq_tmo_seg);
536 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
537 sso_hws_deq_tmo_seg_burst);
539 if (dev->is_ca_internal_port) {
540 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
542 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
543 sso_hws_deq_ca_seg_burst);
546 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
547 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
548 sso_hws_deq_tmo_ca_seg);
549 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
550 sso_hws_deq_tmo_ca_seg_burst);
553 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
554 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
556 if (dev->is_timeout_deq) {
557 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
559 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
560 sso_hws_deq_tmo_burst);
562 if (dev->is_ca_internal_port) {
563 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
565 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
566 sso_hws_deq_ca_burst);
569 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
570 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
572 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
573 sso_hws_deq_tmo_ca_burst);
576 event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
578 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
579 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
580 sso_hws_tx_adptr_enq_seg);
582 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
583 sso_hws_tx_adptr_enq);
586 event_dev->enqueue = cn9k_sso_hws_dual_enq;
587 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
588 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
589 event_dev->enqueue_forward_burst =
590 cn9k_sso_hws_dual_enq_fwd_burst;
591 event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
593 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
594 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
595 sso_hws_dual_deq_seg);
596 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
597 sso_hws_dual_deq_seg_burst);
598 if (dev->is_timeout_deq) {
599 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
600 sso_hws_dual_deq_tmo_seg);
601 CN9K_SET_EVDEV_DEQ_OP(
602 dev, event_dev->dequeue_burst,
603 sso_hws_dual_deq_tmo_seg_burst);
605 if (dev->is_ca_internal_port) {
606 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
607 sso_hws_dual_deq_ca_seg);
608 CN9K_SET_EVDEV_DEQ_OP(
609 dev, event_dev->dequeue_burst,
610 sso_hws_dual_deq_ca_seg_burst);
612 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
613 CN9K_SET_EVDEV_DEQ_OP(
614 dev, event_dev->dequeue,
615 sso_hws_dual_deq_tmo_ca_seg);
616 CN9K_SET_EVDEV_DEQ_OP(
617 dev, event_dev->dequeue_burst,
618 sso_hws_dual_deq_tmo_ca_seg_burst);
621 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
623 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
624 sso_hws_dual_deq_burst);
625 if (dev->is_timeout_deq) {
626 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
627 sso_hws_dual_deq_tmo);
628 CN9K_SET_EVDEV_DEQ_OP(
629 dev, event_dev->dequeue_burst,
630 sso_hws_dual_deq_tmo_burst);
632 if (dev->is_ca_internal_port) {
633 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
634 sso_hws_dual_deq_ca);
635 CN9K_SET_EVDEV_DEQ_OP(
636 dev, event_dev->dequeue_burst,
637 sso_hws_dual_deq_ca_burst);
639 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
640 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
641 sso_hws_dual_deq_tmo_ca);
642 CN9K_SET_EVDEV_DEQ_OP(
643 dev, event_dev->dequeue_burst,
644 sso_hws_dual_deq_tmo_ca_burst);
648 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
649 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
650 sso_hws_dual_tx_adptr_enq_seg);
652 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
653 sso_hws_dual_tx_adptr_enq);
656 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
661 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
663 struct cnxk_sso_evdev *dev = arg;
664 struct cn9k_sso_hws_dual *dws;
665 struct cn9k_sso_hws *ws;
669 dws = rte_zmalloc("cn9k_dual_ws",
670 sizeof(struct cn9k_sso_hws_dual) +
672 RTE_CACHE_LINE_SIZE);
674 plt_err("Failed to alloc memory for port=%d", port_id);
678 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
679 dws->base[0] = roc_sso_hws_base_get(
680 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
681 dws->base[1] = roc_sso_hws_base_get(
682 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
683 dws->hws_id = port_id;
689 /* Allocate event port memory */
690 ws = rte_zmalloc("cn9k_ws",
691 sizeof(struct cn9k_sso_hws) +
693 RTE_CACHE_LINE_SIZE);
695 plt_err("Failed to alloc memory for port=%d", port_id);
699 /* First cache line is reserved for cookie */
700 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
701 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
702 ws->hws_id = port_id;
712 cn9k_sso_info_get(struct rte_eventdev *event_dev,
713 struct rte_event_dev_info *dev_info)
715 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
717 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
718 cnxk_sso_info_get(dev, dev_info);
722 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
724 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
727 rc = cnxk_sso_dev_validate(event_dev);
729 plt_err("Invalid event device configuration");
733 rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
735 plt_err("Failed to initialize SSO resources");
739 rc = cnxk_sso_xaq_allocate(dev);
743 rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
748 /* Restore any prior port-queue mapping. */
749 cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
756 roc_sso_rsrc_fini(&dev->sso);
757 dev->nb_event_ports = 0;
762 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
763 const struct rte_event_port_conf *port_conf)
766 RTE_SET_USED(port_conf);
767 return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
771 cn9k_sso_port_release(void *port)
773 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
774 struct cnxk_sso_evdev *dev;
779 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
780 if (!gws_cookie->configured)
783 cn9k_sso_hws_release(dev, port);
784 memset(gws_cookie, 0, sizeof(*gws_cookie));
786 rte_free(gws_cookie);
790 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
791 const uint8_t queues[], const uint8_t priorities[],
794 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
795 uint16_t hwgrp_ids[nb_links];
798 RTE_SET_USED(priorities);
799 for (link = 0; link < nb_links; link++)
800 hwgrp_ids[link] = queues[link];
801 nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
803 return (int)nb_links;
807 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
808 uint8_t queues[], uint16_t nb_unlinks)
810 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
811 uint16_t hwgrp_ids[nb_unlinks];
814 for (unlink = 0; unlink < nb_unlinks; unlink++)
815 hwgrp_ids[unlink] = queues[unlink];
816 nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
818 return (int)nb_unlinks;
822 cn9k_sso_start(struct rte_eventdev *event_dev)
826 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
830 rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
831 cn9k_sso_hws_flush_events);
835 cn9k_sso_fp_fns_set(event_dev);
841 cn9k_sso_stop(struct rte_eventdev *event_dev)
843 cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
847 cn9k_sso_close(struct rte_eventdev *event_dev)
849 return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
853 cn9k_sso_selftest(void)
855 return cnxk_sso_selftest(RTE_STR(event_cn9k));
859 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
860 const struct rte_eth_dev *eth_dev, uint32_t *caps)
864 RTE_SET_USED(event_dev);
865 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
867 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
869 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
870 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
871 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
877 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
880 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
883 for (i = 0; i < dev->nb_event_ports; i++) {
885 struct cn9k_sso_hws_dual *dws =
886 event_dev->data->ports[i];
887 dws->lookup_mem = lookup_mem;
888 dws->tstamp = tstmp_info;
890 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
891 ws->lookup_mem = lookup_mem;
892 ws->tstamp = tstmp_info;
898 cn9k_sso_rx_adapter_queue_add(
899 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
901 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
903 struct cn9k_eth_rxq *rxq;
908 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
912 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
917 rxq = eth_dev->data->rx_queues[0];
918 lookup_mem = rxq->lookup_mem;
919 tstmp_info = rxq->tstamp;
920 cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
921 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
927 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
928 const struct rte_eth_dev *eth_dev,
933 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
937 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
941 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
942 const struct rte_eth_dev *eth_dev, uint32_t *caps)
947 ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
951 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
957 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id,
960 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
961 struct cn9k_eth_txq *txq;
962 struct roc_nix_sq *sq;
965 if (tx_queue_id < 0) {
966 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
967 cn9k_sso_txq_fc_update(eth_dev, i, ena);
971 sq = &cnxk_eth_dev->sqs[tx_queue_id];
972 txq = eth_dev->data->tx_queues[tx_queue_id];
974 ena ? RTE_MIN(CNXK_SSO_SQB_LIMIT, sq->aura_sqb_bufs) :
976 txq->nb_sqb_bufs_adj =
978 RTE_ALIGN_MUL_CEIL(sq_limit,
979 (1ULL << txq->sqes_per_sqb_log2)) /
980 (1ULL << txq->sqes_per_sqb_log2);
981 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
986 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
987 const struct rte_eth_dev *eth_dev,
993 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
996 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);
997 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
1000 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1006 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
1007 const struct rte_eth_dev *eth_dev,
1008 int32_t tx_queue_id)
1013 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
1016 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, false);
1017 return cn9k_sso_updt_tx_adptr_data(event_dev);
1021 cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
1022 const struct rte_cryptodev *cdev, uint32_t *caps)
1024 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1025 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1027 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
1028 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
1034 cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
1035 const struct rte_cryptodev *cdev,
1036 int32_t queue_pair_id, const struct rte_event *event)
1038 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1040 RTE_SET_USED(event);
1042 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1043 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1045 dev->is_ca_internal_port = 1;
1046 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1048 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
1052 cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
1053 const struct rte_cryptodev *cdev,
1054 int32_t queue_pair_id)
1056 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1057 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1059 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
1062 static struct eventdev_ops cn9k_sso_dev_ops = {
1063 .dev_infos_get = cn9k_sso_info_get,
1064 .dev_configure = cn9k_sso_dev_configure,
1065 .queue_def_conf = cnxk_sso_queue_def_conf,
1066 .queue_setup = cnxk_sso_queue_setup,
1067 .queue_release = cnxk_sso_queue_release,
1068 .port_def_conf = cnxk_sso_port_def_conf,
1069 .port_setup = cn9k_sso_port_setup,
1070 .port_release = cn9k_sso_port_release,
1071 .port_link = cn9k_sso_port_link,
1072 .port_unlink = cn9k_sso_port_unlink,
1073 .timeout_ticks = cnxk_sso_timeout_ticks,
1075 .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1076 .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1077 .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1078 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1079 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1081 .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1082 .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1083 .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1085 .timer_adapter_caps_get = cnxk_tim_caps_get,
1087 .crypto_adapter_caps_get = cn9k_crypto_adapter_caps_get,
1088 .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add,
1089 .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del,
1091 .dump = cnxk_sso_dump,
1092 .dev_start = cn9k_sso_start,
1093 .dev_stop = cn9k_sso_stop,
1094 .dev_close = cn9k_sso_close,
1095 .dev_selftest = cn9k_sso_selftest,
1099 cn9k_sso_init(struct rte_eventdev *event_dev)
1101 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1104 if (RTE_CACHE_LINE_SIZE != 128) {
1105 plt_err("Driver not compiled for CN9K");
1109 rc = roc_plt_init();
1111 plt_err("Failed to initialize platform model");
1115 event_dev->dev_ops = &cn9k_sso_dev_ops;
1116 /* For secondary processes, the primary has done all the work */
1117 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118 cn9k_sso_fp_fns_set(event_dev);
1122 rc = cnxk_sso_init(event_dev);
1126 cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1127 if (!dev->max_event_ports || !dev->max_event_queues) {
1128 plt_err("Not enough eventdev resource queues=%d ports=%d",
1129 dev->max_event_queues, dev->max_event_ports);
1130 cnxk_sso_fini(event_dev);
1134 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1135 event_dev->data->name, dev->max_event_queues,
1136 dev->max_event_ports);
1142 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1144 return rte_event_pmd_pci_probe(
1145 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1148 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1149 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1150 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1151 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1152 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1153 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1154 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1155 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1156 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1157 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1158 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1164 static struct rte_pci_driver cn9k_pci_sso = {
1165 .id_table = cn9k_pci_sso_map,
1166 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1167 .probe = cn9k_sso_probe,
1168 .remove = cnxk_sso_remove,
1171 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1172 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1173 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1174 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1175 CNXK_SSO_GGRP_QOS "=<string>"
1176 CNXK_SSO_FORCE_BP "=1"
1177 CN9K_SSO_SINGLE_WS "=1"
1178 CNXK_TIM_DISABLE_NPA "=1"
1179 CNXK_TIM_CHNK_SLOTS "=<int>"
1180 CNXK_TIM_RINGS_LMT "=<int>"
1181 CNXK_TIM_STATS_ENA "=1");