1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CN9K_WORKER_H__
6 #define __CN9K_WORKER_H__
8 #include <rte_eventdev.h>
11 #include "cnxk_ethdev.h"
12 #include "cnxk_eventdev.h"
13 #include "cnxk_worker.h"
14 #include "cn9k_cryptodev_ops.h"
16 #include "cn9k_ethdev.h"
22 static __rte_always_inline uint8_t
23 cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
25 const uint32_t tag = (uint32_t)ev->event;
26 const uint8_t new_tt = ev->sched_type;
27 const uint64_t event_ptr = ev->u64;
28 const uint16_t grp = ev->queue_id;
30 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
31 if (ws->xaq_lmt <= *ws->fc_mem)
34 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
35 ws->grp_base + (grp << 12));
39 static __rte_always_inline void
40 cn9k_sso_hws_fwd_swtag(uint64_t base, const struct rte_event *ev)
42 const uint32_t tag = (uint32_t)ev->event;
43 const uint8_t new_tt = ev->sched_type;
44 const uint8_t cur_tt =
45 CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG));
48 * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
50 * SSO_TT_ORDERED norm norm untag
51 * SSO_TT_ATOMIC norm norm untag
52 * SSO_TT_UNTAGGED norm norm NOOP
55 if (new_tt == SSO_TT_UNTAGGED) {
56 if (cur_tt != SSO_TT_UNTAGGED)
57 cnxk_sso_hws_swtag_untag(base +
58 SSOW_LF_GWS_OP_SWTAG_UNTAG);
60 cnxk_sso_hws_swtag_norm(tag, new_tt,
61 base + SSOW_LF_GWS_OP_SWTAG_NORM);
65 static __rte_always_inline void
66 cn9k_sso_hws_fwd_group(uint64_t base, const struct rte_event *ev,
69 const uint32_t tag = (uint32_t)ev->event;
70 const uint8_t new_tt = ev->sched_type;
72 plt_write64(ev->u64, base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
73 cnxk_sso_hws_swtag_desched(tag, new_tt, grp,
74 base + SSOW_LF_GWS_OP_SWTAG_DESCHED);
77 static __rte_always_inline void
78 cn9k_sso_hws_forward_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
80 const uint8_t grp = ev->queue_id;
82 /* Group hasn't changed, Use SWTAG to forward the event */
83 if (CNXK_GRP_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_TAG)) == grp) {
84 cn9k_sso_hws_fwd_swtag(ws->base, ev);
88 * Group has been changed for group based work pipelining,
89 * Use deschedule/add_work operation to transfer the event to
92 cn9k_sso_hws_fwd_group(ws->base, ev, grp);
98 static __rte_always_inline uint8_t
99 cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws,
100 const struct rte_event *ev)
102 const uint32_t tag = (uint32_t)ev->event;
103 const uint8_t new_tt = ev->sched_type;
104 const uint64_t event_ptr = ev->u64;
105 const uint16_t grp = ev->queue_id;
107 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
108 if (dws->xaq_lmt <= *dws->fc_mem)
111 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
112 dws->grp_base + (grp << 12));
116 static __rte_always_inline void
117 cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws, uint64_t base,
118 const struct rte_event *ev)
120 const uint8_t grp = ev->queue_id;
122 /* Group hasn't changed, Use SWTAG to forward the event */
123 if (CNXK_GRP_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) == grp) {
124 cn9k_sso_hws_fwd_swtag(base, ev);
128 * Group has been changed for group based work pipelining,
129 * Use deschedule/add_work operation to transfer the event to
132 cn9k_sso_hws_fwd_group(base, ev, grp);
136 static __rte_always_inline void
137 cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
138 const uint32_t tag, const uint32_t flags,
139 const void *const lookup_mem)
141 const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
142 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
144 cn9k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
145 (struct rte_mbuf *)mbuf, lookup_mem,
146 mbuf_init | ((uint64_t)port_id) << 48, flags);
149 static __rte_always_inline uint16_t
150 cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,
151 struct rte_event *ev, const uint32_t flags,
152 struct cn9k_sso_hws_dual *dws)
155 __uint128_t get_work;
161 if (flags & NIX_RX_OFFLOAD_PTYPE_F)
162 rte_prefetch_non_temporal(dws->lookup_mem);
163 #ifdef RTE_ARCH_ARM64
164 asm volatile(PLT_CPU_FEATURE_PREAMBLE
166 " ldr %[tag], [%[tag_loc]] \n"
167 " ldr %[wqp], [%[wqp_loc]] \n"
168 " tbnz %[tag], 63, rty%= \n"
169 "done%=: str %[gw], [%[pong]] \n"
171 " sub %[mbuf], %[wqp], #0x80 \n"
172 " prfm pldl1keep, [%[mbuf]] \n"
173 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
175 : [tag_loc] "r"(base + SSOW_LF_GWS_TAG),
176 [wqp_loc] "r"(base + SSOW_LF_GWS_WQP), [gw] "r"(dws->gw_wdata),
177 [pong] "r"(pair_base + SSOW_LF_GWS_OP_GET_WORK0));
179 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
180 while ((BIT_ULL(63)) & gw.u64[0])
181 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
182 gw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP);
183 plt_write64(dws->gw_wdata, pair_base + SSOW_LF_GWS_OP_GET_WORK0);
184 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
187 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
188 (gw.u64[0] & (0x3FFull << 36)) << 4 |
189 (gw.u64[0] & 0xffffffff);
191 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
192 if ((flags & CPT_RX_WQE_F) &&
193 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
194 RTE_EVENT_TYPE_CRYPTODEV)) {
195 gw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);
196 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
197 RTE_EVENT_TYPE_ETHDEV) {
198 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
200 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
201 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
202 gw.u64[0] & 0xFFFFF, flags,
204 /* Extracting tstamp, if PTP enabled*/
205 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
207 CNXK_SSO_WQE_SG_PTR);
208 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
210 flags & NIX_RX_OFFLOAD_TSTAMP_F,
211 flags & NIX_RX_MULTI_SEG_F,
212 (uint64_t *)tstamp_ptr);
217 ev->event = gw.u64[0];
223 static __rte_always_inline uint16_t
224 cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,
225 const uint32_t flags, const void *const lookup_mem)
228 __uint128_t get_work;
234 plt_write64(ws->gw_wdata, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
236 if (flags & NIX_RX_OFFLOAD_PTYPE_F)
237 rte_prefetch_non_temporal(lookup_mem);
238 #ifdef RTE_ARCH_ARM64
239 asm volatile(PLT_CPU_FEATURE_PREAMBLE
240 " ldr %[tag], [%[tag_loc]] \n"
241 " ldr %[wqp], [%[wqp_loc]] \n"
242 " tbz %[tag], 63, done%= \n"
245 " ldr %[tag], [%[tag_loc]] \n"
246 " ldr %[wqp], [%[wqp_loc]] \n"
247 " tbnz %[tag], 63, rty%= \n"
249 " sub %[mbuf], %[wqp], #0x80 \n"
250 " prfm pldl1keep, [%[mbuf]] \n"
251 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
253 : [tag_loc] "r"(ws->base + SSOW_LF_GWS_TAG),
254 [wqp_loc] "r"(ws->base + SSOW_LF_GWS_WQP));
256 gw.u64[0] = plt_read64(ws->base + SSOW_LF_GWS_TAG);
257 while ((BIT_ULL(63)) & gw.u64[0])
258 gw.u64[0] = plt_read64(ws->base + SSOW_LF_GWS_TAG);
260 gw.u64[1] = plt_read64(ws->base + SSOW_LF_GWS_WQP);
261 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
264 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
265 (gw.u64[0] & (0x3FFull << 36)) << 4 |
266 (gw.u64[0] & 0xffffffff);
268 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
269 if ((flags & CPT_RX_WQE_F) &&
270 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
271 RTE_EVENT_TYPE_CRYPTODEV)) {
272 gw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);
273 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
274 RTE_EVENT_TYPE_ETHDEV) {
275 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
277 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
278 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
279 gw.u64[0] & 0xFFFFF, flags,
281 /* Extracting tstamp, if PTP enabled*/
282 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
284 CNXK_SSO_WQE_SG_PTR);
285 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
287 flags & NIX_RX_OFFLOAD_TSTAMP_F,
288 flags & NIX_RX_MULTI_SEG_F,
289 (uint64_t *)tstamp_ptr);
294 ev->event = gw.u64[0];
300 /* Used in cleaning up workslot. */
301 static __rte_always_inline uint16_t
302 cn9k_sso_hws_get_work_empty(uint64_t base, struct rte_event *ev)
305 __uint128_t get_work;
310 #ifdef RTE_ARCH_ARM64
311 asm volatile(PLT_CPU_FEATURE_PREAMBLE
312 " ldr %[tag], [%[tag_loc]] \n"
313 " ldr %[wqp], [%[wqp_loc]] \n"
314 " tbz %[tag], 63, done%= \n"
317 " ldr %[tag], [%[tag_loc]] \n"
318 " ldr %[wqp], [%[wqp_loc]] \n"
319 " tbnz %[tag], 63, rty%= \n"
321 " sub %[mbuf], %[wqp], #0x80 \n"
322 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
324 : [tag_loc] "r"(base + SSOW_LF_GWS_TAG),
325 [wqp_loc] "r"(base + SSOW_LF_GWS_WQP));
327 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
328 while ((BIT_ULL(63)) & gw.u64[0])
329 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
331 gw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP);
332 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
335 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
336 (gw.u64[0] & (0x3FFull << 36)) << 4 |
337 (gw.u64[0] & 0xffffffff);
339 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
340 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
341 RTE_EVENT_TYPE_ETHDEV) {
342 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
344 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
345 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
346 gw.u64[0] & 0xFFFFF, 0, NULL);
351 ev->event = gw.u64[0];
357 /* CN9K Fastpath functions. */
358 uint16_t __rte_hot cn9k_sso_hws_enq(void *port, const struct rte_event *ev);
359 uint16_t __rte_hot cn9k_sso_hws_enq_burst(void *port,
360 const struct rte_event ev[],
362 uint16_t __rte_hot cn9k_sso_hws_enq_new_burst(void *port,
363 const struct rte_event ev[],
365 uint16_t __rte_hot cn9k_sso_hws_enq_fwd_burst(void *port,
366 const struct rte_event ev[],
369 uint16_t __rte_hot cn9k_sso_hws_dual_enq(void *port,
370 const struct rte_event *ev);
371 uint16_t __rte_hot cn9k_sso_hws_dual_enq_burst(void *port,
372 const struct rte_event ev[],
374 uint16_t __rte_hot cn9k_sso_hws_dual_enq_new_burst(void *port,
375 const struct rte_event ev[],
377 uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,
378 const struct rte_event ev[],
380 uint16_t __rte_hot cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[],
382 uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],
385 #define R(name, flags) \
386 uint16_t __rte_hot cn9k_sso_hws_deq_##name( \
387 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
388 uint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \
389 void *port, struct rte_event ev[], uint16_t nb_events, \
390 uint64_t timeout_ticks); \
391 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_##name( \
392 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
393 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_burst_##name( \
394 void *port, struct rte_event ev[], uint16_t nb_events, \
395 uint64_t timeout_ticks); \
396 uint16_t __rte_hot cn9k_sso_hws_deq_ca_##name( \
397 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
398 uint16_t __rte_hot cn9k_sso_hws_deq_ca_burst_##name( \
399 void *port, struct rte_event ev[], uint16_t nb_events, \
400 uint64_t timeout_ticks); \
401 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_##name( \
402 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
403 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_burst_##name( \
404 void *port, struct rte_event ev[], uint16_t nb_events, \
405 uint64_t timeout_ticks); \
406 uint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \
407 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
408 uint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \
409 void *port, struct rte_event ev[], uint16_t nb_events, \
410 uint64_t timeout_ticks); \
411 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_##name( \
412 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
413 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_burst_##name( \
414 void *port, struct rte_event ev[], uint16_t nb_events, \
415 uint64_t timeout_ticks); \
416 uint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_##name( \
417 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
418 uint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_burst_##name( \
419 void *port, struct rte_event ev[], uint16_t nb_events, \
420 uint64_t timeout_ticks); \
421 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_seg_##name( \
422 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
423 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_seg_burst_##name( \
424 void *port, struct rte_event ev[], uint16_t nb_events, \
425 uint64_t timeout_ticks);
427 NIX_RX_FASTPATH_MODES
430 #define SSO_DEQ(fn, flags) \
431 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
432 uint64_t timeout_ticks) \
434 struct cn9k_sso_hws *ws = port; \
435 RTE_SET_USED(timeout_ticks); \
436 if (ws->swtag_req) { \
438 cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_TAG); \
441 return cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
444 #define SSO_DEQ_SEG(fn, flags) SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
445 #define SSO_DEQ_CA(fn, flags) SSO_DEQ(fn, flags | CPT_RX_WQE_F)
446 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
448 #define SSO_DEQ_TMO(fn, flags) \
449 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
450 uint64_t timeout_ticks) \
452 struct cn9k_sso_hws *ws = port; \
455 if (ws->swtag_req) { \
457 cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_TAG); \
460 ret = cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
461 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \
462 ret = cn9k_sso_hws_get_work(ws, ev, flags, \
467 #define SSO_DEQ_TMO_SEG(fn, flags) SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
468 #define SSO_DEQ_TMO_CA(fn, flags) SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
469 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
471 #define R(name, flags) \
472 uint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \
473 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
474 uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \
475 void *port, struct rte_event ev[], uint16_t nb_events, \
476 uint64_t timeout_ticks); \
477 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_##name( \
478 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
479 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_burst_##name( \
480 void *port, struct rte_event ev[], uint16_t nb_events, \
481 uint64_t timeout_ticks); \
482 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_##name( \
483 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
484 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_burst_##name( \
485 void *port, struct rte_event ev[], uint16_t nb_events, \
486 uint64_t timeout_ticks); \
487 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_##name( \
488 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
489 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_burst_##name( \
490 void *port, struct rte_event ev[], uint16_t nb_events, \
491 uint64_t timeout_ticks); \
492 uint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \
493 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
494 uint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \
495 void *port, struct rte_event ev[], uint16_t nb_events, \
496 uint64_t timeout_ticks); \
497 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_##name( \
498 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
499 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_burst_##name( \
500 void *port, struct rte_event ev[], uint16_t nb_events, \
501 uint64_t timeout_ticks); \
502 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_##name( \
503 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
504 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_burst_##name( \
505 void *port, struct rte_event ev[], uint16_t nb_events, \
506 uint64_t timeout_ticks); \
507 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_seg_##name( \
508 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
509 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name( \
510 void *port, struct rte_event ev[], uint16_t nb_events, \
511 uint64_t timeout_ticks);
513 NIX_RX_FASTPATH_MODES
516 #define SSO_DUAL_DEQ(fn, flags) \
517 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
518 uint64_t timeout_ticks) \
520 struct cn9k_sso_hws_dual *dws = port; \
522 RTE_SET_USED(timeout_ticks); \
523 if (dws->swtag_req) { \
524 dws->swtag_req = 0; \
525 cnxk_sso_hws_swtag_wait(dws->base[!dws->vws] + \
529 gw = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \
530 dws->base[!dws->vws], ev, \
532 dws->vws = !dws->vws; \
536 #define SSO_DUAL_DEQ_SEG(fn, flags) SSO_DUAL_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
537 #define SSO_DUAL_DEQ_CA(fn, flags) SSO_DUAL_DEQ(fn, flags | CPT_RX_WQE_F)
538 #define SSO_DUAL_DEQ_CA_SEG(fn, flags) \
539 SSO_DUAL_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
541 #define SSO_DUAL_DEQ_TMO(fn, flags) \
542 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
543 uint64_t timeout_ticks) \
545 struct cn9k_sso_hws_dual *dws = port; \
548 if (dws->swtag_req) { \
549 dws->swtag_req = 0; \
550 cnxk_sso_hws_swtag_wait(dws->base[!dws->vws] + \
554 ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \
555 dws->base[!dws->vws], ev, \
557 dws->vws = !dws->vws; \
558 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \
559 ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \
560 dws->base[!dws->vws], \
562 dws->vws = !dws->vws; \
567 #define SSO_DUAL_DEQ_TMO_SEG(fn, flags) \
568 SSO_DUAL_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
569 #define SSO_DUAL_DEQ_TMO_CA(fn, flags) \
570 SSO_DUAL_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
571 #define SSO_DUAL_DEQ_TMO_CA_SEG(fn, flags) \
572 SSO_DUAL_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
574 #define SSO_CMN_DEQ_BURST(fnb, fn, flags) \
575 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
576 uint16_t nb_events, uint64_t timeout_ticks) \
578 RTE_SET_USED(nb_events); \
579 return fn(port, ev, timeout_ticks); \
582 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags) \
583 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
584 uint16_t nb_events, uint64_t timeout_ticks) \
586 RTE_SET_USED(nb_events); \
587 return fn(port, ev, timeout_ticks); \
590 static __rte_always_inline void
591 cn9k_sso_txq_fc_wait(const struct cn9k_eth_txq *txq)
593 while (!((txq->nb_sqb_bufs_adj -
594 __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
595 << (txq)->sqes_per_sqb_log2))
599 static __rte_always_inline struct cn9k_eth_txq *
600 cn9k_sso_hws_xtract_meta(struct rte_mbuf *m, uint64_t *txq_data)
602 return (struct cn9k_eth_txq
603 *)(txq_data[(txq_data[m->port] >> 48) +
604 rte_event_eth_tx_adapter_txq_get(m)] &
608 #if defined(RTE_ARCH_ARM64)
610 static __rte_always_inline void
611 cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,
612 struct rte_mbuf *m, uint64_t *cmd,
615 struct cn9k_outb_priv_data *outb_priv;
616 rte_iova_t io_addr = txq->cpt_io_addr;
617 uint64_t *lmt_addr = txq->lmt_addr;
618 struct cn9k_sec_sess_priv mdata;
619 struct nix_send_hdr_s *send_hdr;
620 uint64_t sa_base = txq->sa_base;
621 uint32_t pkt_len, dlen_adj, rlen;
622 uint64x2_t cmd01, cmd23;
623 uint64_t lmt_status, sa;
624 union nix_send_sg_s *sg;
625 uintptr_t dptr, nixtx;
626 uint64_t ucode_cmd[4];
630 mdata.u64 = *rte_security_dynfield(m);
631 send_hdr = (struct nix_send_hdr_s *)cmd;
632 if (flags & NIX_TX_NEED_EXT_HDR)
633 sg = (union nix_send_sg_s *)&cmd[4];
635 sg = (union nix_send_sg_s *)&cmd[2];
637 if (flags & NIX_TX_NEED_SEND_HDR_W1)
638 l2_len = cmd[1] & 0xFF;
643 dptr = *(uint64_t *)(sg + 1);
644 pkt_len = send_hdr->w0.total;
647 rlen = pkt_len - l2_len;
648 rlen = (rlen + mdata.roundup_len) + (mdata.roundup_byte - 1);
649 rlen &= ~(uint64_t)(mdata.roundup_byte - 1);
650 rlen += mdata.partial_len;
651 dlen_adj = rlen - pkt_len + l2_len;
653 /* Update send descriptors. Security is single segment only */
654 send_hdr->w0.total = pkt_len + dlen_adj;
655 sg->seg1_size = pkt_len + dlen_adj;
657 /* Get area where NIX descriptor needs to be stored */
658 nixtx = dptr + pkt_len + dlen_adj;
660 nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1);
662 roc_lmt_mov_nv((void *)(nixtx + 16), cmd, cn9k_nix_tx_ext_subs(flags));
664 /* Load opcode and cptr already prepared at pkt metadata set */
666 pkt_len += sizeof(struct roc_onf_ipsec_outb_hdr) +
667 ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ;
668 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
670 sa = (uintptr_t)roc_nix_inl_onf_ipsec_outb_sa(sa_base, mdata.sa_idx);
671 ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | sa);
672 ucode_cmd[0] = (ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |
673 0x40UL << 48 | pkt_len);
675 /* CPT Word 0 and Word 1 */
676 cmd01 = vdupq_n_u64((nixtx + 16) | (cn9k_nix_tx_ext_subs(flags) + 1));
677 /* CPT_RES_S is 16B above NIXTX */
678 cmd01 = vsetq_lane_u8(nixtx & BIT_ULL(7), cmd01, 8);
680 /* CPT word 2 and 3 */
681 cmd23 = vdupq_n_u64(0);
682 cmd23 = vsetq_lane_u64((((uint64_t)RTE_EVENT_TYPE_CPU << 28) |
683 CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0);
684 cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1);
686 dptr += l2_len - ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ -
687 sizeof(struct roc_onf_ipsec_outb_hdr);
691 /* Update IV to zero and l2 sz */
692 *(uint16_t *)(dptr + sizeof(struct roc_onf_ipsec_outb_hdr)) =
693 rte_cpu_to_be_16(ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ);
694 iv = (uint64_t *)(dptr + 8);
698 /* Head wait if needed */
700 roc_sso_hws_head_wait(base);
703 outb_priv = roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd((void *)sa);
704 esn = outb_priv->esn;
705 outb_priv->esn = esn + 1;
707 ucode_cmd[0] |= (esn >> 32) << 16;
708 esn = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1));
710 /* Update ESN and IPID and IV */
711 *(uint64_t *)dptr = esn << 32 | esn;
714 cn9k_sso_txq_fc_wait(txq);
716 /* Write CPT instruction to lmt line */
717 vst1q_u64(lmt_addr, cmd01);
718 vst1q_u64(lmt_addr + 2, cmd23);
720 roc_lmt_mov_seg(lmt_addr + 4, ucode_cmd, 2);
722 if (roc_lmt_submit_ldeor(io_addr) == 0) {
724 vst1q_u64(lmt_addr, cmd01);
725 vst1q_u64(lmt_addr + 2, cmd23);
726 roc_lmt_mov_seg(lmt_addr + 4, ucode_cmd, 2);
728 lmt_status = roc_lmt_submit_ldeor(io_addr);
729 } while (lmt_status == 0);
735 cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,
736 struct rte_mbuf *m, uint64_t *cmd,
747 static __rte_always_inline uint16_t
748 cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,
749 uint64_t *txq_data, const uint32_t flags)
751 struct rte_mbuf *m = ev->mbuf;
752 uint16_t ref_cnt = m->refcnt;
753 struct cn9k_eth_txq *txq;
755 /* Perform header writes before barrier for TSO */
756 cn9k_nix_xmit_prepare_tso(m, flags);
757 /* Lets commit any changes in the packet here in case when
758 * fast free is set as no further changes will be made to mbuf.
759 * In case of fast free is not set, both cn9k_nix_prepare_mseg()
760 * and cn9k_nix_xmit_prepare() has a barrier after refcnt update.
762 if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) &&
763 !(flags & NIX_TX_OFFLOAD_SECURITY_F))
765 txq = cn9k_sso_hws_xtract_meta(m, txq_data);
766 cn9k_nix_tx_skeleton(txq, cmd, flags, 0);
767 cn9k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt);
769 if (flags & NIX_TX_OFFLOAD_SECURITY_F) {
770 uint64_t ol_flags = m->ol_flags;
772 if (ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
773 uintptr_t ssow_base = base;
778 cn9k_sso_hws_xmit_sec_one(txq, ssow_base, m, cmd,
783 if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
787 if (flags & NIX_TX_MULTI_SEG_F) {
788 const uint16_t segdw = cn9k_nix_prepare_mseg(m, cmd, flags);
789 cn9k_nix_xmit_prepare_tstamp(txq, cmd, m->ol_flags, segdw,
791 if (!CNXK_TT_FROM_EVENT(ev->event)) {
792 cn9k_nix_xmit_mseg_prep_lmt(cmd, txq->lmt_addr, segdw);
793 roc_sso_hws_head_wait(base);
794 cn9k_sso_txq_fc_wait(txq);
795 if (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)
796 cn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr,
797 txq->io_addr, segdw);
799 cn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr, txq->io_addr,
803 cn9k_nix_xmit_prepare_tstamp(txq, cmd, m->ol_flags, 4, flags);
804 if (!CNXK_TT_FROM_EVENT(ev->event)) {
805 cn9k_nix_xmit_prep_lmt(cmd, txq->lmt_addr, flags);
806 roc_sso_hws_head_wait(base);
807 cn9k_sso_txq_fc_wait(txq);
808 if (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)
809 cn9k_nix_xmit_one(cmd, txq->lmt_addr,
810 txq->io_addr, flags);
812 cn9k_nix_xmit_one(cmd, txq->lmt_addr, txq->io_addr,
818 if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
823 cnxk_sso_hws_swtag_flush(base + SSOW_LF_GWS_TAG,
824 base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
829 #define T(name, sz, flags) \
830 uint16_t __rte_hot cn9k_sso_hws_tx_adptr_enq_##name( \
831 void *port, struct rte_event ev[], uint16_t nb_events); \
832 uint16_t __rte_hot cn9k_sso_hws_tx_adptr_enq_seg_##name( \
833 void *port, struct rte_event ev[], uint16_t nb_events); \
834 uint16_t __rte_hot cn9k_sso_hws_dual_tx_adptr_enq_##name( \
835 void *port, struct rte_event ev[], uint16_t nb_events); \
836 uint16_t __rte_hot cn9k_sso_hws_dual_tx_adptr_enq_seg_##name( \
837 void *port, struct rte_event ev[], uint16_t nb_events);
839 NIX_TX_FASTPATH_MODES
842 #define SSO_TX(fn, sz, flags) \
843 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
844 uint16_t nb_events) \
846 struct cn9k_sso_hws *ws = port; \
848 RTE_SET_USED(nb_events); \
849 return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, \
850 (uint64_t *)ws->tx_adptr_data, \
854 #define SSO_TX_SEG(fn, sz, flags) \
855 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
856 uint16_t nb_events) \
858 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
859 struct cn9k_sso_hws *ws = port; \
860 RTE_SET_USED(nb_events); \
861 return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, \
862 (uint64_t *)ws->tx_adptr_data, \
863 (flags) | NIX_TX_MULTI_SEG_F); \
866 #define SSO_DUAL_TX(fn, sz, flags) \
867 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
868 uint16_t nb_events) \
870 struct cn9k_sso_hws_dual *ws = port; \
872 RTE_SET_USED(nb_events); \
873 return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, \
874 (uint64_t *)ws->tx_adptr_data, \
878 #define SSO_DUAL_TX_SEG(fn, sz, flags) \
879 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
880 uint16_t nb_events) \
882 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
883 struct cn9k_sso_hws_dual *ws = port; \
884 RTE_SET_USED(nb_events); \
885 return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, \
886 (uint64_t *)ws->tx_adptr_data, \
887 (flags) | NIX_TX_MULTI_SEG_F); \