1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CN9K_WORKER_H__
6 #define __CN9K_WORKER_H__
8 #include <rte_eventdev.h>
11 #include "cnxk_ethdev.h"
12 #include "cnxk_eventdev.h"
13 #include "cnxk_worker.h"
14 #include "cn9k_cryptodev_ops.h"
16 #include "cn9k_ethdev.h"
22 static __rte_always_inline uint8_t
23 cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
25 const uint32_t tag = (uint32_t)ev->event;
26 const uint8_t new_tt = ev->sched_type;
27 const uint64_t event_ptr = ev->u64;
28 const uint16_t grp = ev->queue_id;
30 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
31 if (ws->xaq_lmt <= *ws->fc_mem)
34 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
35 ws->grp_base + (grp << 12));
39 static __rte_always_inline void
40 cn9k_sso_hws_fwd_swtag(uint64_t base, const struct rte_event *ev)
42 const uint32_t tag = (uint32_t)ev->event;
43 const uint8_t new_tt = ev->sched_type;
44 const uint8_t cur_tt =
45 CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG));
48 * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
50 * SSO_TT_ORDERED norm norm untag
51 * SSO_TT_ATOMIC norm norm untag
52 * SSO_TT_UNTAGGED norm norm NOOP
55 if (new_tt == SSO_TT_UNTAGGED) {
56 if (cur_tt != SSO_TT_UNTAGGED)
57 cnxk_sso_hws_swtag_untag(base +
58 SSOW_LF_GWS_OP_SWTAG_UNTAG);
60 cnxk_sso_hws_swtag_norm(tag, new_tt,
61 base + SSOW_LF_GWS_OP_SWTAG_NORM);
65 static __rte_always_inline void
66 cn9k_sso_hws_new_event_wait(struct cn9k_sso_hws *ws, const struct rte_event *ev)
68 const uint32_t tag = (uint32_t)ev->event;
69 const uint8_t new_tt = ev->sched_type;
70 const uint64_t event_ptr = ev->u64;
71 const uint16_t grp = ev->queue_id;
73 while (ws->xaq_lmt <= __atomic_load_n(ws->fc_mem, __ATOMIC_RELAXED))
76 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
77 ws->grp_base + (grp << 12));
80 static __rte_always_inline void
81 cn9k_sso_hws_forward_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
83 const uint8_t grp = ev->queue_id;
85 /* Group hasn't changed, Use SWTAG to forward the event */
86 if (CNXK_GRP_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_TAG)) == grp) {
87 cn9k_sso_hws_fwd_swtag(ws->base, ev);
91 * Group has been changed for group based work pipelining,
92 * Use add_work operation to transfer the event to
95 rte_atomic_thread_fence(__ATOMIC_RELEASE);
96 roc_sso_hws_head_wait(ws->base);
97 cn9k_sso_hws_new_event_wait(ws, ev);
103 static __rte_always_inline uint8_t
104 cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws,
105 const struct rte_event *ev)
107 const uint32_t tag = (uint32_t)ev->event;
108 const uint8_t new_tt = ev->sched_type;
109 const uint64_t event_ptr = ev->u64;
110 const uint16_t grp = ev->queue_id;
112 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
113 if (dws->xaq_lmt <= *dws->fc_mem)
116 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
117 dws->grp_base + (grp << 12));
121 static __rte_always_inline void
122 cn9k_sso_hws_dual_new_event_wait(struct cn9k_sso_hws_dual *dws,
123 const struct rte_event *ev)
125 const uint32_t tag = (uint32_t)ev->event;
126 const uint8_t new_tt = ev->sched_type;
127 const uint64_t event_ptr = ev->u64;
128 const uint16_t grp = ev->queue_id;
130 while (dws->xaq_lmt <= __atomic_load_n(dws->fc_mem, __ATOMIC_RELAXED))
133 cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
134 dws->grp_base + (grp << 12));
137 static __rte_always_inline void
138 cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws, uint64_t base,
139 const struct rte_event *ev)
141 const uint8_t grp = ev->queue_id;
143 /* Group hasn't changed, Use SWTAG to forward the event */
144 if (CNXK_GRP_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) == grp) {
145 cn9k_sso_hws_fwd_swtag(base, ev);
149 * Group has been changed for group based work pipelining,
150 * Use add_work operation to transfer the event to
153 rte_atomic_thread_fence(__ATOMIC_RELEASE);
154 roc_sso_hws_head_wait(base);
155 cn9k_sso_hws_dual_new_event_wait(dws, ev);
159 static __rte_always_inline void
160 cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
161 const uint32_t tag, const uint32_t flags,
162 const void *const lookup_mem)
164 const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
165 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
167 cn9k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
168 (struct rte_mbuf *)mbuf, lookup_mem,
169 mbuf_init | ((uint64_t)port_id) << 48, flags);
172 static __rte_always_inline uint16_t
173 cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,
174 struct rte_event *ev, const uint32_t flags,
175 struct cn9k_sso_hws_dual *dws)
178 __uint128_t get_work;
184 if (flags & NIX_RX_OFFLOAD_PTYPE_F)
185 rte_prefetch_non_temporal(dws->lookup_mem);
186 #ifdef RTE_ARCH_ARM64
187 asm volatile(PLT_CPU_FEATURE_PREAMBLE
189 " ldr %[tag], [%[tag_loc]] \n"
190 " ldr %[wqp], [%[wqp_loc]] \n"
191 " tbnz %[tag], 63, rty%= \n"
192 "done%=: str %[gw], [%[pong]] \n"
194 " sub %[mbuf], %[wqp], #0x80 \n"
195 " prfm pldl1keep, [%[mbuf]] \n"
196 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
198 : [tag_loc] "r"(base + SSOW_LF_GWS_TAG),
199 [wqp_loc] "r"(base + SSOW_LF_GWS_WQP), [gw] "r"(dws->gw_wdata),
200 [pong] "r"(pair_base + SSOW_LF_GWS_OP_GET_WORK0));
202 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
203 while ((BIT_ULL(63)) & gw.u64[0])
204 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
205 gw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP);
206 plt_write64(dws->gw_wdata, pair_base + SSOW_LF_GWS_OP_GET_WORK0);
207 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
210 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
211 (gw.u64[0] & (0x3FFull << 36)) << 4 |
212 (gw.u64[0] & 0xffffffff);
214 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
215 if ((flags & CPT_RX_WQE_F) &&
216 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
217 RTE_EVENT_TYPE_CRYPTODEV)) {
218 gw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);
219 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
220 RTE_EVENT_TYPE_ETHDEV) {
221 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
223 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
224 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
225 gw.u64[0] & 0xFFFFF, flags,
227 /* Extracting tstamp, if PTP enabled*/
228 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
230 CNXK_SSO_WQE_SG_PTR);
231 cn9k_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
233 flags & NIX_RX_OFFLOAD_TSTAMP_F,
234 (uint64_t *)tstamp_ptr);
239 ev->event = gw.u64[0];
245 static __rte_always_inline uint16_t
246 cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,
247 const uint32_t flags, const void *const lookup_mem)
250 __uint128_t get_work;
256 plt_write64(ws->gw_wdata, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
258 if (flags & NIX_RX_OFFLOAD_PTYPE_F)
259 rte_prefetch_non_temporal(lookup_mem);
260 #ifdef RTE_ARCH_ARM64
261 asm volatile(PLT_CPU_FEATURE_PREAMBLE
262 " ldr %[tag], [%[tag_loc]] \n"
263 " ldr %[wqp], [%[wqp_loc]] \n"
264 " tbz %[tag], 63, done%= \n"
267 " ldr %[tag], [%[tag_loc]] \n"
268 " ldr %[wqp], [%[wqp_loc]] \n"
269 " tbnz %[tag], 63, rty%= \n"
271 " sub %[mbuf], %[wqp], #0x80 \n"
272 " prfm pldl1keep, [%[mbuf]] \n"
273 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
275 : [tag_loc] "r"(ws->base + SSOW_LF_GWS_TAG),
276 [wqp_loc] "r"(ws->base + SSOW_LF_GWS_WQP));
278 gw.u64[0] = plt_read64(ws->base + SSOW_LF_GWS_TAG);
279 while ((BIT_ULL(63)) & gw.u64[0])
280 gw.u64[0] = plt_read64(ws->base + SSOW_LF_GWS_TAG);
282 gw.u64[1] = plt_read64(ws->base + SSOW_LF_GWS_WQP);
283 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
286 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
287 (gw.u64[0] & (0x3FFull << 36)) << 4 |
288 (gw.u64[0] & 0xffffffff);
290 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
291 if ((flags & CPT_RX_WQE_F) &&
292 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
293 RTE_EVENT_TYPE_CRYPTODEV)) {
294 gw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);
295 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
296 RTE_EVENT_TYPE_ETHDEV) {
297 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
299 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
300 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
301 gw.u64[0] & 0xFFFFF, flags,
303 /* Extracting tstamp, if PTP enabled*/
304 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
306 CNXK_SSO_WQE_SG_PTR);
307 cn9k_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
309 flags & NIX_RX_OFFLOAD_TSTAMP_F,
310 (uint64_t *)tstamp_ptr);
315 ev->event = gw.u64[0];
321 /* Used in cleaning up workslot. */
322 static __rte_always_inline uint16_t
323 cn9k_sso_hws_get_work_empty(uint64_t base, struct rte_event *ev)
326 __uint128_t get_work;
331 #ifdef RTE_ARCH_ARM64
332 asm volatile(PLT_CPU_FEATURE_PREAMBLE
333 " ldr %[tag], [%[tag_loc]] \n"
334 " ldr %[wqp], [%[wqp_loc]] \n"
335 " tbz %[tag], 63, done%= \n"
338 " ldr %[tag], [%[tag_loc]] \n"
339 " ldr %[wqp], [%[wqp_loc]] \n"
340 " tbnz %[tag], 63, rty%= \n"
342 " sub %[mbuf], %[wqp], #0x80 \n"
343 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
345 : [tag_loc] "r"(base + SSOW_LF_GWS_TAG),
346 [wqp_loc] "r"(base + SSOW_LF_GWS_WQP));
348 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
349 while ((BIT_ULL(63)) & gw.u64[0])
350 gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
352 gw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP);
353 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
356 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
357 (gw.u64[0] & (0x3FFull << 36)) << 4 |
358 (gw.u64[0] & 0xffffffff);
360 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
361 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
362 RTE_EVENT_TYPE_ETHDEV) {
363 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
365 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
366 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
367 gw.u64[0] & 0xFFFFF, 0, NULL);
372 ev->event = gw.u64[0];
378 /* CN9K Fastpath functions. */
379 uint16_t __rte_hot cn9k_sso_hws_enq(void *port, const struct rte_event *ev);
380 uint16_t __rte_hot cn9k_sso_hws_enq_burst(void *port,
381 const struct rte_event ev[],
383 uint16_t __rte_hot cn9k_sso_hws_enq_new_burst(void *port,
384 const struct rte_event ev[],
386 uint16_t __rte_hot cn9k_sso_hws_enq_fwd_burst(void *port,
387 const struct rte_event ev[],
390 uint16_t __rte_hot cn9k_sso_hws_dual_enq(void *port,
391 const struct rte_event *ev);
392 uint16_t __rte_hot cn9k_sso_hws_dual_enq_burst(void *port,
393 const struct rte_event ev[],
395 uint16_t __rte_hot cn9k_sso_hws_dual_enq_new_burst(void *port,
396 const struct rte_event ev[],
398 uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,
399 const struct rte_event ev[],
401 uint16_t __rte_hot cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[],
403 uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],
406 #define R(name, flags) \
407 uint16_t __rte_hot cn9k_sso_hws_deq_##name( \
408 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
409 uint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \
410 void *port, struct rte_event ev[], uint16_t nb_events, \
411 uint64_t timeout_ticks); \
412 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_##name( \
413 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
414 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_burst_##name( \
415 void *port, struct rte_event ev[], uint16_t nb_events, \
416 uint64_t timeout_ticks); \
417 uint16_t __rte_hot cn9k_sso_hws_deq_ca_##name( \
418 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
419 uint16_t __rte_hot cn9k_sso_hws_deq_ca_burst_##name( \
420 void *port, struct rte_event ev[], uint16_t nb_events, \
421 uint64_t timeout_ticks); \
422 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_##name( \
423 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
424 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_burst_##name( \
425 void *port, struct rte_event ev[], uint16_t nb_events, \
426 uint64_t timeout_ticks); \
427 uint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \
428 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
429 uint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \
430 void *port, struct rte_event ev[], uint16_t nb_events, \
431 uint64_t timeout_ticks); \
432 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_##name( \
433 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
434 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_burst_##name( \
435 void *port, struct rte_event ev[], uint16_t nb_events, \
436 uint64_t timeout_ticks); \
437 uint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_##name( \
438 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
439 uint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_burst_##name( \
440 void *port, struct rte_event ev[], uint16_t nb_events, \
441 uint64_t timeout_ticks); \
442 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_seg_##name( \
443 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
444 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_ca_seg_burst_##name( \
445 void *port, struct rte_event ev[], uint16_t nb_events, \
446 uint64_t timeout_ticks);
448 NIX_RX_FASTPATH_MODES
451 #define SSO_DEQ(fn, flags) \
452 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
453 uint64_t timeout_ticks) \
455 struct cn9k_sso_hws *ws = port; \
456 RTE_SET_USED(timeout_ticks); \
457 if (ws->swtag_req) { \
459 cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_TAG); \
462 return cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
465 #define SSO_DEQ_SEG(fn, flags) SSO_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
466 #define SSO_DEQ_CA(fn, flags) SSO_DEQ(fn, flags | CPT_RX_WQE_F)
467 #define SSO_DEQ_CA_SEG(fn, flags) SSO_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
469 #define SSO_DEQ_TMO(fn, flags) \
470 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
471 uint64_t timeout_ticks) \
473 struct cn9k_sso_hws *ws = port; \
476 if (ws->swtag_req) { \
478 cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_TAG); \
481 ret = cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \
482 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \
483 ret = cn9k_sso_hws_get_work(ws, ev, flags, \
488 #define SSO_DEQ_TMO_SEG(fn, flags) SSO_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
489 #define SSO_DEQ_TMO_CA(fn, flags) SSO_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
490 #define SSO_DEQ_TMO_CA_SEG(fn, flags) SSO_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
492 #define R(name, flags) \
493 uint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \
494 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
495 uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \
496 void *port, struct rte_event ev[], uint16_t nb_events, \
497 uint64_t timeout_ticks); \
498 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_##name( \
499 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
500 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_burst_##name( \
501 void *port, struct rte_event ev[], uint16_t nb_events, \
502 uint64_t timeout_ticks); \
503 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_##name( \
504 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
505 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_burst_##name( \
506 void *port, struct rte_event ev[], uint16_t nb_events, \
507 uint64_t timeout_ticks); \
508 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_##name( \
509 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
510 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_burst_##name( \
511 void *port, struct rte_event ev[], uint16_t nb_events, \
512 uint64_t timeout_ticks); \
513 uint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \
514 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
515 uint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \
516 void *port, struct rte_event ev[], uint16_t nb_events, \
517 uint64_t timeout_ticks); \
518 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_##name( \
519 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
520 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_burst_##name( \
521 void *port, struct rte_event ev[], uint16_t nb_events, \
522 uint64_t timeout_ticks); \
523 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_##name( \
524 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
525 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_burst_##name( \
526 void *port, struct rte_event ev[], uint16_t nb_events, \
527 uint64_t timeout_ticks); \
528 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_seg_##name( \
529 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
530 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name( \
531 void *port, struct rte_event ev[], uint16_t nb_events, \
532 uint64_t timeout_ticks);
534 NIX_RX_FASTPATH_MODES
537 #define SSO_DUAL_DEQ(fn, flags) \
538 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
539 uint64_t timeout_ticks) \
541 struct cn9k_sso_hws_dual *dws = port; \
543 RTE_SET_USED(timeout_ticks); \
544 if (dws->swtag_req) { \
545 dws->swtag_req = 0; \
546 cnxk_sso_hws_swtag_wait(dws->base[!dws->vws] + \
550 gw = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \
551 dws->base[!dws->vws], ev, \
553 dws->vws = !dws->vws; \
557 #define SSO_DUAL_DEQ_SEG(fn, flags) SSO_DUAL_DEQ(fn, flags | NIX_RX_MULTI_SEG_F)
558 #define SSO_DUAL_DEQ_CA(fn, flags) SSO_DUAL_DEQ(fn, flags | CPT_RX_WQE_F)
559 #define SSO_DUAL_DEQ_CA_SEG(fn, flags) \
560 SSO_DUAL_DEQ_SEG(fn, flags | CPT_RX_WQE_F)
562 #define SSO_DUAL_DEQ_TMO(fn, flags) \
563 uint16_t __rte_hot fn(void *port, struct rte_event *ev, \
564 uint64_t timeout_ticks) \
566 struct cn9k_sso_hws_dual *dws = port; \
569 if (dws->swtag_req) { \
570 dws->swtag_req = 0; \
571 cnxk_sso_hws_swtag_wait(dws->base[!dws->vws] + \
575 ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \
576 dws->base[!dws->vws], ev, \
578 dws->vws = !dws->vws; \
579 for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \
580 ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \
581 dws->base[!dws->vws], \
583 dws->vws = !dws->vws; \
588 #define SSO_DUAL_DEQ_TMO_SEG(fn, flags) \
589 SSO_DUAL_DEQ_TMO(fn, flags | NIX_RX_MULTI_SEG_F)
590 #define SSO_DUAL_DEQ_TMO_CA(fn, flags) \
591 SSO_DUAL_DEQ_TMO(fn, flags | CPT_RX_WQE_F)
592 #define SSO_DUAL_DEQ_TMO_CA_SEG(fn, flags) \
593 SSO_DUAL_DEQ_TMO_SEG(fn, flags | CPT_RX_WQE_F)
595 #define SSO_CMN_DEQ_BURST(fnb, fn, flags) \
596 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
597 uint16_t nb_events, uint64_t timeout_ticks) \
599 RTE_SET_USED(nb_events); \
600 return fn(port, ev, timeout_ticks); \
603 #define SSO_CMN_DEQ_SEG_BURST(fnb, fn, flags) \
604 uint16_t __rte_hot fnb(void *port, struct rte_event ev[], \
605 uint16_t nb_events, uint64_t timeout_ticks) \
607 RTE_SET_USED(nb_events); \
608 return fn(port, ev, timeout_ticks); \
611 static __rte_always_inline void
612 cn9k_sso_txq_fc_wait(const struct cn9k_eth_txq *txq)
614 while ((uint64_t)txq->nb_sqb_bufs_adj <=
615 __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
619 static __rte_always_inline struct cn9k_eth_txq *
620 cn9k_sso_hws_xtract_meta(struct rte_mbuf *m, uint64_t *txq_data)
622 return (struct cn9k_eth_txq
623 *)(txq_data[(txq_data[m->port] >> 48) +
624 rte_event_eth_tx_adapter_txq_get(m)] &
628 #if defined(RTE_ARCH_ARM64)
630 static __rte_always_inline void
631 cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,
632 struct rte_mbuf *m, uint64_t *cmd,
635 struct cn9k_outb_priv_data *outb_priv;
636 rte_iova_t io_addr = txq->cpt_io_addr;
637 uint64_t *lmt_addr = txq->lmt_addr;
638 struct cn9k_sec_sess_priv mdata;
639 struct nix_send_hdr_s *send_hdr;
640 uint64_t sa_base = txq->sa_base;
641 uint32_t pkt_len, dlen_adj, rlen;
642 uint64x2_t cmd01, cmd23;
643 uint64_t lmt_status, sa;
644 union nix_send_sg_s *sg;
645 uintptr_t dptr, nixtx;
646 uint64_t ucode_cmd[4];
650 mdata.u64 = *rte_security_dynfield(m);
651 send_hdr = (struct nix_send_hdr_s *)cmd;
652 if (flags & NIX_TX_NEED_EXT_HDR)
653 sg = (union nix_send_sg_s *)&cmd[4];
655 sg = (union nix_send_sg_s *)&cmd[2];
657 if (flags & NIX_TX_NEED_SEND_HDR_W1)
658 l2_len = cmd[1] & 0xFF;
663 dptr = *(uint64_t *)(sg + 1);
664 pkt_len = send_hdr->w0.total;
667 rlen = pkt_len - l2_len;
668 rlen = (rlen + mdata.roundup_len) + (mdata.roundup_byte - 1);
669 rlen &= ~(uint64_t)(mdata.roundup_byte - 1);
670 rlen += mdata.partial_len;
671 dlen_adj = rlen - pkt_len + l2_len;
673 /* Update send descriptors. Security is single segment only */
674 send_hdr->w0.total = pkt_len + dlen_adj;
675 sg->seg1_size = pkt_len + dlen_adj;
677 /* Get area where NIX descriptor needs to be stored */
678 nixtx = dptr + pkt_len + dlen_adj;
680 nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1);
682 roc_lmt_mov_nv((void *)(nixtx + 16), cmd, cn9k_nix_tx_ext_subs(flags));
684 /* Load opcode and cptr already prepared at pkt metadata set */
686 pkt_len += sizeof(struct roc_onf_ipsec_outb_hdr) +
687 ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ;
688 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
690 sa = (uintptr_t)roc_nix_inl_onf_ipsec_outb_sa(sa_base, mdata.sa_idx);
691 ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | sa);
692 ucode_cmd[0] = (ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |
693 0x40UL << 48 | pkt_len);
695 /* CPT Word 0 and Word 1 */
696 cmd01 = vdupq_n_u64((nixtx + 16) | (cn9k_nix_tx_ext_subs(flags) + 1));
697 /* CPT_RES_S is 16B above NIXTX */
698 cmd01 = vsetq_lane_u8(nixtx & BIT_ULL(7), cmd01, 8);
700 /* CPT word 2 and 3 */
701 cmd23 = vdupq_n_u64(0);
702 cmd23 = vsetq_lane_u64((((uint64_t)RTE_EVENT_TYPE_CPU << 28) |
703 CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0);
704 cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1);
706 dptr += l2_len - ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ -
707 sizeof(struct roc_onf_ipsec_outb_hdr);
711 /* Update IV to zero and l2 sz */
712 *(uint16_t *)(dptr + sizeof(struct roc_onf_ipsec_outb_hdr)) =
713 rte_cpu_to_be_16(ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ);
714 iv = (uint64_t *)(dptr + 8);
718 /* Head wait if needed */
720 roc_sso_hws_head_wait(base);
723 outb_priv = roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd((void *)sa);
724 esn = outb_priv->esn;
725 outb_priv->esn = esn + 1;
727 ucode_cmd[0] |= (esn >> 32) << 16;
728 esn = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1));
730 /* Update ESN and IPID and IV */
731 *(uint64_t *)dptr = esn << 32 | esn;
734 cn9k_sso_txq_fc_wait(txq);
736 /* Write CPT instruction to lmt line */
737 vst1q_u64(lmt_addr, cmd01);
738 vst1q_u64(lmt_addr + 2, cmd23);
740 roc_lmt_mov_seg(lmt_addr + 4, ucode_cmd, 2);
742 if (roc_lmt_submit_ldeor(io_addr) == 0) {
744 vst1q_u64(lmt_addr, cmd01);
745 vst1q_u64(lmt_addr + 2, cmd23);
746 roc_lmt_mov_seg(lmt_addr + 4, ucode_cmd, 2);
748 lmt_status = roc_lmt_submit_ldeor(io_addr);
749 } while (lmt_status == 0);
755 cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,
756 struct rte_mbuf *m, uint64_t *cmd,
767 static __rte_always_inline uint16_t
768 cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,
769 uint64_t *txq_data, const uint32_t flags)
771 struct rte_mbuf *m = ev->mbuf;
772 uint16_t ref_cnt = m->refcnt;
773 struct cn9k_eth_txq *txq;
775 /* Perform header writes before barrier for TSO */
776 cn9k_nix_xmit_prepare_tso(m, flags);
777 /* Lets commit any changes in the packet here in case when
778 * fast free is set as no further changes will be made to mbuf.
779 * In case of fast free is not set, both cn9k_nix_prepare_mseg()
780 * and cn9k_nix_xmit_prepare() has a barrier after refcnt update.
782 if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) &&
783 !(flags & NIX_TX_OFFLOAD_SECURITY_F))
785 txq = cn9k_sso_hws_xtract_meta(m, txq_data);
786 cn9k_nix_tx_skeleton(txq, cmd, flags, 0);
787 cn9k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, txq->mark_flag,
790 if (flags & NIX_TX_OFFLOAD_SECURITY_F) {
791 uint64_t ol_flags = m->ol_flags;
793 if (ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
794 uintptr_t ssow_base = base;
799 cn9k_sso_hws_xmit_sec_one(txq, ssow_base, m, cmd,
804 if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
808 if (flags & NIX_TX_MULTI_SEG_F) {
809 const uint16_t segdw = cn9k_nix_prepare_mseg(m, cmd, flags);
810 cn9k_nix_xmit_prepare_tstamp(txq, cmd, m->ol_flags, segdw,
812 if (!CNXK_TT_FROM_EVENT(ev->event)) {
813 cn9k_nix_xmit_mseg_prep_lmt(cmd, txq->lmt_addr, segdw);
814 roc_sso_hws_head_wait(base);
815 cn9k_sso_txq_fc_wait(txq);
816 if (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)
817 cn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr,
818 txq->io_addr, segdw);
820 cn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr, txq->io_addr,
824 cn9k_nix_xmit_prepare_tstamp(txq, cmd, m->ol_flags, 4, flags);
825 if (!CNXK_TT_FROM_EVENT(ev->event)) {
826 cn9k_nix_xmit_prep_lmt(cmd, txq->lmt_addr, flags);
827 roc_sso_hws_head_wait(base);
828 cn9k_sso_txq_fc_wait(txq);
829 if (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)
830 cn9k_nix_xmit_one(cmd, txq->lmt_addr,
831 txq->io_addr, flags);
833 cn9k_nix_xmit_one(cmd, txq->lmt_addr, txq->io_addr,
839 if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
844 cnxk_sso_hws_swtag_flush(base + SSOW_LF_GWS_TAG,
845 base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
850 #define T(name, sz, flags) \
851 uint16_t __rte_hot cn9k_sso_hws_tx_adptr_enq_##name( \
852 void *port, struct rte_event ev[], uint16_t nb_events); \
853 uint16_t __rte_hot cn9k_sso_hws_tx_adptr_enq_seg_##name( \
854 void *port, struct rte_event ev[], uint16_t nb_events); \
855 uint16_t __rte_hot cn9k_sso_hws_dual_tx_adptr_enq_##name( \
856 void *port, struct rte_event ev[], uint16_t nb_events); \
857 uint16_t __rte_hot cn9k_sso_hws_dual_tx_adptr_enq_seg_##name( \
858 void *port, struct rte_event ev[], uint16_t nb_events);
860 NIX_TX_FASTPATH_MODES
863 #define SSO_TX(fn, sz, flags) \
864 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
865 uint16_t nb_events) \
867 struct cn9k_sso_hws *ws = port; \
869 RTE_SET_USED(nb_events); \
870 return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, \
871 (uint64_t *)ws->tx_adptr_data, \
875 #define SSO_TX_SEG(fn, sz, flags) \
876 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
877 uint16_t nb_events) \
879 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
880 struct cn9k_sso_hws *ws = port; \
881 RTE_SET_USED(nb_events); \
882 return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, \
883 (uint64_t *)ws->tx_adptr_data, \
884 (flags) | NIX_TX_MULTI_SEG_F); \
887 #define SSO_DUAL_TX(fn, sz, flags) \
888 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
889 uint16_t nb_events) \
891 struct cn9k_sso_hws_dual *ws = port; \
893 RTE_SET_USED(nb_events); \
894 return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, \
895 (uint64_t *)ws->tx_adptr_data, \
899 #define SSO_DUAL_TX_SEG(fn, sz, flags) \
900 uint16_t __rte_hot fn(void *port, struct rte_event ev[], \
901 uint16_t nb_events) \
903 uint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \
904 struct cn9k_sso_hws_dual *ws = port; \
905 RTE_SET_USED(nb_events); \
906 return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, \
907 (uint64_t *)ws->tx_adptr_data, \
908 (flags) | NIX_TX_MULTI_SEG_F); \