1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CN9K_WORKER_H__
6 #define __CN9K_WORKER_H__
8 #include <rte_eventdev.h>
11 #include "cnxk_ethdev.h"
12 #include "cnxk_eventdev.h"
13 #include "cnxk_worker.h"
14 #include "cn9k_cryptodev_ops.h"
16 #include "cn9k_ethdev.h"
22 static __rte_always_inline uint8_t
23 cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
25 const uint32_t tag = (uint32_t)ev->event;
26 const uint8_t new_tt = ev->sched_type;
27 const uint64_t event_ptr = ev->u64;
28 const uint16_t grp = ev->queue_id;
30 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
31 if (ws->xaq_lmt <= *ws->fc_mem)
34 cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]);
38 static __rte_always_inline void
39 cn9k_sso_hws_fwd_swtag(struct cn9k_sso_hws_state *vws,
40 const struct rte_event *ev)
42 const uint32_t tag = (uint32_t)ev->event;
43 const uint8_t new_tt = ev->sched_type;
44 const uint8_t cur_tt = CNXK_TT_FROM_TAG(plt_read64(vws->tag_op));
47 * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED
49 * SSO_TT_ORDERED norm norm untag
50 * SSO_TT_ATOMIC norm norm untag
51 * SSO_TT_UNTAGGED norm norm NOOP
54 if (new_tt == SSO_TT_UNTAGGED) {
55 if (cur_tt != SSO_TT_UNTAGGED)
56 cnxk_sso_hws_swtag_untag(
57 CN9K_SSOW_GET_BASE_ADDR(vws->getwrk_op) +
58 SSOW_LF_GWS_OP_SWTAG_UNTAG);
60 cnxk_sso_hws_swtag_norm(tag, new_tt, vws->swtag_norm_op);
64 static __rte_always_inline void
65 cn9k_sso_hws_fwd_group(struct cn9k_sso_hws_state *ws,
66 const struct rte_event *ev, const uint16_t grp)
68 const uint32_t tag = (uint32_t)ev->event;
69 const uint8_t new_tt = ev->sched_type;
71 plt_write64(ev->u64, CN9K_SSOW_GET_BASE_ADDR(ws->getwrk_op) +
72 SSOW_LF_GWS_OP_UPD_WQP_GRP1);
73 cnxk_sso_hws_swtag_desched(tag, new_tt, grp, ws->swtag_desched_op);
76 static __rte_always_inline void
77 cn9k_sso_hws_forward_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
79 const uint8_t grp = ev->queue_id;
81 /* Group hasn't changed, Use SWTAG to forward the event */
82 if (CNXK_GRP_FROM_TAG(plt_read64(ws->tag_op)) == grp) {
83 cn9k_sso_hws_fwd_swtag((struct cn9k_sso_hws_state *)ws, ev);
87 * Group has been changed for group based work pipelining,
88 * Use deschedule/add_work operation to transfer the event to
91 cn9k_sso_hws_fwd_group((struct cn9k_sso_hws_state *)ws, ev,
98 static __rte_always_inline uint8_t
99 cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws,
100 const struct rte_event *ev)
102 const uint32_t tag = (uint32_t)ev->event;
103 const uint8_t new_tt = ev->sched_type;
104 const uint64_t event_ptr = ev->u64;
105 const uint16_t grp = ev->queue_id;
107 rte_atomic_thread_fence(__ATOMIC_ACQ_REL);
108 if (dws->xaq_lmt <= *dws->fc_mem)
111 cnxk_sso_hws_add_work(event_ptr, tag, new_tt, dws->grps_base[grp]);
115 static __rte_always_inline void
116 cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws,
117 struct cn9k_sso_hws_state *vws,
118 const struct rte_event *ev)
120 const uint8_t grp = ev->queue_id;
122 /* Group hasn't changed, Use SWTAG to forward the event */
123 if (CNXK_GRP_FROM_TAG(plt_read64(vws->tag_op)) == grp) {
124 cn9k_sso_hws_fwd_swtag(vws, ev);
128 * Group has been changed for group based work pipelining,
129 * Use deschedule/add_work operation to transfer the event to
132 cn9k_sso_hws_fwd_group(vws, ev, grp);
136 static __rte_always_inline void
137 cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
138 const uint32_t tag, const uint32_t flags,
139 const void *const lookup_mem)
141 const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
142 (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
144 cn9k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
145 (struct rte_mbuf *)mbuf, lookup_mem,
146 mbuf_init | ((uint64_t)port_id) << 48, flags);
149 static __rte_always_inline uint16_t
150 cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,
151 struct cn9k_sso_hws_state *ws_pair,
152 struct rte_event *ev, const uint32_t flags,
153 const void *const lookup_mem,
154 struct cnxk_timesync_info *const tstamp)
156 const uint64_t set_gw = BIT_ULL(16) | 1;
158 __uint128_t get_work;
164 if (flags & NIX_RX_OFFLOAD_PTYPE_F)
165 rte_prefetch_non_temporal(lookup_mem);
166 #ifdef RTE_ARCH_ARM64
167 asm volatile(PLT_CPU_FEATURE_PREAMBLE
169 " ldr %[tag], [%[tag_loc]] \n"
170 " ldr %[wqp], [%[wqp_loc]] \n"
171 " tbnz %[tag], 63, rty%= \n"
172 "done%=: str %[gw], [%[pong]] \n"
174 " sub %[mbuf], %[wqp], #0x80 \n"
175 " prfm pldl1keep, [%[mbuf]] \n"
176 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
178 : [tag_loc] "r"(ws->tag_op), [wqp_loc] "r"(ws->wqp_op),
179 [gw] "r"(set_gw), [pong] "r"(ws_pair->getwrk_op));
181 gw.u64[0] = plt_read64(ws->tag_op);
182 while ((BIT_ULL(63)) & gw.u64[0])
183 gw.u64[0] = plt_read64(ws->tag_op);
184 gw.u64[1] = plt_read64(ws->wqp_op);
185 plt_write64(set_gw, ws_pair->getwrk_op);
186 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
189 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
190 (gw.u64[0] & (0x3FFull << 36)) << 4 |
191 (gw.u64[0] & 0xffffffff);
193 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
194 if ((flags & CPT_RX_WQE_F) &&
195 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
196 RTE_EVENT_TYPE_CRYPTODEV)) {
197 gw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);
198 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
199 RTE_EVENT_TYPE_ETHDEV) {
200 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
202 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
203 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
204 gw.u64[0] & 0xFFFFF, flags,
206 /* Extracting tstamp, if PTP enabled*/
207 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
209 CNXK_SSO_WQE_SG_PTR);
210 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
211 flags & NIX_RX_OFFLOAD_TSTAMP_F,
212 flags & NIX_RX_MULTI_SEG_F,
213 (uint64_t *)tstamp_ptr);
218 ev->event = gw.u64[0];
224 static __rte_always_inline uint16_t
225 cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,
226 const uint32_t flags, const void *const lookup_mem)
229 __uint128_t get_work;
235 plt_write64(BIT_ULL(16) | /* wait for work. */
236 1, /* Use Mask set 0. */
239 if (flags & NIX_RX_OFFLOAD_PTYPE_F)
240 rte_prefetch_non_temporal(lookup_mem);
241 #ifdef RTE_ARCH_ARM64
242 asm volatile(PLT_CPU_FEATURE_PREAMBLE
243 " ldr %[tag], [%[tag_loc]] \n"
244 " ldr %[wqp], [%[wqp_loc]] \n"
245 " tbz %[tag], 63, done%= \n"
248 " ldr %[tag], [%[tag_loc]] \n"
249 " ldr %[wqp], [%[wqp_loc]] \n"
250 " tbnz %[tag], 63, rty%= \n"
252 " sub %[mbuf], %[wqp], #0x80 \n"
253 " prfm pldl1keep, [%[mbuf]] \n"
254 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
256 : [tag_loc] "r"(ws->tag_op), [wqp_loc] "r"(ws->wqp_op));
258 gw.u64[0] = plt_read64(ws->tag_op);
259 while ((BIT_ULL(63)) & gw.u64[0])
260 gw.u64[0] = plt_read64(ws->tag_op);
262 gw.u64[1] = plt_read64(ws->wqp_op);
263 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
266 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
267 (gw.u64[0] & (0x3FFull << 36)) << 4 |
268 (gw.u64[0] & 0xffffffff);
270 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
271 if ((flags & CPT_RX_WQE_F) &&
272 (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
273 RTE_EVENT_TYPE_CRYPTODEV)) {
274 gw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);
275 } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
276 RTE_EVENT_TYPE_ETHDEV) {
277 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
279 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
280 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
281 gw.u64[0] & 0xFFFFF, flags,
283 /* Extracting tstamp, if PTP enabled*/
284 tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
286 CNXK_SSO_WQE_SG_PTR);
287 cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
289 flags & NIX_RX_OFFLOAD_TSTAMP_F,
290 flags & NIX_RX_MULTI_SEG_F,
291 (uint64_t *)tstamp_ptr);
296 ev->event = gw.u64[0];
302 /* Used in cleaning up workslot. */
303 static __rte_always_inline uint16_t
304 cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)
307 __uint128_t get_work;
312 #ifdef RTE_ARCH_ARM64
313 asm volatile(PLT_CPU_FEATURE_PREAMBLE
314 " ldr %[tag], [%[tag_loc]] \n"
315 " ldr %[wqp], [%[wqp_loc]] \n"
316 " tbz %[tag], 63, done%= \n"
319 " ldr %[tag], [%[tag_loc]] \n"
320 " ldr %[wqp], [%[wqp_loc]] \n"
321 " tbnz %[tag], 63, rty%= \n"
323 " sub %[mbuf], %[wqp], #0x80 \n"
324 : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
326 : [tag_loc] "r"(ws->tag_op), [wqp_loc] "r"(ws->wqp_op));
328 gw.u64[0] = plt_read64(ws->tag_op);
329 while ((BIT_ULL(63)) & gw.u64[0])
330 gw.u64[0] = plt_read64(ws->tag_op);
332 gw.u64[1] = plt_read64(ws->wqp_op);
333 mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
336 gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |
337 (gw.u64[0] & (0x3FFull << 36)) << 4 |
338 (gw.u64[0] & 0xffffffff);
340 if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
341 if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
342 RTE_EVENT_TYPE_ETHDEV) {
343 uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
345 gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
346 cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
347 gw.u64[0] & 0xFFFFF, 0, NULL);
352 ev->event = gw.u64[0];
358 /* CN9K Fastpath functions. */
359 uint16_t __rte_hot cn9k_sso_hws_enq(void *port, const struct rte_event *ev);
360 uint16_t __rte_hot cn9k_sso_hws_enq_burst(void *port,
361 const struct rte_event ev[],
363 uint16_t __rte_hot cn9k_sso_hws_enq_new_burst(void *port,
364 const struct rte_event ev[],
366 uint16_t __rte_hot cn9k_sso_hws_enq_fwd_burst(void *port,
367 const struct rte_event ev[],
370 uint16_t __rte_hot cn9k_sso_hws_dual_enq(void *port,
371 const struct rte_event *ev);
372 uint16_t __rte_hot cn9k_sso_hws_dual_enq_burst(void *port,
373 const struct rte_event ev[],
375 uint16_t __rte_hot cn9k_sso_hws_dual_enq_new_burst(void *port,
376 const struct rte_event ev[],
378 uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,
379 const struct rte_event ev[],
381 uint16_t __rte_hot cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[],
383 uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],
386 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
387 uint16_t __rte_hot cn9k_sso_hws_deq_##name( \
388 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
389 uint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \
390 void *port, struct rte_event ev[], uint16_t nb_events, \
391 uint64_t timeout_ticks); \
392 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_##name( \
393 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
394 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_burst_##name( \
395 void *port, struct rte_event ev[], uint16_t nb_events, \
396 uint64_t timeout_ticks); \
397 uint16_t __rte_hot cn9k_sso_hws_deq_ca_##name( \
398 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
399 uint16_t __rte_hot cn9k_sso_hws_deq_ca_burst_##name( \
400 void *port, struct rte_event ev[], uint16_t nb_events, \
401 uint64_t timeout_ticks); \
402 uint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \
403 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
404 uint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \
405 void *port, struct rte_event ev[], uint16_t nb_events, \
406 uint64_t timeout_ticks); \
407 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_##name( \
408 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
409 uint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_burst_##name( \
410 void *port, struct rte_event ev[], uint16_t nb_events, \
411 uint64_t timeout_ticks); \
412 uint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_##name( \
413 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
414 uint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_burst_##name( \
415 void *port, struct rte_event ev[], uint16_t nb_events, \
416 uint64_t timeout_ticks);
418 NIX_RX_FASTPATH_MODES
421 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
422 uint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \
423 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
424 uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \
425 void *port, struct rte_event ev[], uint16_t nb_events, \
426 uint64_t timeout_ticks); \
427 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_##name( \
428 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
429 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_burst_##name( \
430 void *port, struct rte_event ev[], uint16_t nb_events, \
431 uint64_t timeout_ticks); \
432 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_##name( \
433 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
434 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_burst_##name( \
435 void *port, struct rte_event ev[], uint16_t nb_events, \
436 uint64_t timeout_ticks); \
437 uint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \
438 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
439 uint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \
440 void *port, struct rte_event ev[], uint16_t nb_events, \
441 uint64_t timeout_ticks); \
442 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_##name( \
443 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
444 uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_burst_##name( \
445 void *port, struct rte_event ev[], uint16_t nb_events, \
446 uint64_t timeout_ticks); \
447 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_##name( \
448 void *port, struct rte_event *ev, uint64_t timeout_ticks); \
449 uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_burst_##name( \
450 void *port, struct rte_event ev[], uint16_t nb_events, \
451 uint64_t timeout_ticks);
453 NIX_RX_FASTPATH_MODES
456 static __rte_always_inline void
457 cn9k_sso_txq_fc_wait(const struct cn9k_eth_txq *txq)
459 while (!((txq->nb_sqb_bufs_adj -
460 __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED))
461 << (txq)->sqes_per_sqb_log2))
465 static __rte_always_inline const struct cn9k_eth_txq *
466 cn9k_sso_hws_xtract_meta(struct rte_mbuf *m,
467 const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])
469 return (const struct cn9k_eth_txq *)
470 txq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];
473 static __rte_always_inline void
474 cn9k_sso_hws_prepare_pkt(const struct cn9k_eth_txq *txq, struct rte_mbuf *m,
475 uint64_t *cmd, const uint32_t flags)
477 roc_lmt_mov(cmd, txq->cmd, cn9k_nix_tx_ext_subs(flags));
478 cn9k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt);
481 #if defined(RTE_ARCH_ARM64)
483 static __rte_always_inline void
484 cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,
485 struct rte_mbuf *m, uint64_t *cmd,
488 struct cn9k_outb_priv_data *outb_priv;
489 rte_iova_t io_addr = txq->cpt_io_addr;
490 uint64_t *lmt_addr = txq->lmt_addr;
491 struct cn9k_sec_sess_priv mdata;
492 struct nix_send_hdr_s *send_hdr;
493 uint64_t sa_base = txq->sa_base;
494 uint32_t pkt_len, dlen_adj, rlen;
495 uint64x2_t cmd01, cmd23;
496 uint64_t lmt_status, sa;
497 union nix_send_sg_s *sg;
498 uintptr_t dptr, nixtx;
499 uint64_t ucode_cmd[4];
503 mdata.u64 = *rte_security_dynfield(m);
504 send_hdr = (struct nix_send_hdr_s *)cmd;
505 if (flags & NIX_TX_NEED_EXT_HDR)
506 sg = (union nix_send_sg_s *)&cmd[4];
508 sg = (union nix_send_sg_s *)&cmd[2];
510 if (flags & NIX_TX_NEED_SEND_HDR_W1)
511 l2_len = cmd[1] & 0xFF;
516 dptr = *(uint64_t *)(sg + 1);
517 pkt_len = send_hdr->w0.total;
520 rlen = pkt_len - l2_len;
521 rlen = (rlen + mdata.roundup_len) + (mdata.roundup_byte - 1);
522 rlen &= ~(uint64_t)(mdata.roundup_byte - 1);
523 rlen += mdata.partial_len;
524 dlen_adj = rlen - pkt_len + l2_len;
526 /* Update send descriptors. Security is single segment only */
527 send_hdr->w0.total = pkt_len + dlen_adj;
528 sg->seg1_size = pkt_len + dlen_adj;
530 /* Get area where NIX descriptor needs to be stored */
531 nixtx = dptr + pkt_len + dlen_adj;
533 nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1);
535 roc_lmt_mov((void *)(nixtx + 16), cmd, cn9k_nix_tx_ext_subs(flags));
537 /* Load opcode and cptr already prepared at pkt metadata set */
539 pkt_len += sizeof(struct roc_onf_ipsec_outb_hdr) +
540 ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ;
541 sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
543 sa = (uintptr_t)roc_nix_inl_onf_ipsec_outb_sa(sa_base, mdata.sa_idx);
544 ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | sa);
545 ucode_cmd[0] = (ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |
546 0x40UL << 48 | pkt_len);
548 /* CPT Word 0 and Word 1 */
549 cmd01 = vdupq_n_u64((nixtx + 16) | (cn9k_nix_tx_ext_subs(flags) + 1));
550 /* CPT_RES_S is 16B above NIXTX */
551 cmd01 = vsetq_lane_u8(nixtx & BIT_ULL(7), cmd01, 8);
553 /* CPT word 2 and 3 */
554 cmd23 = vdupq_n_u64(0);
555 cmd23 = vsetq_lane_u64((((uint64_t)RTE_EVENT_TYPE_CPU << 28) |
556 CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0);
557 cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1);
559 dptr += l2_len - ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ -
560 sizeof(struct roc_onf_ipsec_outb_hdr);
564 /* Update IV to zero and l2 sz */
565 *(uint16_t *)(dptr + sizeof(struct roc_onf_ipsec_outb_hdr)) =
566 rte_cpu_to_be_16(ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ);
567 iv = (uint64_t *)(dptr + 8);
571 /* Head wait if needed */
573 roc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);
576 outb_priv = roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd((void *)sa);
577 esn = outb_priv->esn;
578 outb_priv->esn = esn + 1;
580 ucode_cmd[0] |= (esn >> 32) << 16;
581 esn = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1));
583 /* Update ESN and IPID and IV */
584 *(uint64_t *)dptr = esn << 32 | esn;
587 cn9k_sso_txq_fc_wait(txq);
589 /* Write CPT instruction to lmt line */
590 vst1q_u64(lmt_addr, cmd01);
591 vst1q_u64(lmt_addr + 2, cmd23);
593 roc_lmt_mov_seg(lmt_addr + 4, ucode_cmd, 2);
595 if (roc_lmt_submit_ldeor(io_addr) == 0) {
597 vst1q_u64(lmt_addr, cmd01);
598 vst1q_u64(lmt_addr + 2, cmd23);
599 roc_lmt_mov_seg(lmt_addr + 4, ucode_cmd, 2);
601 lmt_status = roc_lmt_submit_ldeor(io_addr);
602 } while (lmt_status == 0);
608 cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,
609 struct rte_mbuf *m, uint64_t *cmd,
620 static __rte_always_inline uint16_t
621 cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,
622 const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
623 const uint32_t flags)
625 struct rte_mbuf *m = ev->mbuf;
626 const struct cn9k_eth_txq *txq;
627 uint16_t ref_cnt = m->refcnt;
629 /* Perform header writes before barrier for TSO */
630 cn9k_nix_xmit_prepare_tso(m, flags);
631 /* Lets commit any changes in the packet here in case when
632 * fast free is set as no further changes will be made to mbuf.
633 * In case of fast free is not set, both cn9k_nix_prepare_mseg()
634 * and cn9k_nix_xmit_prepare() has a barrier after refcnt update.
636 if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) &&
637 !(flags & NIX_TX_OFFLOAD_SECURITY_F))
639 txq = cn9k_sso_hws_xtract_meta(m, txq_data);
640 cn9k_sso_hws_prepare_pkt(txq, m, cmd, flags);
642 if (flags & NIX_TX_OFFLOAD_SECURITY_F) {
643 uint64_t ol_flags = m->ol_flags;
645 if (ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
646 uintptr_t ssow_base = base;
651 cn9k_sso_hws_xmit_sec_one(txq, ssow_base, m, cmd,
656 if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
660 if (flags & NIX_TX_MULTI_SEG_F) {
661 const uint16_t segdw = cn9k_nix_prepare_mseg(m, cmd, flags);
662 if (!CNXK_TT_FROM_EVENT(ev->event)) {
663 cn9k_nix_xmit_mseg_prep_lmt(cmd, txq->lmt_addr, segdw);
664 roc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);
665 cn9k_sso_txq_fc_wait(txq);
666 if (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)
667 cn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr,
668 txq->io_addr, segdw);
670 cn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr, txq->io_addr,
674 if (!CNXK_TT_FROM_EVENT(ev->event)) {
675 cn9k_nix_xmit_prep_lmt(cmd, txq->lmt_addr, flags);
676 roc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);
677 cn9k_sso_txq_fc_wait(txq);
678 if (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)
679 cn9k_nix_xmit_one(cmd, txq->lmt_addr,
680 txq->io_addr, flags);
682 cn9k_nix_xmit_one(cmd, txq->lmt_addr, txq->io_addr,
688 if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
693 cnxk_sso_hws_swtag_flush(base + SSOW_LF_GWS_TAG,
694 base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
699 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
700 uint16_t __rte_hot cn9k_sso_hws_tx_adptr_enq_##name( \
701 void *port, struct rte_event ev[], uint16_t nb_events); \
702 uint16_t __rte_hot cn9k_sso_hws_tx_adptr_enq_seg_##name( \
703 void *port, struct rte_event ev[], uint16_t nb_events); \
704 uint16_t __rte_hot cn9k_sso_hws_dual_tx_adptr_enq_##name( \
705 void *port, struct rte_event ev[], uint16_t nb_events); \
706 uint16_t __rte_hot cn9k_sso_hws_dual_tx_adptr_enq_seg_##name( \
707 void *port, struct rte_event ev[], uint16_t nb_events);
709 NIX_TX_FASTPATH_MODES