1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cnxk_cryptodev_ops.h"
6 #include "cnxk_eventdev.h"
9 crypto_adapter_qp_setup(const struct rte_cryptodev *cdev,
10 struct cnxk_cpt_qp *qp)
12 char name[RTE_MEMPOOL_NAMESIZE];
13 uint32_t cache_size, nb_req;
14 unsigned int req_size;
16 snprintf(name, RTE_MEMPOOL_NAMESIZE, "cnxk_ca_req_%u:%u",
17 cdev->data->dev_id, qp->lf.lf_id);
18 req_size = sizeof(struct cpt_inflight_req);
19 cache_size = RTE_MIN(RTE_MEMPOOL_CACHE_MAX_SIZE, qp->lf.nb_desc / 1.5);
20 nb_req = RTE_MAX(qp->lf.nb_desc, cache_size * rte_lcore_count());
21 qp->ca.req_mp = rte_mempool_create(name, nb_req, req_size, cache_size,
22 0, NULL, NULL, NULL, NULL,
24 if (qp->ca.req_mp == NULL)
27 qp->ca.enabled = true;
33 cnxk_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
34 const struct rte_cryptodev *cdev,
35 int32_t queue_pair_id)
37 struct cnxk_sso_evdev *sso_evdev = cnxk_sso_pmd_priv(event_dev);
38 uint32_t adptr_xae_cnt = 0;
39 struct cnxk_cpt_qp *qp;
42 if (queue_pair_id == -1) {
45 for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {
46 qp = cdev->data->queue_pairs[qp_id];
47 ret = crypto_adapter_qp_setup(cdev, qp);
49 cnxk_crypto_adapter_qp_del(cdev, -1);
52 adptr_xae_cnt += qp->ca.req_mp->size;
55 qp = cdev->data->queue_pairs[queue_pair_id];
56 ret = crypto_adapter_qp_setup(cdev, qp);
59 adptr_xae_cnt = qp->ca.req_mp->size;
62 /* Update crypto adapter XAE count */
63 sso_evdev->adptr_xae_cnt += adptr_xae_cnt;
64 cnxk_sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)event_dev);
70 crypto_adapter_qp_free(struct cnxk_cpt_qp *qp)
72 rte_mempool_free(qp->ca.req_mp);
73 qp->ca.enabled = false;
79 cnxk_crypto_adapter_qp_del(const struct rte_cryptodev *cdev,
80 int32_t queue_pair_id)
82 struct cnxk_cpt_qp *qp;
84 if (queue_pair_id == -1) {
87 for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {
88 qp = cdev->data->queue_pairs[qp_id];
90 crypto_adapter_qp_free(qp);
93 qp = cdev->data->queue_pairs[queue_pair_id];
95 crypto_adapter_qp_free(qp);
102 cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
103 struct rte_event_dev_info *dev_info)
106 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
107 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
108 dev_info->max_event_queues = dev->max_event_queues;
109 dev_info->max_event_queue_flows = (1ULL << 20);
110 dev_info->max_event_queue_priority_levels = 8;
111 dev_info->max_event_priority_levels = 1;
112 dev_info->max_event_ports = dev->max_event_ports;
113 dev_info->max_event_port_dequeue_depth = 1;
114 dev_info->max_event_port_enqueue_depth = 1;
115 dev_info->max_num_events = dev->max_num_events;
116 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
117 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
118 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
119 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
120 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
121 RTE_EVENT_DEV_CAP_NONSEQ_MODE |
122 RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;
126 cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)
128 char pool_name[RTE_MEMZONE_NAMESIZE];
129 uint32_t xaq_cnt, npa_aura_id;
130 const struct rte_memzone *mz;
131 struct npa_aura_s *aura;
132 static int reconfig_cnt;
136 rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
138 plt_err("Failed to release XAQ %d", rc);
141 rte_mempool_free(dev->xaq_pool);
142 dev->xaq_pool = NULL;
146 * Allocate memory for Add work backpressure.
148 mz = rte_memzone_lookup(CNXK_SSO_FC_NAME);
150 mz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME,
151 sizeof(struct npa_aura_s) +
153 0, 0, RTE_CACHE_LINE_SIZE);
155 plt_err("Failed to allocate mem for fcmem");
159 dev->fc_iova = mz->iova;
160 dev->fc_mem = mz->addr;
162 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem +
163 RTE_CACHE_LINE_SIZE);
164 memset(aura, 0, sizeof(struct npa_aura_s));
167 aura->fc_addr = dev->fc_iova;
168 aura->fc_hyst_bits = 0; /* Store count on all updates */
170 /* Taken from HRM 14.3.3(4) */
171 xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;
173 xaq_cnt += dev->xae_cnt / dev->sso.xae_waes;
174 else if (dev->adptr_xae_cnt)
175 xaq_cnt += (dev->adptr_xae_cnt / dev->sso.xae_waes) +
176 (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);
178 xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +
179 (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);
181 plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
182 /* Setup XAQ based on number of nb queues. */
183 snprintf(pool_name, 30, "cnxk_xaq_buf_pool_%d", reconfig_cnt);
184 dev->xaq_pool = (void *)rte_mempool_create_empty(
185 pool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0,
188 if (dev->xaq_pool == NULL) {
189 plt_err("Unable to create empty mempool.");
190 rte_memzone_free(mz);
194 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
195 rte_mbuf_platform_mempool_ops(), aura);
197 plt_err("Unable to set xaqpool ops.");
201 rc = rte_mempool_populate_default(dev->xaq_pool);
203 plt_err("Unable to set populate xaqpool.");
207 /* When SW does addwork (enqueue) check if there is space in XAQ by
208 * comparing fc_addr above against the xaq_lmt calculated below.
209 * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO
210 * to request XAQ to cache them even before enqueue is called.
213 xaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues);
214 dev->nb_xaq_cfg = xaq_cnt;
216 npa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id);
217 return roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id,
218 dev->nb_event_queues);
220 rte_mempool_free(dev->xaq_pool);
221 rte_memzone_free(mz);
226 cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev)
228 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
231 if (event_dev->data->dev_started)
232 event_dev->dev_ops->dev_stop(event_dev);
234 rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
236 plt_err("Failed to release XAQ %d", rc);
240 rte_mempool_free(dev->xaq_pool);
241 dev->xaq_pool = NULL;
242 rc = cnxk_sso_xaq_allocate(dev);
244 plt_err("Failed to alloc XAQ %d", rc);
249 if (event_dev->data->dev_started)
250 event_dev->dev_ops->dev_start(event_dev);
256 cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
257 cnxk_sso_init_hws_mem_t init_hws_fn,
258 cnxk_sso_hws_setup_t setup_hws_fn)
260 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
263 for (i = 0; i < dev->nb_event_ports; i++) {
264 struct cnxk_sso_hws_cookie *ws_cookie;
267 /* Free memory prior to re-allocation if needed */
268 if (event_dev->data->ports[i] != NULL)
269 ws = event_dev->data->ports[i];
271 ws = init_hws_fn(dev, i);
274 ws_cookie = cnxk_sso_hws_get_cookie(ws);
275 ws_cookie->event_dev = event_dev;
276 ws_cookie->configured = 1;
277 event_dev->data->ports[i] = ws;
278 cnxk_sso_port_setup((struct rte_eventdev *)(uintptr_t)event_dev,
284 for (i = i - 1; i >= 0; i--) {
285 event_dev->data->ports[i] = NULL;
286 rte_free(cnxk_sso_hws_get_cookie(event_dev->data->ports[i]));
292 cnxk_sso_restore_links(const struct rte_eventdev *event_dev,
293 cnxk_sso_link_t link_fn)
295 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
296 uint16_t *links_map, hwgrp[CNXK_SSO_MAX_HWGRP];
299 for (i = 0; i < dev->nb_event_ports; i++) {
300 uint16_t nb_hwgrp = 0;
302 links_map = event_dev->data->links_map;
303 /* Point links_map to this port specific area */
304 links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);
306 for (j = 0; j < dev->nb_event_queues; j++) {
307 if (links_map[j] == 0xdead)
313 link_fn(dev, event_dev->data->ports[i], hwgrp, nb_hwgrp);
318 cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)
320 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
321 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
325 deq_tmo_ns = conf->dequeue_timeout_ns;
328 deq_tmo_ns = dev->min_dequeue_timeout_ns;
329 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
330 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
331 plt_err("Unsupported dequeue timeout requested");
335 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
336 dev->is_timeout_deq = 1;
338 dev->deq_tmo_ns = deq_tmo_ns;
340 if (!conf->nb_event_queues || !conf->nb_event_ports ||
341 conf->nb_event_ports > dev->max_event_ports ||
342 conf->nb_event_queues > dev->max_event_queues) {
343 plt_err("Unsupported event queues/ports requested");
347 if (conf->nb_event_port_dequeue_depth > 1) {
348 plt_err("Unsupported event port deq depth requested");
352 if (conf->nb_event_port_enqueue_depth > 1) {
353 plt_err("Unsupported event port enq depth requested");
358 rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
360 plt_err("Failed to release XAQ %d", rc);
363 rte_mempool_free(dev->xaq_pool);
364 dev->xaq_pool = NULL;
367 dev->nb_event_queues = conf->nb_event_queues;
368 dev->nb_event_ports = conf->nb_event_ports;
374 cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
375 struct rte_event_queue_conf *queue_conf)
377 RTE_SET_USED(event_dev);
378 RTE_SET_USED(queue_id);
380 queue_conf->nb_atomic_flows = (1ULL << 20);
381 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
382 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
383 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
387 cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
388 const struct rte_event_queue_conf *queue_conf)
390 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
392 plt_sso_dbg("Queue=%d prio=%d", queue_id, queue_conf->priority);
393 /* Normalize <0-255> to <0-7> */
394 return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, 0xFF, 0xFF,
395 queue_conf->priority / 32);
399 cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
401 RTE_SET_USED(event_dev);
402 RTE_SET_USED(queue_id);
406 cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
407 struct rte_event_port_conf *port_conf)
409 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
411 RTE_SET_USED(port_id);
412 port_conf->new_event_threshold = dev->max_num_events;
413 port_conf->dequeue_depth = 1;
414 port_conf->enqueue_depth = 1;
418 cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
419 cnxk_sso_hws_setup_t hws_setup_fn)
421 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
422 uintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0};
425 plt_sso_dbg("Port=%d", port_id);
426 if (event_dev->data->ports[port_id] == NULL) {
427 plt_err("Invalid port Id %d", port_id);
431 for (q = 0; q < dev->nb_event_queues; q++) {
432 grps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q);
433 if (grps_base[q] == 0) {
434 plt_err("Failed to get grp[%d] base addr", q);
439 hws_setup_fn(dev, event_dev->data->ports[port_id], grps_base);
440 plt_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
447 cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
450 RTE_SET_USED(event_dev);
451 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
457 cnxk_sso_dump(struct rte_eventdev *event_dev, FILE *f)
459 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
461 roc_sso_dump(&dev->sso, dev->sso.nb_hws, dev->sso.nb_hwgrp, f);
465 cnxk_handle_event(void *arg, struct rte_event event)
467 struct rte_eventdev *event_dev = arg;
469 if (event_dev->dev_ops->dev_stop_flush != NULL)
470 event_dev->dev_ops->dev_stop_flush(
471 event_dev->data->dev_id, event,
472 event_dev->data->dev_stop_flush_arg);
476 cnxk_sso_cleanup(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn,
477 cnxk_sso_hws_flush_t flush_fn, uint8_t enable)
479 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
480 uintptr_t hwgrp_base;
484 for (i = 0; i < dev->nb_event_ports; i++) {
485 ws = event_dev->data->ports[i];
490 ws = event_dev->data->ports[0];
492 for (i = 0; i < dev->nb_event_queues; i++) {
493 /* Consume all the events through HWS0 */
494 hwgrp_base = roc_sso_hwgrp_base_get(&dev->sso, i);
495 flush_fn(ws, i, hwgrp_base, cnxk_handle_event, event_dev);
496 /* Enable/Disable SSO GGRP */
497 plt_write64(enable, hwgrp_base + SSO_LF_GGRP_QCTL);
502 cnxk_sso_start(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn,
503 cnxk_sso_hws_flush_t flush_fn)
505 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
506 struct roc_sso_hwgrp_qos qos[dev->qos_queue_cnt];
510 for (i = 0; i < dev->qos_queue_cnt; i++) {
511 qos->hwgrp = dev->qos_parse_data[i].queue;
512 qos->iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
513 qos->taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
514 qos->xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
516 rc = roc_sso_hwgrp_qos_config(&dev->sso, qos, dev->qos_queue_cnt,
519 plt_sso_dbg("failed to configure HWGRP QoS rc = %d", rc);
522 cnxk_sso_cleanup(event_dev, reset_fn, flush_fn, true);
529 cnxk_sso_stop(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn,
530 cnxk_sso_hws_flush_t flush_fn)
533 cnxk_sso_cleanup(event_dev, reset_fn, flush_fn, false);
538 cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn)
540 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
541 uint16_t all_queues[CNXK_SSO_MAX_HWGRP];
545 if (!dev->configured)
548 for (i = 0; i < dev->nb_event_queues; i++)
551 for (i = 0; i < dev->nb_event_ports; i++) {
552 ws = event_dev->data->ports[i];
553 unlink_fn(dev, ws, all_queues, dev->nb_event_queues);
554 rte_free(cnxk_sso_hws_get_cookie(ws));
555 event_dev->data->ports[i] = NULL;
558 roc_sso_rsrc_fini(&dev->sso);
559 rte_mempool_free(dev->xaq_pool);
560 rte_memzone_free(rte_memzone_lookup(CNXK_SSO_FC_NAME));
564 dev->xaq_pool = NULL;
565 dev->configured = false;
566 dev->is_timeout_deq = 0;
567 dev->nb_event_ports = 0;
568 dev->max_num_events = -1;
569 dev->nb_event_queues = 0;
570 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
571 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
577 parse_queue_param(char *value, void *opaque)
579 struct cnxk_sso_qos queue_qos = {0};
580 uint8_t *val = (uint8_t *)&queue_qos;
581 struct cnxk_sso_evdev *dev = opaque;
582 char *tok = strtok(value, "-");
583 struct cnxk_sso_qos *old_ptr;
588 while (tok != NULL) {
590 tok = strtok(NULL, "-");
594 if (val != (&queue_qos.iaq_prcnt + 1)) {
595 plt_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
599 dev->qos_queue_cnt++;
600 old_ptr = dev->qos_parse_data;
601 dev->qos_parse_data = rte_realloc(
603 sizeof(struct cnxk_sso_qos) * dev->qos_queue_cnt, 0);
604 if (dev->qos_parse_data == NULL) {
605 dev->qos_parse_data = old_ptr;
606 dev->qos_queue_cnt--;
609 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
613 parse_qos_list(const char *value, void *opaque)
615 char *s = strdup(value);
626 if (start && start < end) {
628 parse_queue_param(start + 1, opaque);
639 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
643 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
644 * isn't allowed. Everything is expressed in percentages, 0 represents
647 parse_qos_list(value, opaque);
653 cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)
655 struct rte_kvargs *kvlist;
656 uint8_t single_ws = 0;
660 kvlist = rte_kvargs_parse(devargs->args, NULL);
664 rte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value,
666 rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
668 rte_kvargs_process(kvlist, CNXK_SSO_FORCE_BP, &parse_kvargs_value,
670 rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value,
672 rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value,
674 dev->dual_ws = !single_ws;
675 rte_kvargs_free(kvlist);
679 cnxk_sso_init(struct rte_eventdev *event_dev)
681 const struct rte_memzone *mz = NULL;
682 struct rte_pci_device *pci_dev;
683 struct cnxk_sso_evdev *dev;
686 mz = rte_memzone_reserve(CNXK_SSO_MZ_NAME, sizeof(uint64_t),
689 plt_err("Failed to create eventdev memzone");
693 dev = cnxk_sso_pmd_priv(event_dev);
694 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
695 dev->sso.pci_dev = pci_dev;
697 *(uint64_t *)mz->addr = (uint64_t)dev;
698 cnxk_sso_parse_devargs(dev, pci_dev->device.devargs);
700 /* Initialize the base cnxk_dev object */
701 rc = roc_sso_dev_init(&dev->sso);
703 plt_err("Failed to initialize RoC SSO rc=%d", rc);
707 dev->is_timeout_deq = 0;
708 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
709 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
710 dev->max_num_events = -1;
711 dev->nb_event_queues = 0;
712 dev->nb_event_ports = 0;
714 cnxk_tim_init(&dev->sso);
719 rte_memzone_free(mz);
724 cnxk_sso_fini(struct rte_eventdev *event_dev)
726 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
728 /* For secondary processes, nothing to be done */
729 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
733 roc_sso_rsrc_fini(&dev->sso);
734 roc_sso_dev_fini(&dev->sso);
740 cnxk_sso_remove(struct rte_pci_device *pci_dev)
742 return rte_event_pmd_pci_remove(pci_dev, cnxk_sso_fini);