1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cnxk_eventdev.h"
8 cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
9 struct rte_event_dev_info *dev_info)
12 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
13 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
14 dev_info->max_event_queues = dev->max_event_queues;
15 dev_info->max_event_queue_flows = (1ULL << 20);
16 dev_info->max_event_queue_priority_levels = 8;
17 dev_info->max_event_priority_levels = 1;
18 dev_info->max_event_ports = dev->max_event_ports;
19 dev_info->max_event_port_dequeue_depth = 1;
20 dev_info->max_event_port_enqueue_depth = 1;
21 dev_info->max_num_events = dev->max_num_events;
22 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
23 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
24 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
25 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
26 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
27 RTE_EVENT_DEV_CAP_NONSEQ_MODE |
28 RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;
32 cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)
34 char pool_name[RTE_MEMZONE_NAMESIZE];
35 uint32_t xaq_cnt, npa_aura_id;
36 const struct rte_memzone *mz;
37 struct npa_aura_s *aura;
38 static int reconfig_cnt;
42 rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
44 plt_err("Failed to release XAQ %d", rc);
47 rte_mempool_free(dev->xaq_pool);
52 * Allocate memory for Add work backpressure.
54 mz = rte_memzone_lookup(CNXK_SSO_FC_NAME);
56 mz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME,
57 sizeof(struct npa_aura_s) +
59 0, 0, RTE_CACHE_LINE_SIZE);
61 plt_err("Failed to allocate mem for fcmem");
65 dev->fc_iova = mz->iova;
66 dev->fc_mem = mz->addr;
68 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem +
70 memset(aura, 0, sizeof(struct npa_aura_s));
73 aura->fc_addr = dev->fc_iova;
74 aura->fc_hyst_bits = 0; /* Store count on all updates */
76 /* Taken from HRM 14.3.3(4) */
77 xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;
79 xaq_cnt += dev->xae_cnt / dev->sso.xae_waes;
81 xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +
82 (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);
84 plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
85 /* Setup XAQ based on number of nb queues. */
86 snprintf(pool_name, 30, "cnxk_xaq_buf_pool_%d", reconfig_cnt);
87 dev->xaq_pool = (void *)rte_mempool_create_empty(
88 pool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0,
91 if (dev->xaq_pool == NULL) {
92 plt_err("Unable to create empty mempool.");
97 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
98 rte_mbuf_platform_mempool_ops(), aura);
100 plt_err("Unable to set xaqpool ops.");
104 rc = rte_mempool_populate_default(dev->xaq_pool);
106 plt_err("Unable to set populate xaqpool.");
110 /* When SW does addwork (enqueue) check if there is space in XAQ by
111 * comparing fc_addr above against the xaq_lmt calculated below.
112 * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO
113 * to request XAQ to cache them even before enqueue is called.
116 xaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues);
117 dev->nb_xaq_cfg = xaq_cnt;
119 npa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id);
120 return roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id,
121 dev->nb_event_queues);
123 rte_mempool_free(dev->xaq_pool);
124 rte_memzone_free(mz);
129 cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
130 cnxk_sso_init_hws_mem_t init_hws_fn,
131 cnxk_sso_hws_setup_t setup_hws_fn)
133 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
136 for (i = 0; i < dev->nb_event_ports; i++) {
137 struct cnxk_sso_hws_cookie *ws_cookie;
140 /* Free memory prior to re-allocation if needed */
141 if (event_dev->data->ports[i] != NULL)
142 ws = event_dev->data->ports[i];
144 ws = init_hws_fn(dev, i);
147 ws_cookie = cnxk_sso_hws_get_cookie(ws);
148 ws_cookie->event_dev = event_dev;
149 ws_cookie->configured = 1;
150 event_dev->data->ports[i] = ws;
151 cnxk_sso_port_setup((struct rte_eventdev *)(uintptr_t)event_dev,
157 for (i = i - 1; i >= 0; i--) {
158 event_dev->data->ports[i] = NULL;
159 rte_free(cnxk_sso_hws_get_cookie(event_dev->data->ports[i]));
165 cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)
167 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
168 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
172 deq_tmo_ns = conf->dequeue_timeout_ns;
175 deq_tmo_ns = dev->min_dequeue_timeout_ns;
176 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
177 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
178 plt_err("Unsupported dequeue timeout requested");
182 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
183 dev->is_timeout_deq = 1;
185 dev->deq_tmo_ns = deq_tmo_ns;
187 if (!conf->nb_event_queues || !conf->nb_event_ports ||
188 conf->nb_event_ports > dev->max_event_ports ||
189 conf->nb_event_queues > dev->max_event_queues) {
190 plt_err("Unsupported event queues/ports requested");
194 if (conf->nb_event_port_dequeue_depth > 1) {
195 plt_err("Unsupported event port deq depth requested");
199 if (conf->nb_event_port_enqueue_depth > 1) {
200 plt_err("Unsupported event port enq depth requested");
205 rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);
207 plt_err("Failed to release XAQ %d", rc);
210 rte_mempool_free(dev->xaq_pool);
211 dev->xaq_pool = NULL;
214 dev->nb_event_queues = conf->nb_event_queues;
215 dev->nb_event_ports = conf->nb_event_ports;
221 cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
222 struct rte_event_queue_conf *queue_conf)
224 RTE_SET_USED(event_dev);
225 RTE_SET_USED(queue_id);
227 queue_conf->nb_atomic_flows = (1ULL << 20);
228 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
229 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
230 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
234 cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
235 const struct rte_event_queue_conf *queue_conf)
237 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
239 plt_sso_dbg("Queue=%d prio=%d", queue_id, queue_conf->priority);
240 /* Normalize <0-255> to <0-7> */
241 return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, 0xFF, 0xFF,
242 queue_conf->priority / 32);
246 cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
248 RTE_SET_USED(event_dev);
249 RTE_SET_USED(queue_id);
253 cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
254 struct rte_event_port_conf *port_conf)
256 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
258 RTE_SET_USED(port_id);
259 port_conf->new_event_threshold = dev->max_num_events;
260 port_conf->dequeue_depth = 1;
261 port_conf->enqueue_depth = 1;
265 cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
266 cnxk_sso_hws_setup_t hws_setup_fn)
268 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
269 uintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0};
272 plt_sso_dbg("Port=%d", port_id);
273 if (event_dev->data->ports[port_id] == NULL) {
274 plt_err("Invalid port Id %d", port_id);
278 for (q = 0; q < dev->nb_event_queues; q++) {
279 grps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q);
280 if (grps_base[q] == 0) {
281 plt_err("Failed to get grp[%d] base addr", q);
286 hws_setup_fn(dev, event_dev->data->ports[port_id], grps_base);
287 plt_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
294 parse_queue_param(char *value, void *opaque)
296 struct cnxk_sso_qos queue_qos = {0};
297 uint8_t *val = (uint8_t *)&queue_qos;
298 struct cnxk_sso_evdev *dev = opaque;
299 char *tok = strtok(value, "-");
300 struct cnxk_sso_qos *old_ptr;
305 while (tok != NULL) {
307 tok = strtok(NULL, "-");
311 if (val != (&queue_qos.iaq_prcnt + 1)) {
312 plt_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
316 dev->qos_queue_cnt++;
317 old_ptr = dev->qos_parse_data;
318 dev->qos_parse_data = rte_realloc(
320 sizeof(struct cnxk_sso_qos) * dev->qos_queue_cnt, 0);
321 if (dev->qos_parse_data == NULL) {
322 dev->qos_parse_data = old_ptr;
323 dev->qos_queue_cnt--;
326 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
330 parse_qos_list(const char *value, void *opaque)
332 char *s = strdup(value);
343 if (start && start < end) {
345 parse_queue_param(start + 1, opaque);
356 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
360 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
361 * isn't allowed. Everything is expressed in percentages, 0 represents
364 parse_qos_list(value, opaque);
370 cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)
372 struct rte_kvargs *kvlist;
376 kvlist = rte_kvargs_parse(devargs->args, NULL);
380 rte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value,
382 rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
384 rte_kvargs_free(kvlist);
388 cnxk_sso_init(struct rte_eventdev *event_dev)
390 const struct rte_memzone *mz = NULL;
391 struct rte_pci_device *pci_dev;
392 struct cnxk_sso_evdev *dev;
395 mz = rte_memzone_reserve(CNXK_SSO_MZ_NAME, sizeof(uint64_t),
398 plt_err("Failed to create eventdev memzone");
402 dev = cnxk_sso_pmd_priv(event_dev);
403 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
404 dev->sso.pci_dev = pci_dev;
406 *(uint64_t *)mz->addr = (uint64_t)dev;
407 cnxk_sso_parse_devargs(dev, pci_dev->device.devargs);
409 /* Initialize the base cnxk_dev object */
410 rc = roc_sso_dev_init(&dev->sso);
412 plt_err("Failed to initialize RoC SSO rc=%d", rc);
416 dev->is_timeout_deq = 0;
417 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
418 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
419 dev->max_num_events = -1;
420 dev->nb_event_queues = 0;
421 dev->nb_event_ports = 0;
426 rte_memzone_free(mz);
431 cnxk_sso_fini(struct rte_eventdev *event_dev)
433 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
435 /* For secondary processes, nothing to be done */
436 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
439 roc_sso_rsrc_fini(&dev->sso);
440 roc_sso_dev_fini(&dev->sso);
446 cnxk_sso_remove(struct rte_pci_device *pci_dev)
448 return rte_event_pmd_pci_remove(pci_dev, cnxk_sso_fini);