drivers/event/cnxk/cnxk_eventdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_EVENTDEV_H__
   6 #define __CNXK_EVENTDEV_H__
   7
   8 #include <rte_devargs.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_mbuf_pool_ops.h>
  11 #include <rte_pci.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14
  15 #include "roc_api.h"
  16
  17 #define CNXK_SSO_XAE_CNT   "xae_cnt"
  18 #define CNXK_SSO_GGRP_QOS  "qos"
  19 #define CN9K_SSO_SINGLE_WS "single_ws"
  20 #define CN10K_SSO_GW_MODE  "gw_mode"
  21
  22 #define NSEC2USEC(__ns)         ((__ns) / 1E3)
  23 #define USEC2NSEC(__us)         ((__us)*1E3)
  24 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
  25
  26 #define CNXK_SSO_MAX_HWGRP     (RTE_EVENT_MAX_QUEUES_PER_DEV + 1)
  27 #define CNXK_SSO_FC_NAME       "cnxk_evdev_xaq_fc"
  28 #define CNXK_SSO_MZ_NAME       "cnxk_evdev_mz"
  29 #define CNXK_SSO_XAQ_CACHE_CNT (0x7)
  30 #define CNXK_SSO_XAQ_SLACK     (8)
  31
  32 #define CNXK_TT_FROM_TAG(x)         (((x) >> 32) & SSO_TT_EMPTY)
  33 #define CNXK_TT_FROM_EVENT(x)       (((x) >> 38) & SSO_TT_EMPTY)
  34 #define CNXK_EVENT_TYPE_FROM_TAG(x) (((x) >> 28) & 0xf)
  35 #define CNXK_SUB_EVENT_FROM_TAG(x)  (((x) >> 20) & 0xff)
  36 #define CNXK_CLR_SUB_EVENT(x)       (~(0xffu << 20) & x)
  37 #define CNXK_GRP_FROM_TAG(x)        (((x) >> 36) & 0x3ff)
  38 #define CNXK_SWTAG_PEND(x)          (BIT_ULL(62) & x)
  39
  40 #define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0)
  41
  42 #define CN10K_GW_MODE_NONE     0
  43 #define CN10K_GW_MODE_PREF     1
  44 #define CN10K_GW_MODE_PREF_WFE 2
  45
  46 typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);
  47 typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);
  48 typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);
  49 typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,
  50                                uint16_t nb_link);
  51
  52 struct cnxk_sso_qos {
  53         uint16_t queue;
  54         uint8_t xaq_prcnt;
  55         uint8_t taq_prcnt;
  56         uint8_t iaq_prcnt;
  57 };
  58
  59 struct cnxk_sso_evdev {
  60         struct roc_sso sso;
  61         uint8_t max_event_queues;
  62         uint8_t max_event_ports;
  63         uint8_t is_timeout_deq;
  64         uint8_t nb_event_queues;
  65         uint8_t nb_event_ports;
  66         uint8_t configured;
  67         uint32_t deq_tmo_ns;
  68         uint32_t min_dequeue_timeout_ns;
  69         uint32_t max_dequeue_timeout_ns;
  70         int32_t max_num_events;
  71         uint64_t *fc_mem;
  72         uint64_t xaq_lmt;
  73         uint64_t nb_xaq_cfg;
  74         rte_iova_t fc_iova;
  75         struct rte_mempool *xaq_pool;
  76         /* Dev args */
  77         uint32_t xae_cnt;
  78         uint8_t qos_queue_cnt;
  79         struct cnxk_sso_qos *qos_parse_data;
  80         /* CN9K */
  81         uint8_t dual_ws;
  82         /* CN10K */
  83         uint8_t gw_mode;
  84 } __rte_cache_aligned;
  85
  86 /* CN10K HWS ops */
  87 #define CN10K_SSO_HWS_OPS                                                      \
  88         uintptr_t swtag_desched_op;                                            \
  89         uintptr_t swtag_flush_op;                                              \
  90         uintptr_t swtag_untag_op;                                              \
  91         uintptr_t swtag_norm_op;                                               \
  92         uintptr_t updt_wqe_op;                                                 \
  93         uintptr_t tag_wqe_op;                                                  \
  94         uintptr_t getwrk_op
  95
  96 struct cn10k_sso_hws {
  97         /* Get Work Fastpath data */
  98         CN10K_SSO_HWS_OPS;
  99         uint32_t gw_wdata;
 100         uint8_t swtag_req;
 101         uint8_t hws_id;
 102         /* Add Work Fastpath data */
 103         uint64_t xaq_lmt __rte_cache_aligned;
 104         uint64_t *fc_mem;
 105         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 106         uint64_t base;
 107         uintptr_t lmt_base;
 108 } __rte_cache_aligned;
 109
 110 /* CN9K HWS ops */
 111 #define CN9K_SSO_HWS_OPS                                                       \
 112         uintptr_t swtag_desched_op;                                            \
 113         uintptr_t swtag_flush_op;                                              \
 114         uintptr_t swtag_norm_op;                                               \
 115         uintptr_t getwrk_op;                                                   \
 116         uintptr_t tag_op;                                                      \
 117         uintptr_t wqp_op
 118
 119 /* Event port a.k.a GWS */
 120 struct cn9k_sso_hws {
 121         /* Get Work Fastpath data */
 122         CN9K_SSO_HWS_OPS;
 123         uint8_t swtag_req;
 124         uint8_t hws_id;
 125         /* Add Work Fastpath data */
 126         uint64_t xaq_lmt __rte_cache_aligned;
 127         uint64_t *fc_mem;
 128         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 129         uint64_t base;
 130 } __rte_cache_aligned;
 131
 132 struct cn9k_sso_hws_state {
 133         CN9K_SSO_HWS_OPS;
 134 };
 135
 136 struct cn9k_sso_hws_dual {
 137         /* Get Work Fastpath data */
 138         struct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */
 139         uint8_t swtag_req;
 140         uint8_t vws; /* Ping pong bit */
 141         uint8_t hws_id;
 142         /* Add Work Fastpath data */
 143         uint64_t xaq_lmt __rte_cache_aligned;
 144         uint64_t *fc_mem;
 145         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 146         uint64_t base[2];
 147 } __rte_cache_aligned;
 148
 149 struct cnxk_sso_hws_cookie {
 150         const struct rte_eventdev *event_dev;
 151         bool configured;
 152 } __rte_cache_aligned;
 153
 154 static inline int
 155 parse_kvargs_value(const char *key, const char *value, void *opaque)
 156 {
 157         RTE_SET_USED(key);
 158
 159         *(uint32_t *)opaque = (uint32_t)atoi(value);
 160         return 0;
 161 }
 162
 163 static inline struct cnxk_sso_evdev *
 164 cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)
 165 {
 166         return event_dev->data->dev_private;
 167 }
 168
 169 static inline struct cnxk_sso_hws_cookie *
 170 cnxk_sso_hws_get_cookie(void *ws)
 171 {
 172         return RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie));
 173 }
 174
 175 /* Configuration functions */
 176 int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);
 177
 178 /* Common ops API. */
 179 int cnxk_sso_init(struct rte_eventdev *event_dev);
 180 int cnxk_sso_fini(struct rte_eventdev *event_dev);
 181 int cnxk_sso_remove(struct rte_pci_device *pci_dev);
 182 void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
 183                        struct rte_event_dev_info *dev_info);
 184 int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);
 185 int cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
 186                            cnxk_sso_init_hws_mem_t init_hws_mem,
 187                            cnxk_sso_hws_setup_t hws_setup);
 188 void cnxk_sso_restore_links(const struct rte_eventdev *event_dev,
 189                             cnxk_sso_link_t link_fn);
 190 void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
 191                              struct rte_event_queue_conf *queue_conf);
 192 int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
 193                          const struct rte_event_queue_conf *queue_conf);
 194 void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id);
 195 void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
 196                             struct rte_event_port_conf *port_conf);
 197 int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 198                         cnxk_sso_hws_setup_t hws_setup_fn);
 199 int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
 200                            uint64_t *tmo_ticks);
 201
 202 #endif /* __CNXK_EVENTDEV_H__ */