drivers/event/cnxk/cnxk_eventdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_EVENTDEV_H__
   6 #define __CNXK_EVENTDEV_H__
   7
   8 #include <rte_devargs.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_mbuf_pool_ops.h>
  11 #include <rte_pci.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14
  15 #include "roc_api.h"
  16
  17 #define CNXK_SSO_XAE_CNT  "xae_cnt"
  18 #define CNXK_SSO_GGRP_QOS "qos"
  19
  20 #define NSEC2USEC(__ns) ((__ns) / 1E3)
  21 #define USEC2NSEC(__us) ((__us)*1E3)
  22
  23 #define CNXK_SSO_MAX_HWGRP     (RTE_EVENT_MAX_QUEUES_PER_DEV + 1)
  24 #define CNXK_SSO_FC_NAME       "cnxk_evdev_xaq_fc"
  25 #define CNXK_SSO_MZ_NAME       "cnxk_evdev_mz"
  26 #define CNXK_SSO_XAQ_CACHE_CNT (0x7)
  27 #define CNXK_SSO_XAQ_SLACK     (8)
  28
  29 #define CN10K_GW_MODE_NONE     0
  30 #define CN10K_GW_MODE_PREF     1
  31 #define CN10K_GW_MODE_PREF_WFE 2
  32
  33 typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);
  34 typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);
  35 typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);
  36
  37 struct cnxk_sso_qos {
  38         uint16_t queue;
  39         uint8_t xaq_prcnt;
  40         uint8_t taq_prcnt;
  41         uint8_t iaq_prcnt;
  42 };
  43
  44 struct cnxk_sso_evdev {
  45         struct roc_sso sso;
  46         uint8_t max_event_queues;
  47         uint8_t max_event_ports;
  48         uint8_t is_timeout_deq;
  49         uint8_t nb_event_queues;
  50         uint8_t nb_event_ports;
  51         uint32_t deq_tmo_ns;
  52         uint32_t min_dequeue_timeout_ns;
  53         uint32_t max_dequeue_timeout_ns;
  54         int32_t max_num_events;
  55         uint64_t *fc_mem;
  56         uint64_t xaq_lmt;
  57         uint64_t nb_xaq_cfg;
  58         rte_iova_t fc_iova;
  59         struct rte_mempool *xaq_pool;
  60         /* Dev args */
  61         uint32_t xae_cnt;
  62         uint8_t qos_queue_cnt;
  63         struct cnxk_sso_qos *qos_parse_data;
  64         /* CN9K */
  65         uint8_t dual_ws;
  66         /* CN10K */
  67         uint8_t gw_mode;
  68 } __rte_cache_aligned;
  69
  70 /* CN10K HWS ops */
  71 #define CN10K_SSO_HWS_OPS                                                      \
  72         uintptr_t swtag_desched_op;                                            \
  73         uintptr_t swtag_flush_op;                                              \
  74         uintptr_t swtag_untag_op;                                              \
  75         uintptr_t swtag_norm_op;                                               \
  76         uintptr_t updt_wqe_op;                                                 \
  77         uintptr_t tag_wqe_op;                                                  \
  78         uintptr_t getwrk_op
  79
  80 struct cn10k_sso_hws {
  81         /* Get Work Fastpath data */
  82         CN10K_SSO_HWS_OPS;
  83         uint32_t gw_wdata;
  84         uint8_t swtag_req;
  85         uint8_t hws_id;
  86         /* Add Work Fastpath data */
  87         uint64_t xaq_lmt __rte_cache_aligned;
  88         uint64_t *fc_mem;
  89         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
  90         uint64_t base;
  91         uintptr_t lmt_base;
  92 } __rte_cache_aligned;
  93
  94 /* CN9K HWS ops */
  95 #define CN9K_SSO_HWS_OPS                                                       \
  96         uintptr_t swtag_desched_op;                                            \
  97         uintptr_t swtag_flush_op;                                              \
  98         uintptr_t swtag_norm_op;                                               \
  99         uintptr_t getwrk_op;                                                   \
 100         uintptr_t tag_op;                                                      \
 101         uintptr_t wqp_op
 102
 103 /* Event port a.k.a GWS */
 104 struct cn9k_sso_hws {
 105         /* Get Work Fastpath data */
 106         CN9K_SSO_HWS_OPS;
 107         uint8_t swtag_req;
 108         uint8_t hws_id;
 109         /* Add Work Fastpath data */
 110         uint64_t xaq_lmt __rte_cache_aligned;
 111         uint64_t *fc_mem;
 112         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 113         uint64_t base;
 114 } __rte_cache_aligned;
 115
 116 struct cn9k_sso_hws_state {
 117         CN9K_SSO_HWS_OPS;
 118 };
 119
 120 struct cn9k_sso_hws_dual {
 121         /* Get Work Fastpath data */
 122         struct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */
 123         uint8_t swtag_req;
 124         uint8_t vws; /* Ping pong bit */
 125         uint8_t hws_id;
 126         /* Add Work Fastpath data */
 127         uint64_t xaq_lmt __rte_cache_aligned;
 128         uint64_t *fc_mem;
 129         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 130         uint64_t base[2];
 131 } __rte_cache_aligned;
 132
 133 struct cnxk_sso_hws_cookie {
 134         const struct rte_eventdev *event_dev;
 135         bool configured;
 136 } __rte_cache_aligned;
 137
 138 static inline int
 139 parse_kvargs_value(const char *key, const char *value, void *opaque)
 140 {
 141         RTE_SET_USED(key);
 142
 143         *(uint32_t *)opaque = (uint32_t)atoi(value);
 144         return 0;
 145 }
 146
 147 static inline struct cnxk_sso_evdev *
 148 cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)
 149 {
 150         return event_dev->data->dev_private;
 151 }
 152
 153 static inline struct cnxk_sso_hws_cookie *
 154 cnxk_sso_hws_get_cookie(void *ws)
 155 {
 156         return RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie));
 157 }
 158
 159 /* Configuration functions */
 160 int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);
 161
 162 /* Common ops API. */
 163 int cnxk_sso_init(struct rte_eventdev *event_dev);
 164 int cnxk_sso_fini(struct rte_eventdev *event_dev);
 165 int cnxk_sso_remove(struct rte_pci_device *pci_dev);
 166 void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
 167                        struct rte_event_dev_info *dev_info);
 168 int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);
 169 int cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
 170                            cnxk_sso_init_hws_mem_t init_hws_mem,
 171                            cnxk_sso_hws_setup_t hws_setup);
 172 void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
 173                              struct rte_event_queue_conf *queue_conf);
 174 int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
 175                          const struct rte_event_queue_conf *queue_conf);
 176 void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id);
 177 void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
 178                             struct rte_event_port_conf *port_conf);
 179 int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 180                         cnxk_sso_hws_setup_t hws_setup_fn);
 181
 182 #endif /* __CNXK_EVENTDEV_H__ */