drivers/event/cnxk/cnxk_eventdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_EVENTDEV_H__
   6 #define __CNXK_EVENTDEV_H__
   7
   8 #include <rte_devargs.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_mbuf_pool_ops.h>
  11 #include <rte_pci.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14
  15 #include "roc_api.h"
  16
  17 #define CNXK_SSO_XAE_CNT  "xae_cnt"
  18 #define CNXK_SSO_GGRP_QOS "qos"
  19
  20 #define NSEC2USEC(__ns)         ((__ns) / 1E3)
  21 #define USEC2NSEC(__us)         ((__us)*1E3)
  22 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
  23
  24 #define CNXK_SSO_MAX_HWGRP     (RTE_EVENT_MAX_QUEUES_PER_DEV + 1)
  25 #define CNXK_SSO_FC_NAME       "cnxk_evdev_xaq_fc"
  26 #define CNXK_SSO_MZ_NAME       "cnxk_evdev_mz"
  27 #define CNXK_SSO_XAQ_CACHE_CNT (0x7)
  28 #define CNXK_SSO_XAQ_SLACK     (8)
  29
  30 #define CN10K_GW_MODE_NONE     0
  31 #define CN10K_GW_MODE_PREF     1
  32 #define CN10K_GW_MODE_PREF_WFE 2
  33
  34 typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);
  35 typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);
  36 typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);
  37 typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,
  38                                uint16_t nb_link);
  39
  40 struct cnxk_sso_qos {
  41         uint16_t queue;
  42         uint8_t xaq_prcnt;
  43         uint8_t taq_prcnt;
  44         uint8_t iaq_prcnt;
  45 };
  46
  47 struct cnxk_sso_evdev {
  48         struct roc_sso sso;
  49         uint8_t max_event_queues;
  50         uint8_t max_event_ports;
  51         uint8_t is_timeout_deq;
  52         uint8_t nb_event_queues;
  53         uint8_t nb_event_ports;
  54         uint8_t configured;
  55         uint32_t deq_tmo_ns;
  56         uint32_t min_dequeue_timeout_ns;
  57         uint32_t max_dequeue_timeout_ns;
  58         int32_t max_num_events;
  59         uint64_t *fc_mem;
  60         uint64_t xaq_lmt;
  61         uint64_t nb_xaq_cfg;
  62         rte_iova_t fc_iova;
  63         struct rte_mempool *xaq_pool;
  64         /* Dev args */
  65         uint32_t xae_cnt;
  66         uint8_t qos_queue_cnt;
  67         struct cnxk_sso_qos *qos_parse_data;
  68         /* CN9K */
  69         uint8_t dual_ws;
  70         /* CN10K */
  71         uint8_t gw_mode;
  72 } __rte_cache_aligned;
  73
  74 /* CN10K HWS ops */
  75 #define CN10K_SSO_HWS_OPS                                                      \
  76         uintptr_t swtag_desched_op;                                            \
  77         uintptr_t swtag_flush_op;                                              \
  78         uintptr_t swtag_untag_op;                                              \
  79         uintptr_t swtag_norm_op;                                               \
  80         uintptr_t updt_wqe_op;                                                 \
  81         uintptr_t tag_wqe_op;                                                  \
  82         uintptr_t getwrk_op
  83
  84 struct cn10k_sso_hws {
  85         /* Get Work Fastpath data */
  86         CN10K_SSO_HWS_OPS;
  87         uint32_t gw_wdata;
  88         uint8_t swtag_req;
  89         uint8_t hws_id;
  90         /* Add Work Fastpath data */
  91         uint64_t xaq_lmt __rte_cache_aligned;
  92         uint64_t *fc_mem;
  93         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
  94         uint64_t base;
  95         uintptr_t lmt_base;
  96 } __rte_cache_aligned;
  97
  98 /* CN9K HWS ops */
  99 #define CN9K_SSO_HWS_OPS                                                       \
 100         uintptr_t swtag_desched_op;                                            \
 101         uintptr_t swtag_flush_op;                                              \
 102         uintptr_t swtag_norm_op;                                               \
 103         uintptr_t getwrk_op;                                                   \
 104         uintptr_t tag_op;                                                      \
 105         uintptr_t wqp_op
 106
 107 /* Event port a.k.a GWS */
 108 struct cn9k_sso_hws {
 109         /* Get Work Fastpath data */
 110         CN9K_SSO_HWS_OPS;
 111         uint8_t swtag_req;
 112         uint8_t hws_id;
 113         /* Add Work Fastpath data */
 114         uint64_t xaq_lmt __rte_cache_aligned;
 115         uint64_t *fc_mem;
 116         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 117         uint64_t base;
 118 } __rte_cache_aligned;
 119
 120 struct cn9k_sso_hws_state {
 121         CN9K_SSO_HWS_OPS;
 122 };
 123
 124 struct cn9k_sso_hws_dual {
 125         /* Get Work Fastpath data */
 126         struct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */
 127         uint8_t swtag_req;
 128         uint8_t vws; /* Ping pong bit */
 129         uint8_t hws_id;
 130         /* Add Work Fastpath data */
 131         uint64_t xaq_lmt __rte_cache_aligned;
 132         uint64_t *fc_mem;
 133         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 134         uint64_t base[2];
 135 } __rte_cache_aligned;
 136
 137 struct cnxk_sso_hws_cookie {
 138         const struct rte_eventdev *event_dev;
 139         bool configured;
 140 } __rte_cache_aligned;
 141
 142 static inline int
 143 parse_kvargs_value(const char *key, const char *value, void *opaque)
 144 {
 145         RTE_SET_USED(key);
 146
 147         *(uint32_t *)opaque = (uint32_t)atoi(value);
 148         return 0;
 149 }
 150
 151 static inline struct cnxk_sso_evdev *
 152 cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)
 153 {
 154         return event_dev->data->dev_private;
 155 }
 156
 157 static inline struct cnxk_sso_hws_cookie *
 158 cnxk_sso_hws_get_cookie(void *ws)
 159 {
 160         return RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie));
 161 }
 162
 163 /* Configuration functions */
 164 int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);
 165
 166 /* Common ops API. */
 167 int cnxk_sso_init(struct rte_eventdev *event_dev);
 168 int cnxk_sso_fini(struct rte_eventdev *event_dev);
 169 int cnxk_sso_remove(struct rte_pci_device *pci_dev);
 170 void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
 171                        struct rte_event_dev_info *dev_info);
 172 int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);
 173 int cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
 174                            cnxk_sso_init_hws_mem_t init_hws_mem,
 175                            cnxk_sso_hws_setup_t hws_setup);
 176 void cnxk_sso_restore_links(const struct rte_eventdev *event_dev,
 177                             cnxk_sso_link_t link_fn);
 178 void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
 179                              struct rte_event_queue_conf *queue_conf);
 180 int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
 181                          const struct rte_event_queue_conf *queue_conf);
 182 void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id);
 183 void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
 184                             struct rte_event_port_conf *port_conf);
 185 int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 186                         cnxk_sso_hws_setup_t hws_setup_fn);
 187 int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
 188                            uint64_t *tmo_ticks);
 189
 190 #endif /* __CNXK_EVENTDEV_H__ */