drivers/event/cnxk/cnxk_eventdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_EVENTDEV_H__
   6 #define __CNXK_EVENTDEV_H__
   7
   8 #include <rte_devargs.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_mbuf_pool_ops.h>
  11 #include <rte_pci.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14
  15 #include "roc_api.h"
  16
  17 #include "cnxk_tim_evdev.h"
  18
  19 #define CNXK_SSO_XAE_CNT   "xae_cnt"
  20 #define CNXK_SSO_GGRP_QOS  "qos"
  21 #define CN9K_SSO_SINGLE_WS "single_ws"
  22 #define CN10K_SSO_GW_MODE  "gw_mode"
  23
  24 #define NSEC2USEC(__ns)         ((__ns) / 1E3)
  25 #define USEC2NSEC(__us)         ((__us)*1E3)
  26 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
  27
  28 #define CNXK_SSO_MAX_HWGRP     (RTE_EVENT_MAX_QUEUES_PER_DEV + 1)
  29 #define CNXK_SSO_FC_NAME       "cnxk_evdev_xaq_fc"
  30 #define CNXK_SSO_MZ_NAME       "cnxk_evdev_mz"
  31 #define CNXK_SSO_XAQ_CACHE_CNT (0x7)
  32 #define CNXK_SSO_XAQ_SLACK     (8)
  33
  34 #define CNXK_TT_FROM_TAG(x)         (((x) >> 32) & SSO_TT_EMPTY)
  35 #define CNXK_TT_FROM_EVENT(x)       (((x) >> 38) & SSO_TT_EMPTY)
  36 #define CNXK_EVENT_TYPE_FROM_TAG(x) (((x) >> 28) & 0xf)
  37 #define CNXK_SUB_EVENT_FROM_TAG(x)  (((x) >> 20) & 0xff)
  38 #define CNXK_CLR_SUB_EVENT(x)       (~(0xffu << 20) & x)
  39 #define CNXK_GRP_FROM_TAG(x)        (((x) >> 36) & 0x3ff)
  40 #define CNXK_SWTAG_PEND(x)          (BIT_ULL(62) & x)
  41
  42 #define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0)
  43
  44 #define CN10K_GW_MODE_NONE     0
  45 #define CN10K_GW_MODE_PREF     1
  46 #define CN10K_GW_MODE_PREF_WFE 2
  47
  48 typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);
  49 typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);
  50 typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);
  51 typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,
  52                                uint16_t nb_link);
  53 typedef int (*cnxk_sso_unlink_t)(void *dev, void *ws, uint16_t *map,
  54                                  uint16_t nb_link);
  55 typedef void (*cnxk_handle_event_t)(void *arg, struct rte_event ev);
  56 typedef void (*cnxk_sso_hws_reset_t)(void *arg, void *ws);
  57 typedef void (*cnxk_sso_hws_flush_t)(void *ws, uint8_t queue_id, uintptr_t base,
  58                                      cnxk_handle_event_t fn, void *arg);
  59
  60 struct cnxk_sso_qos {
  61         uint16_t queue;
  62         uint8_t xaq_prcnt;
  63         uint8_t taq_prcnt;
  64         uint8_t iaq_prcnt;
  65 };
  66
  67 struct cnxk_sso_evdev {
  68         struct roc_sso sso;
  69         uint8_t max_event_queues;
  70         uint8_t max_event_ports;
  71         uint8_t is_timeout_deq;
  72         uint8_t nb_event_queues;
  73         uint8_t nb_event_ports;
  74         uint8_t configured;
  75         uint32_t deq_tmo_ns;
  76         uint32_t min_dequeue_timeout_ns;
  77         uint32_t max_dequeue_timeout_ns;
  78         int32_t max_num_events;
  79         uint64_t *fc_mem;
  80         uint64_t xaq_lmt;
  81         uint64_t nb_xaq_cfg;
  82         rte_iova_t fc_iova;
  83         struct rte_mempool *xaq_pool;
  84         /* Dev args */
  85         uint32_t xae_cnt;
  86         uint8_t qos_queue_cnt;
  87         struct cnxk_sso_qos *qos_parse_data;
  88         /* CN9K */
  89         uint8_t dual_ws;
  90         /* CN10K */
  91         uint8_t gw_mode;
  92 } __rte_cache_aligned;
  93
  94 /* CN10K HWS ops */
  95 #define CN10K_SSO_HWS_OPS                                                      \
  96         uintptr_t swtag_desched_op;                                            \
  97         uintptr_t swtag_flush_op;                                              \
  98         uintptr_t swtag_untag_op;                                              \
  99         uintptr_t swtag_norm_op;                                               \
 100         uintptr_t updt_wqe_op;                                                 \
 101         uintptr_t tag_wqe_op;                                                  \
 102         uintptr_t getwrk_op
 103
 104 struct cn10k_sso_hws {
 105         /* Get Work Fastpath data */
 106         CN10K_SSO_HWS_OPS;
 107         uint32_t gw_wdata;
 108         uint8_t swtag_req;
 109         uint8_t hws_id;
 110         /* Add Work Fastpath data */
 111         uint64_t xaq_lmt __rte_cache_aligned;
 112         uint64_t *fc_mem;
 113         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 114         uint64_t base;
 115         uintptr_t lmt_base;
 116 } __rte_cache_aligned;
 117
 118 /* CN9K HWS ops */
 119 #define CN9K_SSO_HWS_OPS                                                       \
 120         uintptr_t swtag_desched_op;                                            \
 121         uintptr_t swtag_flush_op;                                              \
 122         uintptr_t swtag_norm_op;                                               \
 123         uintptr_t getwrk_op;                                                   \
 124         uintptr_t tag_op;                                                      \
 125         uintptr_t wqp_op
 126
 127 /* Event port a.k.a GWS */
 128 struct cn9k_sso_hws {
 129         /* Get Work Fastpath data */
 130         CN9K_SSO_HWS_OPS;
 131         uint8_t swtag_req;
 132         uint8_t hws_id;
 133         /* Add Work Fastpath data */
 134         uint64_t xaq_lmt __rte_cache_aligned;
 135         uint64_t *fc_mem;
 136         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 137         uint64_t base;
 138 } __rte_cache_aligned;
 139
 140 struct cn9k_sso_hws_state {
 141         CN9K_SSO_HWS_OPS;
 142 };
 143
 144 struct cn9k_sso_hws_dual {
 145         /* Get Work Fastpath data */
 146         struct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */
 147         uint8_t swtag_req;
 148         uint8_t vws; /* Ping pong bit */
 149         uint8_t hws_id;
 150         /* Add Work Fastpath data */
 151         uint64_t xaq_lmt __rte_cache_aligned;
 152         uint64_t *fc_mem;
 153         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 154         uint64_t base[2];
 155 } __rte_cache_aligned;
 156
 157 struct cnxk_sso_hws_cookie {
 158         const struct rte_eventdev *event_dev;
 159         bool configured;
 160 } __rte_cache_aligned;
 161
 162 static inline int
 163 parse_kvargs_value(const char *key, const char *value, void *opaque)
 164 {
 165         RTE_SET_USED(key);
 166
 167         *(uint32_t *)opaque = (uint32_t)atoi(value);
 168         return 0;
 169 }
 170
 171 static inline struct cnxk_sso_evdev *
 172 cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)
 173 {
 174         return event_dev->data->dev_private;
 175 }
 176
 177 static inline struct cnxk_sso_hws_cookie *
 178 cnxk_sso_hws_get_cookie(void *ws)
 179 {
 180         return RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie));
 181 }
 182
 183 /* Configuration functions */
 184 int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);
 185
 186 /* Common ops API. */
 187 int cnxk_sso_init(struct rte_eventdev *event_dev);
 188 int cnxk_sso_fini(struct rte_eventdev *event_dev);
 189 int cnxk_sso_remove(struct rte_pci_device *pci_dev);
 190 void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
 191                        struct rte_event_dev_info *dev_info);
 192 int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);
 193 int cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
 194                            cnxk_sso_init_hws_mem_t init_hws_mem,
 195                            cnxk_sso_hws_setup_t hws_setup);
 196 void cnxk_sso_restore_links(const struct rte_eventdev *event_dev,
 197                             cnxk_sso_link_t link_fn);
 198 void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
 199                              struct rte_event_queue_conf *queue_conf);
 200 int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
 201                          const struct rte_event_queue_conf *queue_conf);
 202 void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id);
 203 void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
 204                             struct rte_event_port_conf *port_conf);
 205 int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 206                         cnxk_sso_hws_setup_t hws_setup_fn);
 207 int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
 208                            uint64_t *tmo_ticks);
 209 int cnxk_sso_start(struct rte_eventdev *event_dev,
 210                    cnxk_sso_hws_reset_t reset_fn,
 211                    cnxk_sso_hws_flush_t flush_fn);
 212 void cnxk_sso_stop(struct rte_eventdev *event_dev,
 213                    cnxk_sso_hws_reset_t reset_fn,
 214                    cnxk_sso_hws_flush_t flush_fn);
 215 int cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn);
 216 int cnxk_sso_selftest(const char *dev_name);
 217 void cnxk_sso_dump(struct rte_eventdev *event_dev, FILE *f);
 218
 219 /* Stats API. */
 220 int cnxk_sso_xstats_get_names(const struct rte_eventdev *event_dev,
 221                               enum rte_event_dev_xstats_mode mode,
 222                               uint8_t queue_port_id,
 223                               struct rte_event_dev_xstats_name *xstats_names,
 224                               unsigned int *ids, unsigned int size);
 225 int cnxk_sso_xstats_get(const struct rte_eventdev *event_dev,
 226                         enum rte_event_dev_xstats_mode mode,
 227                         uint8_t queue_port_id, const unsigned int ids[],
 228                         uint64_t values[], unsigned int n);
 229 int cnxk_sso_xstats_reset(struct rte_eventdev *event_dev,
 230                           enum rte_event_dev_xstats_mode mode,
 231                           int16_t queue_port_id, const uint32_t ids[],
 232                           uint32_t n);
 233
 234 /* CN9K */
 235 void cn9k_sso_set_rsrc(void *arg);
 236
 237 #endif /* __CNXK_EVENTDEV_H__ */