1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cnxk_ethdev.h"
6 #include "cnxk_eventdev.h"
9 cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data,
15 case RTE_EVENT_TYPE_ETHDEV: {
16 struct cnxk_eth_rxq_sp *rxq = data;
19 for (i = 0; i < dev->rx_adptr_pool_cnt; i++) {
20 if ((uint64_t)rxq->qconf.mp == dev->rx_adptr_pools[i])
24 dev->rx_adptr_pool_cnt++;
25 old_ptr = dev->rx_adptr_pools;
26 dev->rx_adptr_pools = rte_realloc(
28 sizeof(uint64_t) * dev->rx_adptr_pool_cnt, 0);
29 if (dev->rx_adptr_pools == NULL) {
30 dev->adptr_xae_cnt += rxq->qconf.mp->size;
31 dev->rx_adptr_pools = old_ptr;
32 dev->rx_adptr_pool_cnt--;
35 dev->rx_adptr_pools[dev->rx_adptr_pool_cnt - 1] =
36 (uint64_t)rxq->qconf.mp;
38 dev->adptr_xae_cnt += rxq->qconf.mp->size;
41 case RTE_EVENT_TYPE_ETHDEV_VECTOR: {
42 struct rte_mempool *mp = data;
45 for (i = 0; i < dev->vec_pool_cnt; i++) {
46 if ((uint64_t)mp == dev->vec_pools[i])
51 old_ptr = dev->vec_pools;
53 rte_realloc(dev->vec_pools,
54 sizeof(uint64_t) * dev->vec_pool_cnt, 0);
55 if (dev->vec_pools == NULL) {
56 dev->adptr_xae_cnt += mp->size;
57 dev->vec_pools = old_ptr;
61 dev->vec_pools[dev->vec_pool_cnt - 1] = (uint64_t)mp;
63 dev->adptr_xae_cnt += mp->size;
66 case RTE_EVENT_TYPE_TIMER: {
67 struct cnxk_tim_ring *timr = data;
68 uint16_t *old_ring_ptr;
71 for (i = 0; i < dev->tim_adptr_ring_cnt; i++) {
72 if (timr->ring_id != dev->timer_adptr_rings[i])
74 if (timr->nb_timers == dev->timer_adptr_sz[i])
76 dev->adptr_xae_cnt -= dev->timer_adptr_sz[i];
77 dev->adptr_xae_cnt += timr->nb_timers;
78 dev->timer_adptr_sz[i] = timr->nb_timers;
83 dev->tim_adptr_ring_cnt++;
84 old_ring_ptr = dev->timer_adptr_rings;
85 old_sz_ptr = dev->timer_adptr_sz;
87 dev->timer_adptr_rings = rte_realloc(
88 dev->timer_adptr_rings,
89 sizeof(uint16_t) * dev->tim_adptr_ring_cnt, 0);
90 if (dev->timer_adptr_rings == NULL) {
91 dev->adptr_xae_cnt += timr->nb_timers;
92 dev->timer_adptr_rings = old_ring_ptr;
93 dev->tim_adptr_ring_cnt--;
97 dev->timer_adptr_sz = rte_realloc(
99 sizeof(uint64_t) * dev->tim_adptr_ring_cnt, 0);
101 if (dev->timer_adptr_sz == NULL) {
102 dev->adptr_xae_cnt += timr->nb_timers;
103 dev->timer_adptr_sz = old_sz_ptr;
104 dev->tim_adptr_ring_cnt--;
108 dev->timer_adptr_rings[dev->tim_adptr_ring_cnt - 1] =
110 dev->timer_adptr_sz[dev->tim_adptr_ring_cnt - 1] =
113 dev->adptr_xae_cnt += timr->nb_timers;
122 cnxk_sso_rxq_enable(struct cnxk_eth_dev *cnxk_eth_dev, uint16_t rq_id,
123 uint16_t port_id, const struct rte_event *ev,
124 uint8_t custom_flowid)
126 struct roc_nix *nix = &cnxk_eth_dev->nix;
127 struct roc_nix_rq *rq;
130 rq = &cnxk_eth_dev->rqs[rq_id];
132 rq->tt = ev->sched_type;
133 rq->hwgrp = ev->queue_id;
134 rq->flow_tag_width = 20;
136 rq->tag_mask = (port_id & 0xF) << 20;
137 rq->tag_mask |= (((port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV << 4))
141 rq->flow_tag_width = 0;
142 rq->tag_mask |= ev->flow_id;
145 rc = roc_nix_rq_modify(&cnxk_eth_dev->nix, rq, 0);
149 if (rq_id == 0 && roc_nix_inl_inb_is_enabled(nix)) {
150 uint32_t sec_tag_const;
152 /* IPSec tag const is 8-bit left shifted value of tag_mask
153 * as it applies to bit 32:8 of tag only.
155 sec_tag_const = rq->tag_mask >> 8;
156 rc = roc_nix_inl_inb_tag_update(nix, sec_tag_const,
159 plt_err("Failed to set tag conf for ipsec, rc=%d", rc);
166 cnxk_sso_rxq_disable(struct cnxk_eth_dev *cnxk_eth_dev, uint16_t rq_id)
168 struct roc_nix_rq *rq;
170 rq = &cnxk_eth_dev->rqs[rq_id];
172 rq->flow_tag_width = 32;
175 return roc_nix_rq_modify(&cnxk_eth_dev->nix, rq, 0);
179 cnxk_sso_rx_adapter_queue_add(
180 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
182 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
184 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
185 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
186 uint16_t port = eth_dev->data->port_id;
187 struct cnxk_eth_rxq_sp *rxq_sp;
190 if (rx_queue_id < 0) {
191 for (i = 0; i < eth_dev->data->nb_rx_queues; i++)
192 rc |= cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev,
195 rxq_sp = cnxk_eth_rxq_to_sp(
196 eth_dev->data->rx_queues[rx_queue_id]);
197 cnxk_sso_updt_xae_cnt(dev, rxq_sp, RTE_EVENT_TYPE_ETHDEV);
198 rc = cnxk_sso_xae_reconfigure(
199 (struct rte_eventdev *)(uintptr_t)event_dev);
200 rc |= cnxk_sso_rxq_enable(
201 cnxk_eth_dev, (uint16_t)rx_queue_id, port,
203 !!(queue_conf->rx_queue_flags &
204 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID));
205 rox_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,
206 rxq_sp->qconf.mp->pool_id, true,
208 cnxk_eth_dev->nb_rxq_sso++;
212 plt_err("Failed to configure Rx adapter port=%d, q=%d", port,
213 queue_conf->ev.queue_id);
217 dev->rx_offloads |= cnxk_eth_dev->rx_offload_flags;
219 /* Switch to use PF/VF's NIX LF instead of inline device for inbound
220 * when all the RQ's are switched to event dev mode. We do this only
221 * when using inline device is not forced by dev args.
223 if (!cnxk_eth_dev->inb.force_inl_dev &&
224 cnxk_eth_dev->nb_rxq_sso == cnxk_eth_dev->nb_rxq)
225 cnxk_nix_inb_mode_set(cnxk_eth_dev, false);
231 cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
232 const struct rte_eth_dev *eth_dev,
235 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
236 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
237 struct cnxk_eth_rxq_sp *rxq_sp;
240 RTE_SET_USED(event_dev);
241 if (rx_queue_id < 0) {
242 for (i = 0; i < eth_dev->data->nb_rx_queues; i++)
243 cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, i);
245 rxq_sp = cnxk_eth_rxq_to_sp(
246 eth_dev->data->rx_queues[rx_queue_id]);
247 rc = cnxk_sso_rxq_disable(cnxk_eth_dev, (uint16_t)rx_queue_id);
248 rox_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,
249 rxq_sp->qconf.mp->pool_id, false,
251 cnxk_eth_dev->nb_rxq_sso--;
255 plt_err("Failed to clear Rx adapter config port=%d, q=%d",
256 eth_dev->data->port_id, rx_queue_id);
258 /* Removing RQ from Rx adapter implies need to use
259 * inline device for CQ/Poll mode.
261 cnxk_nix_inb_mode_set(cnxk_eth_dev, true);
267 cnxk_sso_rx_adapter_start(const struct rte_eventdev *event_dev,
268 const struct rte_eth_dev *eth_dev)
270 RTE_SET_USED(event_dev);
271 RTE_SET_USED(eth_dev);
277 cnxk_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,
278 const struct rte_eth_dev *eth_dev)
280 RTE_SET_USED(event_dev);
281 RTE_SET_USED(eth_dev);
287 cnxk_sso_sqb_aura_limit_edit(struct roc_nix_sq *sq, uint16_t nb_sqb_bufs)
289 return roc_npa_aura_limit_modify(
290 sq->aura_handle, RTE_MIN(nb_sqb_bufs, sq->aura_sqb_bufs));
294 cnxk_sso_updt_tx_queue_data(const struct rte_eventdev *event_dev,
295 uint16_t eth_port_id, uint16_t tx_queue_id,
298 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
299 uint16_t max_port_id = dev->max_port_id;
300 uint64_t *txq_data = dev->tx_adptr_data;
302 if (txq_data == NULL || eth_port_id > max_port_id) {
303 max_port_id = RTE_MAX(max_port_id, eth_port_id);
304 txq_data = rte_realloc_socket(
306 (sizeof(uint64_t) * (max_port_id + 1) *
307 RTE_MAX_QUEUES_PER_PORT),
308 RTE_CACHE_LINE_SIZE, event_dev->data->socket_id);
309 if (txq_data == NULL)
313 ((uint64_t(*)[RTE_MAX_QUEUES_PER_PORT])
314 txq_data)[eth_port_id][tx_queue_id] = (uint64_t)txq;
315 dev->max_port_id = max_port_id;
316 dev->tx_adptr_data = txq_data;
321 cnxk_sso_tx_adapter_queue_add(const struct rte_eventdev *event_dev,
322 const struct rte_eth_dev *eth_dev,
325 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
326 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
327 struct roc_nix_sq *sq;
331 if (tx_queue_id < 0) {
332 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
333 cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, i);
335 txq = eth_dev->data->tx_queues[tx_queue_id];
336 sq = &cnxk_eth_dev->sqs[tx_queue_id];
337 cnxk_sso_sqb_aura_limit_edit(sq, CNXK_SSO_SQB_LIMIT);
338 ret = cnxk_sso_updt_tx_queue_data(
339 event_dev, eth_dev->data->port_id, tx_queue_id, txq);
343 dev->tx_offloads |= cnxk_eth_dev->tx_offload_flags;
350 cnxk_sso_tx_adapter_queue_del(const struct rte_eventdev *event_dev,
351 const struct rte_eth_dev *eth_dev,
354 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
355 struct roc_nix_sq *sq;
358 RTE_SET_USED(event_dev);
359 if (tx_queue_id < 0) {
360 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
361 cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, i);
363 sq = &cnxk_eth_dev->sqs[tx_queue_id];
364 cnxk_sso_sqb_aura_limit_edit(sq, sq->nb_sqb_bufs);
365 ret = cnxk_sso_updt_tx_queue_data(
366 event_dev, eth_dev->data->port_id, tx_queue_id, NULL);