drivers/event/cnxk/cnxk_tim_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cnxk_eventdev.h"
   6 #include "cnxk_tim_evdev.h"
   7
   8 static struct rte_event_timer_adapter_ops cnxk_tim_ops;
   9
  10 static int
  11 cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
  12                           struct rte_event_timer_adapter_conf *rcfg)
  13 {
  14         unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
  15         unsigned int mp_flags = 0;
  16         char pool_name[25];
  17         int rc;
  18
  19         cache_sz /= rte_lcore_count();
  20         /* Create chunk pool. */
  21         if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
  22                 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
  23                 plt_tim_dbg("Using single producer mode");
  24                 tim_ring->prod_type_sp = true;
  25         }
  26
  27         snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d",
  28                  tim_ring->ring_id);
  29
  30         if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
  31                 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
  32         cache_sz = cache_sz != 0 ? cache_sz : 2;
  33         tim_ring->nb_chunks += (cache_sz * rte_lcore_count());
  34         if (!tim_ring->disable_npa) {
  35                 tim_ring->chunk_pool = rte_mempool_create_empty(
  36                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  37                         cache_sz, 0, rte_socket_id(), mp_flags);
  38
  39                 if (tim_ring->chunk_pool == NULL) {
  40                         plt_err("Unable to create chunkpool.");
  41                         return -ENOMEM;
  42                 }
  43
  44                 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
  45                                                 rte_mbuf_platform_mempool_ops(),
  46                                                 NULL);
  47                 if (rc < 0) {
  48                         plt_err("Unable to set chunkpool ops");
  49                         goto free;
  50                 }
  51
  52                 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
  53                 if (rc < 0) {
  54                         plt_err("Unable to set populate chunkpool.");
  55                         goto free;
  56                 }
  57                 tim_ring->aura = roc_npa_aura_handle_to_aura(
  58                         tim_ring->chunk_pool->pool_id);
  59                 tim_ring->ena_dfb = 0;
  60         } else {
  61                 tim_ring->chunk_pool = rte_mempool_create(
  62                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  63                         cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(),
  64                         mp_flags);
  65                 if (tim_ring->chunk_pool == NULL) {
  66                         plt_err("Unable to create chunkpool.");
  67                         return -ENOMEM;
  68                 }
  69                 tim_ring->ena_dfb = 1;
  70         }
  71
  72         return 0;
  73
  74 free:
  75         rte_mempool_free(tim_ring->chunk_pool);
  76         return rc;
  77 }
  78
  79 static void
  80 cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)
  81 {
  82         uint8_t prod_flag = !tim_ring->prod_type_sp;
  83
  84         /* [STATS] [DFB/FB] [SP][MP]*/
  85         const rte_event_timer_arm_burst_t arm_burst[2][2][2] = {
  86 #define FP(_name, _f3, _f2, _f1, flags)                                        \
  87         [_f3][_f2][_f1] = cnxk_tim_arm_burst_##_name,
  88                 TIM_ARM_FASTPATH_MODES
  89 #undef FP
  90         };
  91
  92         const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = {
  93 #define FP(_name, _f2, _f1, flags)                                             \
  94         [_f2][_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,
  95                 TIM_ARM_TMO_FASTPATH_MODES
  96 #undef FP
  97         };
  98
  99         cnxk_tim_ops.arm_burst =
 100                 arm_burst[tim_ring->enable_stats][tim_ring->ena_dfb][prod_flag];
 101         cnxk_tim_ops.arm_tmo_tick_burst =
 102                 arm_tmo_burst[tim_ring->enable_stats][tim_ring->ena_dfb];
 103         cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst;
 104 }
 105
 106 static void
 107 cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
 108                        struct rte_event_timer_adapter_info *adptr_info)
 109 {
 110         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 111
 112         adptr_info->max_tmo_ns = tim_ring->max_tout;
 113         adptr_info->min_resolution_ns = tim_ring->tck_nsec;
 114         rte_memcpy(&adptr_info->conf, &adptr->data->conf,
 115                    sizeof(struct rte_event_timer_adapter_conf));
 116 }
 117
 118 static int
 119 cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
 120 {
 121         struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
 122         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 123         struct cnxk_tim_ring *tim_ring;
 124         int rc;
 125
 126         if (dev == NULL)
 127                 return -ENODEV;
 128
 129         if (adptr->data->id >= dev->nb_rings)
 130                 return -ENODEV;
 131
 132         tim_ring = rte_zmalloc("cnxk_tim_prv", sizeof(struct cnxk_tim_ring), 0);
 133         if (tim_ring == NULL)
 134                 return -ENOMEM;
 135
 136         rc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL);
 137         if (rc < 0) {
 138                 plt_err("Failed to create timer ring");
 139                 goto tim_ring_free;
 140         }
 141
 142         if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(
 143                               rcfg->timer_tick_ns,
 144                               cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),
 145                       cnxk_tim_cntfrq()) <
 146             cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {
 147                 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
 148                         rcfg->timer_tick_ns = TICK2NSEC(
 149                                 cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),
 150                                 cnxk_tim_cntfrq());
 151                 else {
 152                         rc = -ERANGE;
 153                         goto tim_hw_free;
 154                 }
 155         }
 156         tim_ring->ring_id = adptr->data->id;
 157         tim_ring->clk_src = (int)rcfg->clk_src;
 158         tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(
 159                 rcfg->timer_tick_ns,
 160                 cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));
 161         tim_ring->max_tout = rcfg->max_tmo_ns;
 162         tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
 163         tim_ring->nb_timers = rcfg->nb_timers;
 164         tim_ring->chunk_sz = dev->chunk_sz;
 165         tim_ring->disable_npa = dev->disable_npa;
 166         tim_ring->enable_stats = dev->enable_stats;
 167
 168         if (tim_ring->disable_npa) {
 169                 tim_ring->nb_chunks =
 170                         tim_ring->nb_timers /
 171                         CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 172                 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
 173         } else {
 174                 tim_ring->nb_chunks = tim_ring->nb_timers;
 175         }
 176
 177         tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 178         /* Create buckets. */
 179         tim_ring->bkt =
 180                 rte_zmalloc("cnxk_tim_bucket",
 181                             (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt),
 182                             RTE_CACHE_LINE_SIZE);
 183         if (tim_ring->bkt == NULL)
 184                 goto tim_hw_free;
 185
 186         rc = cnxk_tim_chnk_pool_create(tim_ring, rcfg);
 187         if (rc < 0)
 188                 goto tim_bkt_free;
 189
 190         rc = roc_tim_lf_config(
 191                 &dev->tim, tim_ring->ring_id,
 192                 cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,
 193                 tim_ring->nb_bkts, tim_ring->chunk_sz,
 194                 NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));
 195         if (rc < 0) {
 196                 plt_err("Failed to configure timer ring");
 197                 goto tim_chnk_free;
 198         }
 199
 200         tim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id);
 201         plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
 202         plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
 203
 204         /* Set fastpath ops. */
 205         cnxk_tim_set_fp_ops(tim_ring);
 206
 207         /* Update SSO xae count. */
 208         cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,
 209                               RTE_EVENT_TYPE_TIMER);
 210         cnxk_sso_xae_reconfigure(dev->event_dev);
 211
 212         plt_tim_dbg(
 213                 "Total memory used %" PRIu64 "MB\n",
 214                 (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +
 215                             (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) /
 216                            BIT_ULL(20)));
 217
 218         adptr->data->adapter_priv = tim_ring;
 219         return rc;
 220
 221 tim_chnk_free:
 222         rte_mempool_free(tim_ring->chunk_pool);
 223 tim_bkt_free:
 224         rte_free(tim_ring->bkt);
 225 tim_hw_free:
 226         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 227 tim_ring_free:
 228         rte_free(tim_ring);
 229         return rc;
 230 }
 231
 232 static int
 233 cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)
 234 {
 235         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 236         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 237
 238         if (dev == NULL)
 239                 return -ENODEV;
 240
 241         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 242         rte_free(tim_ring->bkt);
 243         rte_mempool_free(tim_ring->chunk_pool);
 244         rte_free(tim_ring);
 245
 246         return 0;
 247 }
 248
 249 static void
 250 cnxk_tim_calibrate_start_tsc(struct cnxk_tim_ring *tim_ring)
 251 {
 252 #define CNXK_TIM_CALIB_ITER 1E6
 253         uint32_t real_bkt, bucket;
 254         int icount, ecount = 0;
 255         uint64_t bkt_cyc;
 256
 257         for (icount = 0; icount < CNXK_TIM_CALIB_ITER; icount++) {
 258                 real_bkt = plt_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;
 259                 bkt_cyc = cnxk_tim_cntvct();
 260                 bucket = (bkt_cyc - tim_ring->ring_start_cyc) /
 261                          tim_ring->tck_int;
 262                 bucket = bucket % (tim_ring->nb_bkts);
 263                 tim_ring->ring_start_cyc =
 264                         bkt_cyc - (real_bkt * tim_ring->tck_int);
 265                 if (bucket != real_bkt)
 266                         ecount++;
 267         }
 268         tim_ring->last_updt_cyc = bkt_cyc;
 269         plt_tim_dbg("Bucket mispredict %3.2f distance %d\n",
 270                     100 - (((double)(icount - ecount) / (double)icount) * 100),
 271                     bucket - real_bkt);
 272 }
 273
 274 static int
 275 cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr)
 276 {
 277         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 278         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 279         int rc;
 280
 281         if (dev == NULL)
 282                 return -ENODEV;
 283
 284         rc = roc_tim_lf_enable(&dev->tim, tim_ring->ring_id,
 285                                &tim_ring->ring_start_cyc, NULL);
 286         if (rc < 0)
 287                 return rc;
 288
 289         tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq());
 290         tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts;
 291         tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int);
 292         tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts);
 293
 294         cnxk_tim_calibrate_start_tsc(tim_ring);
 295
 296         return rc;
 297 }
 298
 299 static int
 300 cnxk_tim_ring_stop(const struct rte_event_timer_adapter *adptr)
 301 {
 302         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 303         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 304         int rc;
 305
 306         if (dev == NULL)
 307                 return -ENODEV;
 308
 309         rc = roc_tim_lf_disable(&dev->tim, tim_ring->ring_id);
 310         if (rc < 0)
 311                 plt_err("Failed to disable timer ring");
 312
 313         return rc;
 314 }
 315
 316 static int
 317 cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter,
 318                    struct rte_event_timer_adapter_stats *stats)
 319 {
 320         struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv;
 321         uint64_t bkt_cyc = cnxk_tim_cntvct() - tim_ring->ring_start_cyc;
 322
 323         stats->evtim_exp_count =
 324                 __atomic_load_n(&tim_ring->arm_cnt, __ATOMIC_RELAXED);
 325         stats->ev_enq_count = stats->evtim_exp_count;
 326         stats->adapter_tick_count =
 327                 rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div);
 328         return 0;
 329 }
 330
 331 static int
 332 cnxk_tim_stats_reset(const struct rte_event_timer_adapter *adapter)
 333 {
 334         struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv;
 335
 336         __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED);
 337         return 0;
 338 }
 339
 340 int
 341 cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 342                   uint32_t *caps,
 343                   const struct rte_event_timer_adapter_ops **ops)
 344 {
 345         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 346
 347         RTE_SET_USED(flags);
 348
 349         if (dev == NULL)
 350                 return -ENODEV;
 351
 352         cnxk_tim_ops.init = cnxk_tim_ring_create;
 353         cnxk_tim_ops.uninit = cnxk_tim_ring_free;
 354         cnxk_tim_ops.start = cnxk_tim_ring_start;
 355         cnxk_tim_ops.stop = cnxk_tim_ring_stop;
 356         cnxk_tim_ops.get_info = cnxk_tim_ring_info_get;
 357
 358         if (dev->enable_stats) {
 359                 cnxk_tim_ops.stats_get = cnxk_tim_stats_get;
 360                 cnxk_tim_ops.stats_reset = cnxk_tim_stats_reset;
 361         }
 362
 363         /* Store evdev pointer for later use. */
 364         dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
 365         *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
 366         *ops = &cnxk_tim_ops;
 367
 368         return 0;
 369 }
 370
 371 static void
 372 cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)
 373 {
 374         struct rte_kvargs *kvlist;
 375
 376         if (devargs == NULL)
 377                 return;
 378
 379         kvlist = rte_kvargs_parse(devargs->args, NULL);
 380         if (kvlist == NULL)
 381                 return;
 382
 383         rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
 384                            &dev->disable_npa);
 385         rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
 386                            &dev->chunk_slots);
 387         rte_kvargs_process(kvlist, CNXK_TIM_STATS_ENA, &parse_kvargs_flag,
 388                            &dev->enable_stats);
 389         rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
 390                            &dev->min_ring_cnt);
 391
 392         rte_kvargs_free(kvlist);
 393 }
 394
 395 void
 396 cnxk_tim_init(struct roc_sso *sso)
 397 {
 398         const struct rte_memzone *mz;
 399         struct cnxk_tim_evdev *dev;
 400         int rc;
 401
 402         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 403                 return;
 404
 405         mz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME),
 406                                  sizeof(struct cnxk_tim_evdev), 0, 0);
 407         if (mz == NULL) {
 408                 plt_tim_dbg("Unable to allocate memory for TIM Event device");
 409                 return;
 410         }
 411         dev = mz->addr;
 412
 413         cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
 414
 415         dev->tim.roc_sso = sso;
 416         dev->tim.nb_lfs = dev->min_ring_cnt;
 417         rc = roc_tim_init(&dev->tim);
 418         if (rc < 0) {
 419                 plt_err("Failed to initialize roc tim resources");
 420                 rte_memzone_free(mz);
 421                 return;
 422         }
 423         dev->nb_rings = rc;
 424
 425         if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
 426             dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
 427                 dev->chunk_sz =
 428                         (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
 429         } else {
 430                 dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
 431         }
 432 }
 433
 434 void
 435 cnxk_tim_fini(void)
 436 {
 437         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 438
 439         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 440                 return;
 441
 442         roc_tim_fini(&dev->tim);
 443         rte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)));
 444 }