drivers/event/cnxk/cnxk_tim_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cnxk_eventdev.h"
   6 #include "cnxk_tim_evdev.h"
   7
   8 static struct rte_event_timer_adapter_ops cnxk_tim_ops;
   9
  10 static int
  11 cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
  12                           struct rte_event_timer_adapter_conf *rcfg)
  13 {
  14         unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
  15         unsigned int mp_flags = 0;
  16         char pool_name[25];
  17         int rc;
  18
  19         cache_sz /= rte_lcore_count();
  20         /* Create chunk pool. */
  21         if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
  22                 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
  23                 plt_tim_dbg("Using single producer mode");
  24                 tim_ring->prod_type_sp = true;
  25         }
  26
  27         snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d",
  28                  tim_ring->ring_id);
  29
  30         if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
  31                 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
  32         cache_sz = cache_sz != 0 ? cache_sz : 2;
  33         tim_ring->nb_chunks += (cache_sz * rte_lcore_count());
  34         if (!tim_ring->disable_npa) {
  35                 tim_ring->chunk_pool = rte_mempool_create_empty(
  36                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  37                         cache_sz, 0, rte_socket_id(), mp_flags);
  38
  39                 if (tim_ring->chunk_pool == NULL) {
  40                         plt_err("Unable to create chunkpool.");
  41                         return -ENOMEM;
  42                 }
  43
  44                 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
  45                                                 rte_mbuf_platform_mempool_ops(),
  46                                                 NULL);
  47                 if (rc < 0) {
  48                         plt_err("Unable to set chunkpool ops");
  49                         goto free;
  50                 }
  51
  52                 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
  53                 if (rc < 0) {
  54                         plt_err("Unable to set populate chunkpool.");
  55                         goto free;
  56                 }
  57                 tim_ring->aura = roc_npa_aura_handle_to_aura(
  58                         tim_ring->chunk_pool->pool_id);
  59                 tim_ring->ena_dfb = 0;
  60         } else {
  61                 tim_ring->chunk_pool = rte_mempool_create(
  62                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  63                         cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(),
  64                         mp_flags);
  65                 if (tim_ring->chunk_pool == NULL) {
  66                         plt_err("Unable to create chunkpool.");
  67                         return -ENOMEM;
  68                 }
  69                 tim_ring->ena_dfb = 1;
  70         }
  71
  72         return 0;
  73
  74 free:
  75         rte_mempool_free(tim_ring->chunk_pool);
  76         return rc;
  77 }
  78
  79 static void
  80 cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)
  81 {
  82         uint8_t prod_flag = !tim_ring->prod_type_sp;
  83
  84         /* [DFB/FB] [SP][MP]*/
  85         const rte_event_timer_arm_burst_t arm_burst[2][2] = {
  86 #define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name,
  87                 TIM_ARM_FASTPATH_MODES
  88 #undef FP
  89         };
  90
  91         const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = {
  92 #define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,
  93                 TIM_ARM_TMO_FASTPATH_MODES
  94 #undef FP
  95         };
  96
  97         cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag];
  98         cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb];
  99 }
 100
 101 static void
 102 cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
 103                        struct rte_event_timer_adapter_info *adptr_info)
 104 {
 105         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 106
 107         adptr_info->max_tmo_ns = tim_ring->max_tout;
 108         adptr_info->min_resolution_ns = tim_ring->tck_nsec;
 109         rte_memcpy(&adptr_info->conf, &adptr->data->conf,
 110                    sizeof(struct rte_event_timer_adapter_conf));
 111 }
 112
 113 static int
 114 cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
 115 {
 116         struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
 117         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 118         struct cnxk_tim_ring *tim_ring;
 119         int rc;
 120
 121         if (dev == NULL)
 122                 return -ENODEV;
 123
 124         if (adptr->data->id >= dev->nb_rings)
 125                 return -ENODEV;
 126
 127         tim_ring = rte_zmalloc("cnxk_tim_prv", sizeof(struct cnxk_tim_ring), 0);
 128         if (tim_ring == NULL)
 129                 return -ENOMEM;
 130
 131         rc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL);
 132         if (rc < 0) {
 133                 plt_err("Failed to create timer ring");
 134                 goto tim_ring_free;
 135         }
 136
 137         if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(
 138                               rcfg->timer_tick_ns,
 139                               cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),
 140                       cnxk_tim_cntfrq()) <
 141             cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {
 142                 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
 143                         rcfg->timer_tick_ns = TICK2NSEC(
 144                                 cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),
 145                                 cnxk_tim_cntfrq());
 146                 else {
 147                         rc = -ERANGE;
 148                         goto tim_hw_free;
 149                 }
 150         }
 151         tim_ring->ring_id = adptr->data->id;
 152         tim_ring->clk_src = (int)rcfg->clk_src;
 153         tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(
 154                 rcfg->timer_tick_ns,
 155                 cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));
 156         tim_ring->max_tout = rcfg->max_tmo_ns;
 157         tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
 158         tim_ring->nb_timers = rcfg->nb_timers;
 159         tim_ring->chunk_sz = dev->chunk_sz;
 160         tim_ring->disable_npa = dev->disable_npa;
 161
 162         if (tim_ring->disable_npa) {
 163                 tim_ring->nb_chunks =
 164                         tim_ring->nb_timers /
 165                         CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 166                 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
 167         } else {
 168                 tim_ring->nb_chunks = tim_ring->nb_timers;
 169         }
 170
 171         tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 172         /* Create buckets. */
 173         tim_ring->bkt =
 174                 rte_zmalloc("cnxk_tim_bucket",
 175                             (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt),
 176                             RTE_CACHE_LINE_SIZE);
 177         if (tim_ring->bkt == NULL)
 178                 goto tim_hw_free;
 179
 180         rc = cnxk_tim_chnk_pool_create(tim_ring, rcfg);
 181         if (rc < 0)
 182                 goto tim_bkt_free;
 183
 184         rc = roc_tim_lf_config(
 185                 &dev->tim, tim_ring->ring_id,
 186                 cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,
 187                 tim_ring->nb_bkts, tim_ring->chunk_sz,
 188                 NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));
 189         if (rc < 0) {
 190                 plt_err("Failed to configure timer ring");
 191                 goto tim_chnk_free;
 192         }
 193
 194         tim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id);
 195         plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
 196         plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
 197
 198         /* Set fastpath ops. */
 199         cnxk_tim_set_fp_ops(tim_ring);
 200
 201         /* Update SSO xae count. */
 202         cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,
 203                               RTE_EVENT_TYPE_TIMER);
 204         cnxk_sso_xae_reconfigure(dev->event_dev);
 205
 206         plt_tim_dbg(
 207                 "Total memory used %" PRIu64 "MB\n",
 208                 (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +
 209                             (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) /
 210                            BIT_ULL(20)));
 211
 212         adptr->data->adapter_priv = tim_ring;
 213         return rc;
 214
 215 tim_chnk_free:
 216         rte_mempool_free(tim_ring->chunk_pool);
 217 tim_bkt_free:
 218         rte_free(tim_ring->bkt);
 219 tim_hw_free:
 220         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 221 tim_ring_free:
 222         rte_free(tim_ring);
 223         return rc;
 224 }
 225
 226 static int
 227 cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)
 228 {
 229         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 230         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 231
 232         if (dev == NULL)
 233                 return -ENODEV;
 234
 235         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 236         rte_free(tim_ring->bkt);
 237         rte_mempool_free(tim_ring->chunk_pool);
 238         rte_free(tim_ring);
 239
 240         return 0;
 241 }
 242
 243 int
 244 cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 245                   uint32_t *caps,
 246                   const struct rte_event_timer_adapter_ops **ops)
 247 {
 248         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 249
 250         RTE_SET_USED(flags);
 251         RTE_SET_USED(ops);
 252
 253         if (dev == NULL)
 254                 return -ENODEV;
 255
 256         cnxk_tim_ops.init = cnxk_tim_ring_create;
 257         cnxk_tim_ops.uninit = cnxk_tim_ring_free;
 258         cnxk_tim_ops.get_info = cnxk_tim_ring_info_get;
 259
 260         /* Store evdev pointer for later use. */
 261         dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
 262         *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
 263
 264         return 0;
 265 }
 266
 267 static void
 268 cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)
 269 {
 270         struct rte_kvargs *kvlist;
 271
 272         if (devargs == NULL)
 273                 return;
 274
 275         kvlist = rte_kvargs_parse(devargs->args, NULL);
 276         if (kvlist == NULL)
 277                 return;
 278
 279         rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
 280                            &dev->disable_npa);
 281         rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
 282                            &dev->chunk_slots);
 283         rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
 284                            &dev->min_ring_cnt);
 285
 286         rte_kvargs_free(kvlist);
 287 }
 288
 289 void
 290 cnxk_tim_init(struct roc_sso *sso)
 291 {
 292         const struct rte_memzone *mz;
 293         struct cnxk_tim_evdev *dev;
 294         int rc;
 295
 296         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 297                 return;
 298
 299         mz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME),
 300                                  sizeof(struct cnxk_tim_evdev), 0, 0);
 301         if (mz == NULL) {
 302                 plt_tim_dbg("Unable to allocate memory for TIM Event device");
 303                 return;
 304         }
 305         dev = mz->addr;
 306
 307         cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
 308
 309         dev->tim.roc_sso = sso;
 310         dev->tim.nb_lfs = dev->min_ring_cnt;
 311         rc = roc_tim_init(&dev->tim);
 312         if (rc < 0) {
 313                 plt_err("Failed to initialize roc tim resources");
 314                 rte_memzone_free(mz);
 315                 return;
 316         }
 317         dev->nb_rings = rc;
 318
 319         if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
 320             dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
 321                 dev->chunk_sz =
 322                         (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
 323         } else {
 324                 dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
 325         }
 326 }
 327
 328 void
 329 cnxk_tim_fini(void)
 330 {
 331         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 332
 333         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 334                 return;
 335
 336         roc_tim_fini(&dev->tim);
 337         rte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)));
 338 }