drivers/event/cnxk/cnxk_tim_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cnxk_eventdev.h"
   6 #include "cnxk_tim_evdev.h"
   7
   8 static struct rte_event_timer_adapter_ops cnxk_tim_ops;
   9
  10 static int
  11 cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
  12                           struct rte_event_timer_adapter_conf *rcfg)
  13 {
  14         unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
  15         unsigned int mp_flags = 0;
  16         char pool_name[25];
  17         int rc;
  18
  19         cache_sz /= rte_lcore_count();
  20         /* Create chunk pool. */
  21         if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
  22                 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
  23                 plt_tim_dbg("Using single producer mode");
  24                 tim_ring->prod_type_sp = true;
  25         }
  26
  27         snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d",
  28                  tim_ring->ring_id);
  29
  30         if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
  31                 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
  32         cache_sz = cache_sz != 0 ? cache_sz : 2;
  33         tim_ring->nb_chunks += (cache_sz * rte_lcore_count());
  34         if (!tim_ring->disable_npa) {
  35                 tim_ring->chunk_pool = rte_mempool_create_empty(
  36                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  37                         cache_sz, 0, rte_socket_id(), mp_flags);
  38
  39                 if (tim_ring->chunk_pool == NULL) {
  40                         plt_err("Unable to create chunkpool.");
  41                         return -ENOMEM;
  42                 }
  43
  44                 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
  45                                                 rte_mbuf_platform_mempool_ops(),
  46                                                 NULL);
  47                 if (rc < 0) {
  48                         plt_err("Unable to set chunkpool ops");
  49                         goto free;
  50                 }
  51
  52                 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
  53                 if (rc < 0) {
  54                         plt_err("Unable to set populate chunkpool.");
  55                         goto free;
  56                 }
  57                 tim_ring->aura = roc_npa_aura_handle_to_aura(
  58                         tim_ring->chunk_pool->pool_id);
  59                 tim_ring->ena_dfb = 0;
  60         } else {
  61                 tim_ring->chunk_pool = rte_mempool_create(
  62                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  63                         cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(),
  64                         mp_flags);
  65                 if (tim_ring->chunk_pool == NULL) {
  66                         plt_err("Unable to create chunkpool.");
  67                         return -ENOMEM;
  68                 }
  69                 tim_ring->ena_dfb = 1;
  70         }
  71
  72         return 0;
  73
  74 free:
  75         rte_mempool_free(tim_ring->chunk_pool);
  76         return rc;
  77 }
  78
  79 static void
  80 cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)
  81 {
  82         uint8_t prod_flag = !tim_ring->prod_type_sp;
  83
  84         /* [DFB/FB] [SP][MP]*/
  85         const rte_event_timer_arm_burst_t arm_burst[2][2] = {
  86 #define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name,
  87                 TIM_ARM_FASTPATH_MODES
  88 #undef FP
  89         };
  90
  91         const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = {
  92 #define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,
  93                 TIM_ARM_TMO_FASTPATH_MODES
  94 #undef FP
  95         };
  96
  97         cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag];
  98         cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb];
  99         cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst;
 100 }
 101
 102 static void
 103 cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
 104                        struct rte_event_timer_adapter_info *adptr_info)
 105 {
 106         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 107
 108         adptr_info->max_tmo_ns = tim_ring->max_tout;
 109         adptr_info->min_resolution_ns = tim_ring->tck_nsec;
 110         rte_memcpy(&adptr_info->conf, &adptr->data->conf,
 111                    sizeof(struct rte_event_timer_adapter_conf));
 112 }
 113
 114 static int
 115 cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
 116 {
 117         struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
 118         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 119         struct cnxk_tim_ring *tim_ring;
 120         int rc;
 121
 122         if (dev == NULL)
 123                 return -ENODEV;
 124
 125         if (adptr->data->id >= dev->nb_rings)
 126                 return -ENODEV;
 127
 128         tim_ring = rte_zmalloc("cnxk_tim_prv", sizeof(struct cnxk_tim_ring), 0);
 129         if (tim_ring == NULL)
 130                 return -ENOMEM;
 131
 132         rc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL);
 133         if (rc < 0) {
 134                 plt_err("Failed to create timer ring");
 135                 goto tim_ring_free;
 136         }
 137
 138         if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(
 139                               rcfg->timer_tick_ns,
 140                               cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),
 141                       cnxk_tim_cntfrq()) <
 142             cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {
 143                 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
 144                         rcfg->timer_tick_ns = TICK2NSEC(
 145                                 cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),
 146                                 cnxk_tim_cntfrq());
 147                 else {
 148                         rc = -ERANGE;
 149                         goto tim_hw_free;
 150                 }
 151         }
 152         tim_ring->ring_id = adptr->data->id;
 153         tim_ring->clk_src = (int)rcfg->clk_src;
 154         tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(
 155                 rcfg->timer_tick_ns,
 156                 cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));
 157         tim_ring->max_tout = rcfg->max_tmo_ns;
 158         tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
 159         tim_ring->nb_timers = rcfg->nb_timers;
 160         tim_ring->chunk_sz = dev->chunk_sz;
 161         tim_ring->disable_npa = dev->disable_npa;
 162
 163         if (tim_ring->disable_npa) {
 164                 tim_ring->nb_chunks =
 165                         tim_ring->nb_timers /
 166                         CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 167                 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
 168         } else {
 169                 tim_ring->nb_chunks = tim_ring->nb_timers;
 170         }
 171
 172         tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 173         /* Create buckets. */
 174         tim_ring->bkt =
 175                 rte_zmalloc("cnxk_tim_bucket",
 176                             (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt),
 177                             RTE_CACHE_LINE_SIZE);
 178         if (tim_ring->bkt == NULL)
 179                 goto tim_hw_free;
 180
 181         rc = cnxk_tim_chnk_pool_create(tim_ring, rcfg);
 182         if (rc < 0)
 183                 goto tim_bkt_free;
 184
 185         rc = roc_tim_lf_config(
 186                 &dev->tim, tim_ring->ring_id,
 187                 cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,
 188                 tim_ring->nb_bkts, tim_ring->chunk_sz,
 189                 NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));
 190         if (rc < 0) {
 191                 plt_err("Failed to configure timer ring");
 192                 goto tim_chnk_free;
 193         }
 194
 195         tim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id);
 196         plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
 197         plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
 198
 199         /* Set fastpath ops. */
 200         cnxk_tim_set_fp_ops(tim_ring);
 201
 202         /* Update SSO xae count. */
 203         cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,
 204                               RTE_EVENT_TYPE_TIMER);
 205         cnxk_sso_xae_reconfigure(dev->event_dev);
 206
 207         plt_tim_dbg(
 208                 "Total memory used %" PRIu64 "MB\n",
 209                 (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +
 210                             (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) /
 211                            BIT_ULL(20)));
 212
 213         adptr->data->adapter_priv = tim_ring;
 214         return rc;
 215
 216 tim_chnk_free:
 217         rte_mempool_free(tim_ring->chunk_pool);
 218 tim_bkt_free:
 219         rte_free(tim_ring->bkt);
 220 tim_hw_free:
 221         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 222 tim_ring_free:
 223         rte_free(tim_ring);
 224         return rc;
 225 }
 226
 227 static int
 228 cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)
 229 {
 230         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 231         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 232
 233         if (dev == NULL)
 234                 return -ENODEV;
 235
 236         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 237         rte_free(tim_ring->bkt);
 238         rte_mempool_free(tim_ring->chunk_pool);
 239         rte_free(tim_ring);
 240
 241         return 0;
 242 }
 243
 244 int
 245 cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 246                   uint32_t *caps,
 247                   const struct rte_event_timer_adapter_ops **ops)
 248 {
 249         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 250
 251         RTE_SET_USED(flags);
 252         RTE_SET_USED(ops);
 253
 254         if (dev == NULL)
 255                 return -ENODEV;
 256
 257         cnxk_tim_ops.init = cnxk_tim_ring_create;
 258         cnxk_tim_ops.uninit = cnxk_tim_ring_free;
 259         cnxk_tim_ops.get_info = cnxk_tim_ring_info_get;
 260
 261         /* Store evdev pointer for later use. */
 262         dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
 263         *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
 264
 265         return 0;
 266 }
 267
 268 static void
 269 cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)
 270 {
 271         struct rte_kvargs *kvlist;
 272
 273         if (devargs == NULL)
 274                 return;
 275
 276         kvlist = rte_kvargs_parse(devargs->args, NULL);
 277         if (kvlist == NULL)
 278                 return;
 279
 280         rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
 281                            &dev->disable_npa);
 282         rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
 283                            &dev->chunk_slots);
 284         rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
 285                            &dev->min_ring_cnt);
 286
 287         rte_kvargs_free(kvlist);
 288 }
 289
 290 void
 291 cnxk_tim_init(struct roc_sso *sso)
 292 {
 293         const struct rte_memzone *mz;
 294         struct cnxk_tim_evdev *dev;
 295         int rc;
 296
 297         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 298                 return;
 299
 300         mz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME),
 301                                  sizeof(struct cnxk_tim_evdev), 0, 0);
 302         if (mz == NULL) {
 303                 plt_tim_dbg("Unable to allocate memory for TIM Event device");
 304                 return;
 305         }
 306         dev = mz->addr;
 307
 308         cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
 309
 310         dev->tim.roc_sso = sso;
 311         dev->tim.nb_lfs = dev->min_ring_cnt;
 312         rc = roc_tim_init(&dev->tim);
 313         if (rc < 0) {
 314                 plt_err("Failed to initialize roc tim resources");
 315                 rte_memzone_free(mz);
 316                 return;
 317         }
 318         dev->nb_rings = rc;
 319
 320         if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
 321             dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
 322                 dev->chunk_sz =
 323                         (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
 324         } else {
 325                 dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
 326         }
 327 }
 328
 329 void
 330 cnxk_tim_fini(void)
 331 {
 332         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 333
 334         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 335                 return;
 336
 337         roc_tim_fini(&dev->tim);
 338         rte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)));
 339 }