1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CNXK_TIM_EVDEV_H__
6 #define __CNXK_TIM_EVDEV_H__
13 #include <eventdev_pmd_pci.h>
14 #include <rte_event_timer_adapter.h>
15 #include <rte_malloc.h>
16 #include <rte_memzone.h>
20 #define NSECPERSEC 1E9
21 #define USECPERSEC 1E6
22 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
24 #define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev
25 #define CNXK_TIM_MAX_BUCKETS (0xFFFFF)
26 #define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)
27 #define CNXK_TIM_CHUNK_ALIGNMENT (16)
28 #define CNXK_TIM_MAX_BURST \
29 (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
30 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
31 #define CNXK_TIM_MIN_CHUNK_SLOTS (0x1)
32 #define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE)
34 #define CN9K_TIM_MIN_TMO_TKS (256)
36 #define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
38 struct cnxk_tim_evdev {
40 struct rte_eventdev *event_dev;
47 enum cnxk_tim_clk_src {
48 CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
49 CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
50 CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
51 CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
65 int16_t chunk_remainder;
68 uint64_t current_chunk;
72 struct cnxk_tim_ring {
74 uint16_t nb_chunk_slots;
78 struct cnxk_tim_bkt *bkt;
79 struct rte_mempool *chunk_pool;
91 enum cnxk_tim_clk_src clk_src;
92 } __rte_cache_aligned;
99 static inline struct cnxk_tim_evdev *
100 cnxk_tim_priv_get(void)
102 const struct rte_memzone *mz;
104 mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));
111 static inline uint64_t
112 cnxk_tim_min_tmo_ticks(uint64_t freq)
114 if (roc_model_runtime_is_cn9k())
115 return CN9K_TIM_MIN_TMO_TKS;
116 else /* CN10K min tick is of 1us */
117 return freq / USECPERSEC;
120 static inline uint64_t
121 cnxk_tim_min_resolution_ns(uint64_t freq)
123 return NSECPERSEC / freq;
126 static inline enum roc_tim_clk_src
127 cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
130 case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
131 return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
134 return ROC_TIM_CLK_SRC_INVALID;
138 #ifdef RTE_ARCH_ARM64
139 static inline uint64_t
140 cnxk_tim_cntvct(void)
144 asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
148 static inline uint64_t
149 cnxk_tim_cntfrq(void)
153 asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
157 static inline uint64_t
158 cnxk_tim_cntvct(void)
163 static inline uint64_t
164 cnxk_tim_cntfrq(void)
170 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
172 const struct rte_event_timer_adapter_ops **ops);
174 void cnxk_tim_init(struct roc_sso *sso);
175 void cnxk_tim_fini(void);
177 #endif /* __CNXK_TIM_EVDEV_H__ */