1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CNXK_TIM_EVDEV_H__
6 #define __CNXK_TIM_EVDEV_H__
13 #include <eventdev_pmd_pci.h>
14 #include <rte_event_timer_adapter.h>
15 #include <rte_malloc.h>
16 #include <rte_memzone.h>
17 #include <rte_reciprocal.h>
21 #define NSECPERSEC 1E9
22 #define USECPERSEC 1E6
23 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
25 #define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev
26 #define CNXK_TIM_MAX_BUCKETS (0xFFFFF)
27 #define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)
28 #define CNXK_TIM_CHUNK_ALIGNMENT (16)
29 #define CNXK_TIM_MAX_BURST \
30 (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
31 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
32 #define CNXK_TIM_MIN_CHUNK_SLOTS (0x1)
33 #define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE)
34 #define CNXK_TIM_MAX_POOL_CACHE_SZ (128)
36 #define CN9K_TIM_MIN_TMO_TKS (256)
38 #define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
39 #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots"
40 #define CNXK_TIM_STATS_ENA "tim_stats_ena"
41 #define CNXK_TIM_RINGS_LMT "tim_rings_lmt"
42 #define CNXK_TIM_RING_CTL "tim_ring_ctl"
43 #define CNXK_TIM_EXT_CLK "tim_eclk_freq"
45 #define CNXK_TIM_SP 0x1
46 #define CNXK_TIM_MP 0x2
47 #define CNXK_TIM_ENA_FB 0x10
48 #define CNXK_TIM_ENA_DFB 0x20
49 #define CNXK_TIM_ENA_STATS 0x40
51 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
52 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \
53 ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
54 #define TIM_BUCKET_W1_S_LOCK (40)
55 #define TIM_BUCKET_W1_M_LOCK \
56 ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1)
57 #define TIM_BUCKET_W1_S_RSVD (35)
58 #define TIM_BUCKET_W1_S_BSK (34)
59 #define TIM_BUCKET_W1_M_BSK \
60 ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1)
61 #define TIM_BUCKET_W1_S_HBT (33)
62 #define TIM_BUCKET_W1_M_HBT \
63 ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1)
64 #define TIM_BUCKET_W1_S_SBT (32)
65 #define TIM_BUCKET_W1_M_SBT \
66 ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1)
67 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
68 #define TIM_BUCKET_W1_M_NUM_ENTRIES \
69 ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
71 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
73 #define TIM_BUCKET_CHUNK_REMAIN \
74 (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
76 #define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
78 #define TIM_BUCKET_SEMA_WLOCK \
79 (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
85 uint16_t enable_stats;
88 struct cnxk_tim_evdev {
90 struct rte_eventdev *event_dev;
96 uint32_t min_ring_cnt;
98 uint16_t ring_ctl_cnt;
99 uint64_t ext_clk_freq[ROC_TIM_CLK_SRC_INVALID];
100 struct cnxk_tim_ctl *ring_ctl_data;
103 struct cnxk_tim_bkt {
104 uint64_t first_chunk;
114 int16_t chunk_remainder;
117 uint64_t current_chunk;
121 struct cnxk_tim_ring {
123 uint16_t nb_chunk_slots;
125 uint64_t last_updt_cyc;
126 uint64_t ring_start_cyc;
129 struct cnxk_tim_bkt *bkt;
130 struct rte_mempool *chunk_pool;
131 struct rte_reciprocal_u64 fast_div;
132 struct rte_reciprocal_u64 fast_bkt;
134 uint8_t prod_type_sp;
135 uint8_t enable_stats;
138 uint8_t ena_periodic;
146 enum roc_tim_clk_src clk_src;
147 } __rte_cache_aligned;
149 struct cnxk_tim_ent {
154 static inline struct cnxk_tim_evdev *
155 cnxk_tim_priv_get(void)
157 const struct rte_memzone *mz;
159 mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));
166 static inline long double
167 cnxk_tim_ns_per_tck(uint64_t freq)
169 return (long double)NSECPERSEC / freq;
172 #ifdef RTE_ARCH_ARM64
173 static inline uint64_t
174 cnxk_tim_cntvct(void)
178 asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
182 static inline uint64_t
183 cnxk_tim_cntfrq(void)
187 asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
191 static inline uint64_t
192 cnxk_tim_cntvct(void)
197 static inline uint64_t
198 cnxk_tim_cntfrq(void)
204 static inline enum roc_tim_clk_src
205 cnxk_tim_convert_clk_src(enum rte_event_timer_adapter_clk_src clk_src)
208 case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
209 return ROC_TIM_CLK_SRC_GTI;
210 case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0:
211 return ROC_TIM_CLK_SRC_10NS;
212 case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1:
213 return ROC_TIM_CLK_SRC_GPIO;
214 case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2:
215 return ROC_TIM_CLK_SRC_PTP;
216 case RTE_EVENT_TIMER_ADAPTER_EXT_CLK3:
217 return roc_model_constant_is_cn9k() ? ROC_TIM_CLK_SRC_INVALID :
218 ROC_TIM_CLK_SRC_SYNCE;
220 return ROC_TIM_CLK_SRC_INVALID;
225 cnxk_tim_get_clk_freq(struct cnxk_tim_evdev *dev, enum roc_tim_clk_src clk_src,
233 case ROC_TIM_CLK_SRC_GTI:
234 *freq = cnxk_tim_cntfrq();
236 case ROC_TIM_CLK_SRC_10NS:
239 case ROC_TIM_CLK_SRC_GPIO:
240 case ROC_TIM_CLK_SRC_PTP:
241 case ROC_TIM_CLK_SRC_SYNCE:
242 *freq = dev->ext_clk_freq[clk_src];
251 #define TIM_ARM_FASTPATH_MODES \
252 FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \
253 FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \
254 FP(fb_sp, 0, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \
255 FP(fb_mp, 0, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) \
256 FP(stats_sp, 1, 0, 0, \
257 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \
258 FP(stats_mp, 1, 0, 1, \
259 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \
260 FP(stats_fb_sp, 1, 1, 0, \
261 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_SP) \
262 FP(stats_fb_mp, 1, 1, 1, \
263 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_MP)
265 #define TIM_ARM_TMO_FASTPATH_MODES \
266 FP(dfb, 0, 0, CNXK_TIM_ENA_DFB) \
267 FP(fb, 0, 1, CNXK_TIM_ENA_FB) \
268 FP(stats_dfb, 1, 0, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB) \
269 FP(stats_fb, 1, 1, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB)
271 #define FP(_name, _f3, _f2, _f1, flags) \
272 uint16_t cnxk_tim_arm_burst_##_name( \
273 const struct rte_event_timer_adapter *adptr, \
274 struct rte_event_timer **tim, const uint16_t nb_timers);
275 TIM_ARM_FASTPATH_MODES
278 #define FP(_name, _f2, _f1, flags) \
279 uint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \
280 const struct rte_event_timer_adapter *adptr, \
281 struct rte_event_timer **tim, const uint64_t timeout_tick, \
282 const uint16_t nb_timers);
283 TIM_ARM_TMO_FASTPATH_MODES
287 cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,
288 struct rte_event_timer **tim,
289 const uint16_t nb_timers);
291 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
293 const struct event_timer_adapter_ops **ops);
295 void cnxk_tim_init(struct roc_sso *sso);
296 void cnxk_tim_fini(void);
298 #endif /* __CNXK_TIM_EVDEV_H__ */