1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CNXK_TIM_EVDEV_H__
6 #define __CNXK_TIM_EVDEV_H__
13 #include <eventdev_pmd_pci.h>
14 #include <rte_event_timer_adapter.h>
15 #include <rte_malloc.h>
16 #include <rte_memzone.h>
17 #include <rte_reciprocal.h>
21 #define NSECPERSEC 1E9
22 #define USECPERSEC 1E6
23 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
25 #define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev
26 #define CNXK_TIM_MAX_BUCKETS (0xFFFFF)
27 #define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)
28 #define CNXK_TIM_CHUNK_ALIGNMENT (16)
29 #define CNXK_TIM_MAX_BURST \
30 (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
31 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
32 #define CNXK_TIM_MIN_CHUNK_SLOTS (0x1)
33 #define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE)
35 #define CN9K_TIM_MIN_TMO_TKS (256)
37 #define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
38 #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots"
39 #define CNXK_TIM_STATS_ENA "tim_stats_ena"
40 #define CNXK_TIM_RINGS_LMT "tim_rings_lmt"
41 #define CNXK_TIM_RING_CTL "tim_ring_ctl"
43 #define CNXK_TIM_SP 0x1
44 #define CNXK_TIM_MP 0x2
45 #define CNXK_TIM_ENA_FB 0x10
46 #define CNXK_TIM_ENA_DFB 0x20
47 #define CNXK_TIM_ENA_STATS 0x40
49 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
50 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \
51 ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
52 #define TIM_BUCKET_W1_S_LOCK (40)
53 #define TIM_BUCKET_W1_M_LOCK \
54 ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1)
55 #define TIM_BUCKET_W1_S_RSVD (35)
56 #define TIM_BUCKET_W1_S_BSK (34)
57 #define TIM_BUCKET_W1_M_BSK \
58 ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1)
59 #define TIM_BUCKET_W1_S_HBT (33)
60 #define TIM_BUCKET_W1_M_HBT \
61 ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1)
62 #define TIM_BUCKET_W1_S_SBT (32)
63 #define TIM_BUCKET_W1_M_SBT \
64 ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1)
65 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
66 #define TIM_BUCKET_W1_M_NUM_ENTRIES \
67 ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
69 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
71 #define TIM_BUCKET_CHUNK_REMAIN \
72 (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
74 #define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
76 #define TIM_BUCKET_SEMA_WLOCK \
77 (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
83 uint16_t enable_stats;
86 struct cnxk_tim_evdev {
88 struct rte_eventdev *event_dev;
94 uint16_t min_ring_cnt;
96 uint16_t ring_ctl_cnt;
97 struct cnxk_tim_ctl *ring_ctl_data;
100 enum cnxk_tim_clk_src {
101 CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
102 CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
103 CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
104 CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
107 struct cnxk_tim_bkt {
108 uint64_t first_chunk;
118 int16_t chunk_remainder;
121 uint64_t current_chunk;
125 struct cnxk_tim_ring {
127 uint16_t nb_chunk_slots;
129 uint64_t last_updt_cyc;
130 uint64_t ring_start_cyc;
133 struct cnxk_tim_bkt *bkt;
134 struct rte_mempool *chunk_pool;
135 struct rte_reciprocal_u64 fast_div;
136 struct rte_reciprocal_u64 fast_bkt;
138 uint8_t prod_type_sp;
139 uint8_t enable_stats;
149 enum cnxk_tim_clk_src clk_src;
150 } __rte_cache_aligned;
152 struct cnxk_tim_ent {
157 static inline struct cnxk_tim_evdev *
158 cnxk_tim_priv_get(void)
160 const struct rte_memzone *mz;
162 mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));
169 static inline uint64_t
170 cnxk_tim_min_tmo_ticks(uint64_t freq)
172 if (roc_model_runtime_is_cn9k())
173 return CN9K_TIM_MIN_TMO_TKS;
174 else /* CN10K min tick is of 1us */
175 return freq / USECPERSEC;
178 static inline uint64_t
179 cnxk_tim_min_resolution_ns(uint64_t freq)
181 return NSECPERSEC / freq;
184 static inline enum roc_tim_clk_src
185 cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
188 case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
189 return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
192 return ROC_TIM_CLK_SRC_INVALID;
196 #ifdef RTE_ARCH_ARM64
197 static inline uint64_t
198 cnxk_tim_cntvct(void)
202 asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
206 static inline uint64_t
207 cnxk_tim_cntfrq(void)
211 asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
215 static inline uint64_t
216 cnxk_tim_cntvct(void)
221 static inline uint64_t
222 cnxk_tim_cntfrq(void)
228 #define TIM_ARM_FASTPATH_MODES \
229 FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \
230 FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \
231 FP(fb_sp, 0, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \
232 FP(fb_mp, 0, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) \
233 FP(stats_sp, 1, 0, 0, \
234 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \
235 FP(stats_mp, 1, 0, 1, \
236 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \
237 FP(stats_fb_sp, 1, 1, 0, \
238 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_SP) \
239 FP(stats_fb_mp, 1, 1, 1, \
240 CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_MP)
242 #define TIM_ARM_TMO_FASTPATH_MODES \
243 FP(dfb, 0, 0, CNXK_TIM_ENA_DFB) \
244 FP(fb, 0, 1, CNXK_TIM_ENA_FB) \
245 FP(stats_dfb, 1, 0, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB) \
246 FP(stats_fb, 1, 1, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB)
248 #define FP(_name, _f3, _f2, _f1, flags) \
249 uint16_t cnxk_tim_arm_burst_##_name( \
250 const struct rte_event_timer_adapter *adptr, \
251 struct rte_event_timer **tim, const uint16_t nb_timers);
252 TIM_ARM_FASTPATH_MODES
255 #define FP(_name, _f2, _f1, flags) \
256 uint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \
257 const struct rte_event_timer_adapter *adptr, \
258 struct rte_event_timer **tim, const uint64_t timeout_tick, \
259 const uint16_t nb_timers);
260 TIM_ARM_TMO_FASTPATH_MODES
264 cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,
265 struct rte_event_timer **tim,
266 const uint16_t nb_timers);
268 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
270 const struct rte_event_timer_adapter_ops **ops);
272 void cnxk_tim_init(struct roc_sso *sso);
273 void cnxk_tim_fini(void);
275 #endif /* __CNXK_TIM_EVDEV_H__ */