drivers/event/cnxk/cnxk_tim_evdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_TIM_EVDEV_H__
   6 #define __CNXK_TIM_EVDEV_H__
   7
   8 #include <stddef.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <string.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14 #include <rte_event_timer_adapter.h>
  15 #include <rte_malloc.h>
  16 #include <rte_memzone.h>
  17 #include <rte_reciprocal.h>
  18
  19 #include "roc_api.h"
  20
  21 #define NSECPERSEC               1E9
  22 #define USECPERSEC               1E6
  23 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
  24
  25 #define CNXK_TIM_EVDEV_NAME         cnxk_tim_eventdev
  26 #define CNXK_TIM_MAX_BUCKETS        (0xFFFFF)
  27 #define CNXK_TIM_RING_DEF_CHUNK_SZ  (4096)
  28 #define CNXK_TIM_CHUNK_ALIGNMENT    (16)
  29 #define CNXK_TIM_MAX_BURST          \
  30                         (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
  31 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
  32 #define CNXK_TIM_MIN_CHUNK_SLOTS    (0x1)
  33 #define CNXK_TIM_MAX_CHUNK_SLOTS    (0x1FFE)
  34
  35 #define CN9K_TIM_MIN_TMO_TKS (256)
  36
  37 #define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
  38 #define CNXK_TIM_CHNK_SLOTS  "tim_chnk_slots"
  39 #define CNXK_TIM_RINGS_LMT   "tim_rings_lmt"
  40
  41 #define CNXK_TIM_SP      0x1
  42 #define CNXK_TIM_MP      0x2
  43 #define CNXK_TIM_ENA_FB  0x10
  44 #define CNXK_TIM_ENA_DFB 0x20
  45
  46 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
  47 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER                                        \
  48         ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
  49 #define TIM_BUCKET_W1_S_LOCK (40)
  50 #define TIM_BUCKET_W1_M_LOCK                                                   \
  51         ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1)
  52 #define TIM_BUCKET_W1_S_RSVD (35)
  53 #define TIM_BUCKET_W1_S_BSK  (34)
  54 #define TIM_BUCKET_W1_M_BSK                                                    \
  55         ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1)
  56 #define TIM_BUCKET_W1_S_HBT (33)
  57 #define TIM_BUCKET_W1_M_HBT                                                    \
  58         ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1)
  59 #define TIM_BUCKET_W1_S_SBT (32)
  60 #define TIM_BUCKET_W1_M_SBT                                                    \
  61         ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1)
  62 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
  63 #define TIM_BUCKET_W1_M_NUM_ENTRIES                                            \
  64         ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
  65
  66 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
  67
  68 #define TIM_BUCKET_CHUNK_REMAIN                                                \
  69         (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
  70
  71 #define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
  72
  73 #define TIM_BUCKET_SEMA_WLOCK                                                  \
  74         (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
  75
  76 struct cnxk_tim_evdev {
  77         struct roc_tim tim;
  78         struct rte_eventdev *event_dev;
  79         uint16_t nb_rings;
  80         uint32_t chunk_sz;
  81         /* Dev args */
  82         uint8_t disable_npa;
  83         uint16_t chunk_slots;
  84         uint16_t min_ring_cnt;
  85 };
  86
  87 enum cnxk_tim_clk_src {
  88         CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
  89         CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
  90         CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
  91         CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
  92 };
  93
  94 struct cnxk_tim_bkt {
  95         uint64_t first_chunk;
  96         union {
  97                 uint64_t w1;
  98                 struct {
  99                         uint32_t nb_entry;
 100                         uint8_t sbt : 1;
 101                         uint8_t hbt : 1;
 102                         uint8_t bsk : 1;
 103                         uint8_t rsvd : 5;
 104                         uint8_t lock;
 105                         int16_t chunk_remainder;
 106                 };
 107         };
 108         uint64_t current_chunk;
 109         uint64_t pad;
 110 };
 111
 112 struct cnxk_tim_ring {
 113         uintptr_t base;
 114         uint16_t nb_chunk_slots;
 115         uint32_t nb_bkts;
 116         uint64_t last_updt_cyc;
 117         uint64_t ring_start_cyc;
 118         uint64_t tck_int;
 119         uint64_t tot_int;
 120         struct cnxk_tim_bkt *bkt;
 121         struct rte_mempool *chunk_pool;
 122         struct rte_reciprocal_u64 fast_div;
 123         struct rte_reciprocal_u64 fast_bkt;
 124         uint64_t arm_cnt;
 125         uint8_t prod_type_sp;
 126         uint8_t disable_npa;
 127         uint8_t ena_dfb;
 128         uint16_t ring_id;
 129         uint32_t aura;
 130         uint64_t nb_timers;
 131         uint64_t tck_nsec;
 132         uint64_t max_tout;
 133         uint64_t nb_chunks;
 134         uint64_t chunk_sz;
 135         enum cnxk_tim_clk_src clk_src;
 136 } __rte_cache_aligned;
 137
 138 struct cnxk_tim_ent {
 139         uint64_t w0;
 140         uint64_t wqe;
 141 };
 142
 143 static inline struct cnxk_tim_evdev *
 144 cnxk_tim_priv_get(void)
 145 {
 146         const struct rte_memzone *mz;
 147
 148         mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));
 149         if (mz == NULL)
 150                 return NULL;
 151
 152         return mz->addr;
 153 }
 154
 155 static inline uint64_t
 156 cnxk_tim_min_tmo_ticks(uint64_t freq)
 157 {
 158         if (roc_model_runtime_is_cn9k())
 159                 return CN9K_TIM_MIN_TMO_TKS;
 160         else /* CN10K min tick is of 1us */
 161                 return freq / USECPERSEC;
 162 }
 163
 164 static inline uint64_t
 165 cnxk_tim_min_resolution_ns(uint64_t freq)
 166 {
 167         return NSECPERSEC / freq;
 168 }
 169
 170 static inline enum roc_tim_clk_src
 171 cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
 172 {
 173         switch (clk_src) {
 174         case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
 175                 return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
 176                                                            ROC_TIM_CLK_SRC_GTI;
 177         default:
 178                 return ROC_TIM_CLK_SRC_INVALID;
 179         }
 180 }
 181
 182 #ifdef RTE_ARCH_ARM64
 183 static inline uint64_t
 184 cnxk_tim_cntvct(void)
 185 {
 186         uint64_t tsc;
 187
 188         asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
 189         return tsc;
 190 }
 191
 192 static inline uint64_t
 193 cnxk_tim_cntfrq(void)
 194 {
 195         uint64_t freq;
 196
 197         asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
 198         return freq;
 199 }
 200 #else
 201 static inline uint64_t
 202 cnxk_tim_cntvct(void)
 203 {
 204         return 0;
 205 }
 206
 207 static inline uint64_t
 208 cnxk_tim_cntfrq(void)
 209 {
 210         return 0;
 211 }
 212 #endif
 213
 214 #define TIM_ARM_FASTPATH_MODES                                                 \
 215         FP(sp, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP)                           \
 216         FP(mp, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP)                           \
 217         FP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP)                         \
 218         FP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP)
 219
 220 #define TIM_ARM_TMO_FASTPATH_MODES                                             \
 221         FP(dfb, 0, CNXK_TIM_ENA_DFB)                                           \
 222         FP(fb, 1, CNXK_TIM_ENA_FB)
 223
 224 #define FP(_name, _f2, _f1, flags)                                             \
 225         uint16_t cnxk_tim_arm_burst_##_name(                                   \
 226                 const struct rte_event_timer_adapter *adptr,                   \
 227                 struct rte_event_timer **tim, const uint16_t nb_timers);
 228 TIM_ARM_FASTPATH_MODES
 229 #undef FP
 230
 231 #define FP(_name, _f1, flags)                                                  \
 232         uint16_t cnxk_tim_arm_tmo_tick_burst_##_name(                          \
 233                 const struct rte_event_timer_adapter *adptr,                   \
 234                 struct rte_event_timer **tim, const uint64_t timeout_tick,     \
 235                 const uint16_t nb_timers);
 236 TIM_ARM_TMO_FASTPATH_MODES
 237 #undef FP
 238
 239 uint16_t
 240 cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,
 241                             struct rte_event_timer **tim,
 242                             const uint16_t nb_timers);
 243
 244 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 245                       uint32_t *caps,
 246                       const struct rte_event_timer_adapter_ops **ops);
 247
 248 void cnxk_tim_init(struct roc_sso *sso);
 249 void cnxk_tim_fini(void);
 250
 251 #endif /* __CNXK_TIM_EVDEV_H__ */