1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef __CNXK_TIM_EVDEV_H__
6 #define __CNXK_TIM_EVDEV_H__
13 #include <eventdev_pmd_pci.h>
14 #include <rte_event_timer_adapter.h>
15 #include <rte_malloc.h>
16 #include <rte_memzone.h>
17 #include <rte_reciprocal.h>
21 #define NSECPERSEC 1E9
22 #define USECPERSEC 1E6
23 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
25 #define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev
26 #define CNXK_TIM_MAX_BUCKETS (0xFFFFF)
27 #define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)
28 #define CNXK_TIM_CHUNK_ALIGNMENT (16)
29 #define CNXK_TIM_MAX_BURST \
30 (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
31 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
32 #define CNXK_TIM_MIN_CHUNK_SLOTS (0x1)
33 #define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE)
35 #define CN9K_TIM_MIN_TMO_TKS (256)
37 #define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
38 #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots"
39 #define CNXK_TIM_RINGS_LMT "tim_rings_lmt"
41 #define CNXK_TIM_SP 0x1
42 #define CNXK_TIM_MP 0x2
43 #define CNXK_TIM_ENA_FB 0x10
44 #define CNXK_TIM_ENA_DFB 0x20
46 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
47 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \
48 ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
49 #define TIM_BUCKET_W1_S_LOCK (40)
50 #define TIM_BUCKET_W1_M_LOCK \
51 ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1)
52 #define TIM_BUCKET_W1_S_RSVD (35)
53 #define TIM_BUCKET_W1_S_BSK (34)
54 #define TIM_BUCKET_W1_M_BSK \
55 ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1)
56 #define TIM_BUCKET_W1_S_HBT (33)
57 #define TIM_BUCKET_W1_M_HBT \
58 ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1)
59 #define TIM_BUCKET_W1_S_SBT (32)
60 #define TIM_BUCKET_W1_M_SBT \
61 ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1)
62 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
63 #define TIM_BUCKET_W1_M_NUM_ENTRIES \
64 ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
66 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
68 #define TIM_BUCKET_CHUNK_REMAIN \
69 (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
71 #define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
73 #define TIM_BUCKET_SEMA_WLOCK \
74 (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
76 struct cnxk_tim_evdev {
78 struct rte_eventdev *event_dev;
84 uint16_t min_ring_cnt;
87 enum cnxk_tim_clk_src {
88 CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
89 CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
90 CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
91 CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
105 int16_t chunk_remainder;
108 uint64_t current_chunk;
112 struct cnxk_tim_ring {
114 uint16_t nb_chunk_slots;
116 uint64_t last_updt_cyc;
117 uint64_t ring_start_cyc;
120 struct cnxk_tim_bkt *bkt;
121 struct rte_mempool *chunk_pool;
122 struct rte_reciprocal_u64 fast_div;
123 struct rte_reciprocal_u64 fast_bkt;
125 uint8_t prod_type_sp;
135 enum cnxk_tim_clk_src clk_src;
136 } __rte_cache_aligned;
138 struct cnxk_tim_ent {
143 static inline struct cnxk_tim_evdev *
144 cnxk_tim_priv_get(void)
146 const struct rte_memzone *mz;
148 mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));
155 static inline uint64_t
156 cnxk_tim_min_tmo_ticks(uint64_t freq)
158 if (roc_model_runtime_is_cn9k())
159 return CN9K_TIM_MIN_TMO_TKS;
160 else /* CN10K min tick is of 1us */
161 return freq / USECPERSEC;
164 static inline uint64_t
165 cnxk_tim_min_resolution_ns(uint64_t freq)
167 return NSECPERSEC / freq;
170 static inline enum roc_tim_clk_src
171 cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
174 case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
175 return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
178 return ROC_TIM_CLK_SRC_INVALID;
182 #ifdef RTE_ARCH_ARM64
183 static inline uint64_t
184 cnxk_tim_cntvct(void)
188 asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
192 static inline uint64_t
193 cnxk_tim_cntfrq(void)
197 asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
201 static inline uint64_t
202 cnxk_tim_cntvct(void)
207 static inline uint64_t
208 cnxk_tim_cntfrq(void)
214 #define TIM_ARM_FASTPATH_MODES \
215 FP(sp, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \
216 FP(mp, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \
217 FP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \
218 FP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP)
220 #define FP(_name, _f2, _f1, flags) \
221 uint16_t cnxk_tim_arm_burst_##_name( \
222 const struct rte_event_timer_adapter *adptr, \
223 struct rte_event_timer **tim, const uint16_t nb_timers);
224 TIM_ARM_FASTPATH_MODES
227 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
229 const struct rte_event_timer_adapter_ops **ops);
231 void cnxk_tim_init(struct roc_sso *sso);
232 void cnxk_tim_fini(void);
234 #endif /* __CNXK_TIM_EVDEV_H__ */