drivers/event/cnxk/cnxk_tim_evdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_TIM_EVDEV_H__
   6 #define __CNXK_TIM_EVDEV_H__
   7
   8 #include <stddef.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <string.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14 #include <rte_event_timer_adapter.h>
  15 #include <rte_malloc.h>
  16 #include <rte_memzone.h>
  17
  18 #include "roc_api.h"
  19
  20 #define NSECPERSEC               1E9
  21 #define USECPERSEC               1E6
  22 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
  23
  24 #define CNXK_TIM_EVDEV_NAME         cnxk_tim_eventdev
  25 #define CNXK_TIM_MAX_BUCKETS        (0xFFFFF)
  26 #define CNXK_TIM_RING_DEF_CHUNK_SZ  (4096)
  27 #define CNXK_TIM_CHUNK_ALIGNMENT    (16)
  28 #define CNXK_TIM_MAX_BURST          \
  29                         (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
  30 #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
  31 #define CNXK_TIM_MIN_CHUNK_SLOTS    (0x1)
  32 #define CNXK_TIM_MAX_CHUNK_SLOTS    (0x1FFE)
  33
  34 #define CN9K_TIM_MIN_TMO_TKS (256)
  35
  36 #define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
  37 #define CNXK_TIM_CHNK_SLOTS  "tim_chnk_slots"
  38 #define CNXK_TIM_RINGS_LMT   "tim_rings_lmt"
  39
  40 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
  41 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER                                        \
  42         ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
  43 #define TIM_BUCKET_W1_S_LOCK (40)
  44 #define TIM_BUCKET_W1_M_LOCK                                                   \
  45         ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1)
  46 #define TIM_BUCKET_W1_S_RSVD (35)
  47 #define TIM_BUCKET_W1_S_BSK  (34)
  48 #define TIM_BUCKET_W1_M_BSK                                                    \
  49         ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1)
  50 #define TIM_BUCKET_W1_S_HBT (33)
  51 #define TIM_BUCKET_W1_M_HBT                                                    \
  52         ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1)
  53 #define TIM_BUCKET_W1_S_SBT (32)
  54 #define TIM_BUCKET_W1_M_SBT                                                    \
  55         ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1)
  56 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
  57 #define TIM_BUCKET_W1_M_NUM_ENTRIES                                            \
  58         ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
  59
  60 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
  61
  62 #define TIM_BUCKET_CHUNK_REMAIN                                                \
  63         (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
  64
  65 #define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
  66
  67 #define TIM_BUCKET_SEMA_WLOCK                                                  \
  68         (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
  69
  70 struct cnxk_tim_evdev {
  71         struct roc_tim tim;
  72         struct rte_eventdev *event_dev;
  73         uint16_t nb_rings;
  74         uint32_t chunk_sz;
  75         /* Dev args */
  76         uint8_t disable_npa;
  77         uint16_t chunk_slots;
  78         uint16_t min_ring_cnt;
  79 };
  80
  81 enum cnxk_tim_clk_src {
  82         CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
  83         CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
  84         CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
  85         CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
  86 };
  87
  88 struct cnxk_tim_bkt {
  89         uint64_t first_chunk;
  90         union {
  91                 uint64_t w1;
  92                 struct {
  93                         uint32_t nb_entry;
  94                         uint8_t sbt : 1;
  95                         uint8_t hbt : 1;
  96                         uint8_t bsk : 1;
  97                         uint8_t rsvd : 5;
  98                         uint8_t lock;
  99                         int16_t chunk_remainder;
 100                 };
 101         };
 102         uint64_t current_chunk;
 103         uint64_t pad;
 104 };
 105
 106 struct cnxk_tim_ring {
 107         uintptr_t base;
 108         uint16_t nb_chunk_slots;
 109         uint32_t nb_bkts;
 110         uint64_t tck_int;
 111         uint64_t tot_int;
 112         struct cnxk_tim_bkt *bkt;
 113         struct rte_mempool *chunk_pool;
 114         uint64_t arm_cnt;
 115         uint8_t prod_type_sp;
 116         uint8_t disable_npa;
 117         uint8_t ena_dfb;
 118         uint16_t ring_id;
 119         uint32_t aura;
 120         uint64_t nb_timers;
 121         uint64_t tck_nsec;
 122         uint64_t max_tout;
 123         uint64_t nb_chunks;
 124         uint64_t chunk_sz;
 125         enum cnxk_tim_clk_src clk_src;
 126 } __rte_cache_aligned;
 127
 128 struct cnxk_tim_ent {
 129         uint64_t w0;
 130         uint64_t wqe;
 131 };
 132
 133 static inline struct cnxk_tim_evdev *
 134 cnxk_tim_priv_get(void)
 135 {
 136         const struct rte_memzone *mz;
 137
 138         mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));
 139         if (mz == NULL)
 140                 return NULL;
 141
 142         return mz->addr;
 143 }
 144
 145 static inline uint64_t
 146 cnxk_tim_min_tmo_ticks(uint64_t freq)
 147 {
 148         if (roc_model_runtime_is_cn9k())
 149                 return CN9K_TIM_MIN_TMO_TKS;
 150         else /* CN10K min tick is of 1us */
 151                 return freq / USECPERSEC;
 152 }
 153
 154 static inline uint64_t
 155 cnxk_tim_min_resolution_ns(uint64_t freq)
 156 {
 157         return NSECPERSEC / freq;
 158 }
 159
 160 static inline enum roc_tim_clk_src
 161 cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
 162 {
 163         switch (clk_src) {
 164         case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
 165                 return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
 166                                                            ROC_TIM_CLK_SRC_GTI;
 167         default:
 168                 return ROC_TIM_CLK_SRC_INVALID;
 169         }
 170 }
 171
 172 #ifdef RTE_ARCH_ARM64
 173 static inline uint64_t
 174 cnxk_tim_cntvct(void)
 175 {
 176         uint64_t tsc;
 177
 178         asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
 179         return tsc;
 180 }
 181
 182 static inline uint64_t
 183 cnxk_tim_cntfrq(void)
 184 {
 185         uint64_t freq;
 186
 187         asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
 188         return freq;
 189 }
 190 #else
 191 static inline uint64_t
 192 cnxk_tim_cntvct(void)
 193 {
 194         return 0;
 195 }
 196
 197 static inline uint64_t
 198 cnxk_tim_cntfrq(void)
 199 {
 200         return 0;
 201 }
 202 #endif
 203
 204 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 205                       uint32_t *caps,
 206                       const struct rte_event_timer_adapter_ops **ops);
 207
 208 void cnxk_tim_init(struct roc_sso *sso);
 209 void cnxk_tim_fini(void);
 210
 211 #endif /* __CNXK_TIM_EVDEV_H__ */