1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2020 Intel Corporation
13 #include <sys/fcntl.h>
17 #include <rte_common.h>
18 #include <rte_config.h>
19 #include <rte_cycles.h>
20 #include <rte_debug.h>
22 #include <rte_errno.h>
24 #include <rte_kvargs.h>
26 #include <rte_malloc.h>
28 #include <rte_power_intrinsics.h>
29 #include <rte_prefetch.h>
31 #include <rte_string_fns.h>
33 #include <rte_eventdev.h>
34 #include <rte_eventdev_pmd.h>
37 #include "dlb_iface.h"
38 #include "dlb_inline_fns.h"
41 * Resources exposed to eventdev.
43 #if (RTE_EVENT_MAX_QUEUES_PER_DEV > UINT8_MAX)
44 #error "RTE_EVENT_MAX_QUEUES_PER_DEV cannot fit in member max_event_queues"
46 static struct rte_event_dev_info evdev_dlb_default_info = {
47 .driver_name = "", /* probe will set */
48 .min_dequeue_timeout_ns = DLB_MIN_DEQUEUE_TIMEOUT_NS,
49 .max_dequeue_timeout_ns = DLB_MAX_DEQUEUE_TIMEOUT_NS,
50 #if (RTE_EVENT_MAX_QUEUES_PER_DEV < DLB_MAX_NUM_LDB_QUEUES)
51 .max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,
53 .max_event_queues = DLB_MAX_NUM_LDB_QUEUES,
55 .max_event_queue_flows = DLB_MAX_NUM_FLOWS,
56 .max_event_queue_priority_levels = DLB_QID_PRIORITIES,
57 .max_event_priority_levels = DLB_QID_PRIORITIES,
58 .max_event_ports = DLB_MAX_NUM_LDB_PORTS,
59 .max_event_port_dequeue_depth = DLB_MAX_CQ_DEPTH,
60 .max_event_port_enqueue_depth = DLB_MAX_ENQUEUE_DEPTH,
61 .max_event_port_links = DLB_MAX_NUM_QIDS_PER_LDB_CQ,
62 .max_num_events = DLB_MAX_NUM_LDB_CREDITS,
63 .max_single_link_event_port_queue_pairs = DLB_MAX_NUM_DIR_PORTS,
64 .event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |
65 RTE_EVENT_DEV_CAP_EVENT_QOS |
66 RTE_EVENT_DEV_CAP_BURST_MODE |
67 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
68 RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |
69 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES),
72 struct process_local_port_data
73 dlb_port[DLB_MAX_NUM_PORTS][NUM_DLB_PORT_TYPES];
75 static inline uint16_t
76 dlb_event_enqueue_delayed(void *event_port,
77 const struct rte_event events[]);
79 static inline uint16_t
80 dlb_event_enqueue_burst_delayed(void *event_port,
81 const struct rte_event events[],
84 static inline uint16_t
85 dlb_event_enqueue_new_burst_delayed(void *event_port,
86 const struct rte_event events[],
89 static inline uint16_t
90 dlb_event_enqueue_forward_burst_delayed(void *event_port,
91 const struct rte_event events[],
95 dlb_hw_query_resources(struct dlb_eventdev *dlb)
97 struct dlb_hw_dev *handle = &dlb->qm_instance;
98 struct dlb_hw_resource_info *dlb_info = &handle->info;
101 ret = dlb_iface_get_num_resources(handle,
102 &dlb->hw_rsrc_query_results);
104 DLB_LOG_ERR("get dlb num resources, err=%d\n", ret);
108 /* Complete filling in device resource info returned to evdev app,
109 * overriding any default values.
110 * The capabilities (CAPs) were set at compile time.
113 evdev_dlb_default_info.max_event_queues =
114 dlb->hw_rsrc_query_results.num_ldb_queues;
116 evdev_dlb_default_info.max_event_ports =
117 dlb->hw_rsrc_query_results.num_ldb_ports;
119 evdev_dlb_default_info.max_num_events =
120 dlb->hw_rsrc_query_results.max_contiguous_ldb_credits;
122 /* Save off values used when creating the scheduling domain. */
124 handle->info.num_sched_domains =
125 dlb->hw_rsrc_query_results.num_sched_domains;
127 handle->info.hw_rsrc_max.nb_events_limit =
128 dlb->hw_rsrc_query_results.max_contiguous_ldb_credits;
130 handle->info.hw_rsrc_max.num_queues =
131 dlb->hw_rsrc_query_results.num_ldb_queues +
132 dlb->hw_rsrc_query_results.num_dir_ports;
134 handle->info.hw_rsrc_max.num_ldb_queues =
135 dlb->hw_rsrc_query_results.num_ldb_queues;
137 handle->info.hw_rsrc_max.num_ldb_ports =
138 dlb->hw_rsrc_query_results.num_ldb_ports;
140 handle->info.hw_rsrc_max.num_dir_ports =
141 dlb->hw_rsrc_query_results.num_dir_ports;
143 handle->info.hw_rsrc_max.reorder_window_size =
144 dlb->hw_rsrc_query_results.num_hist_list_entries;
146 rte_memcpy(dlb_info, &handle->info.hw_rsrc_max, sizeof(*dlb_info));
152 dlb_free_qe_mem(struct dlb_port *qm_port)
157 rte_free(qm_port->qe4);
160 rte_free(qm_port->consume_qe);
161 qm_port->consume_qe = NULL;
165 dlb_init_consume_qe(struct dlb_port *qm_port, char *mz_name)
167 struct dlb_cq_pop_qe *qe;
169 qe = rte_zmalloc(mz_name,
170 DLB_NUM_QES_PER_CACHE_LINE *
171 sizeof(struct dlb_cq_pop_qe),
172 RTE_CACHE_LINE_SIZE);
175 DLB_LOG_ERR("dlb: no memory for consume_qe\n");
179 qm_port->consume_qe = qe;
185 /* Tokens value is 0-based; i.e. '0' returns 1 token, '1' returns 2,
188 qe->tokens = 0; /* set at run time */
191 /* Completion IDs are disabled */
198 dlb_init_qe_mem(struct dlb_port *qm_port, char *mz_name)
202 sz = DLB_NUM_QES_PER_CACHE_LINE * sizeof(struct dlb_enqueue_qe);
204 qm_port->qe4 = rte_zmalloc(mz_name, sz, RTE_CACHE_LINE_SIZE);
206 if (qm_port->qe4 == NULL) {
207 DLB_LOG_ERR("dlb: no qe4 memory\n");
212 ret = dlb_init_consume_qe(qm_port, mz_name);
214 DLB_LOG_ERR("dlb: dlb_init_consume_qe ret=%d\n", ret);
222 dlb_free_qe_mem(qm_port);
227 /* Wrapper for string to int conversion. Substituted for atoi(...), which is
230 #define DLB_BASE_10 10
233 dlb_string_to_int(int *result, const char *str)
238 if (str == NULL || result == NULL)
242 ret = strtol(str, &endstr, DLB_BASE_10);
246 /* long int and int may be different width for some architectures */
247 if (ret < INT_MIN || ret > INT_MAX || endstr == str)
255 set_numa_node(const char *key __rte_unused, const char *value, void *opaque)
257 int *socket_id = opaque;
260 ret = dlb_string_to_int(socket_id, value);
264 if (*socket_id > RTE_MAX_NUMA_NODES)
271 set_max_num_events(const char *key __rte_unused,
275 int *max_num_events = opaque;
278 if (value == NULL || opaque == NULL) {
279 DLB_LOG_ERR("NULL pointer\n");
283 ret = dlb_string_to_int(max_num_events, value);
287 if (*max_num_events < 0 || *max_num_events > DLB_MAX_NUM_LDB_CREDITS) {
288 DLB_LOG_ERR("dlb: max_num_events must be between 0 and %d\n",
289 DLB_MAX_NUM_LDB_CREDITS);
297 set_num_dir_credits(const char *key __rte_unused,
301 int *num_dir_credits = opaque;
304 if (value == NULL || opaque == NULL) {
305 DLB_LOG_ERR("NULL pointer\n");
309 ret = dlb_string_to_int(num_dir_credits, value);
313 if (*num_dir_credits < 0 ||
314 *num_dir_credits > DLB_MAX_NUM_DIR_CREDITS) {
315 DLB_LOG_ERR("dlb: num_dir_credits must be between 0 and %d\n",
316 DLB_MAX_NUM_DIR_CREDITS);
323 * This function first unmaps all memory mappings and closes the
324 * domain's file descriptor, which causes the driver to reset the
325 * scheduling domain. Once that completes (when close() returns), we
326 * can safely free the dynamically allocated memory used by the
330 * We will maintain a use count and use that to determine when
331 * a reset is required. In PF mode, we never mmap, or munmap
332 * device memory, and we own the entire physical PCI device.
336 dlb_hw_reset_sched_domain(const struct rte_eventdev *dev, bool reconfig)
338 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
339 enum dlb_configuration_state config_state;
342 /* Close and reset the domain */
343 dlb_iface_domain_close(dlb);
345 /* Free all dynamically allocated port memory */
346 for (i = 0; i < dlb->num_ports; i++)
347 dlb_free_qe_mem(&dlb->ev_ports[i].qm_port);
349 /* If reconfiguring, mark the device's queues and ports as "previously
350 * configured." If the user does not reconfigure them, the PMD will
351 * reapply their previous configuration when the device is started.
353 config_state = (reconfig) ? DLB_PREV_CONFIGURED : DLB_NOT_CONFIGURED;
355 for (i = 0; i < dlb->num_ports; i++) {
356 dlb->ev_ports[i].qm_port.config_state = config_state;
357 /* Reset setup_done so ports can be reconfigured */
358 dlb->ev_ports[i].setup_done = false;
359 for (j = 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++)
360 dlb->ev_ports[i].link[j].mapped = false;
363 for (i = 0; i < dlb->num_queues; i++)
364 dlb->ev_queues[i].qm_queue.config_state = config_state;
366 for (i = 0; i < DLB_MAX_NUM_QUEUES; i++)
367 dlb->ev_queues[i].setup_done = false;
370 dlb->num_ldb_ports = 0;
371 dlb->num_dir_ports = 0;
373 dlb->num_ldb_queues = 0;
374 dlb->num_dir_queues = 0;
375 dlb->configured = false;
379 dlb_ldb_credit_pool_create(struct dlb_hw_dev *handle)
381 struct dlb_create_ldb_pool_args cfg;
382 struct dlb_cmd_response response;
388 if (!handle->cfg.resources.num_ldb_credits) {
389 handle->cfg.ldb_credit_pool_id = 0;
390 handle->cfg.num_ldb_credits = 0;
394 cfg.response = (uintptr_t)&response;
395 cfg.num_ldb_credits = handle->cfg.resources.num_ldb_credits;
397 ret = dlb_iface_ldb_credit_pool_create(handle,
400 DLB_LOG_ERR("dlb: ldb_credit_pool_create ret=%d (driver status: %s)\n",
401 ret, dlb_error_strings[response.status]);
404 handle->cfg.ldb_credit_pool_id = response.id;
405 handle->cfg.num_ldb_credits = cfg.num_ldb_credits;
411 dlb_dir_credit_pool_create(struct dlb_hw_dev *handle)
413 struct dlb_create_dir_pool_args cfg;
414 struct dlb_cmd_response response;
420 if (!handle->cfg.resources.num_dir_credits) {
421 handle->cfg.dir_credit_pool_id = 0;
422 handle->cfg.num_dir_credits = 0;
426 cfg.response = (uintptr_t)&response;
427 cfg.num_dir_credits = handle->cfg.resources.num_dir_credits;
429 ret = dlb_iface_dir_credit_pool_create(handle, &cfg);
431 DLB_LOG_ERR("dlb: dir_credit_pool_create ret=%d (driver status: %s)\n",
432 ret, dlb_error_strings[response.status]);
434 handle->cfg.dir_credit_pool_id = response.id;
435 handle->cfg.num_dir_credits = cfg.num_dir_credits;
441 dlb_hw_create_sched_domain(struct dlb_hw_dev *handle,
442 struct dlb_eventdev *dlb,
443 const struct dlb_hw_rsrcs *resources_asked)
446 struct dlb_create_sched_domain_args *config_params;
447 struct dlb_cmd_response response;
449 if (resources_asked == NULL) {
450 DLB_LOG_ERR("dlb: dlb_create NULL parameter\n");
455 /* Map generic qm resources to dlb resources */
456 config_params = &handle->cfg.resources;
458 config_params->response = (uintptr_t)&response;
460 /* DIR ports and queues */
462 config_params->num_dir_ports =
463 resources_asked->num_dir_ports;
465 config_params->num_dir_credits =
466 resources_asked->num_dir_credits;
468 /* LDB ports and queues */
470 config_params->num_ldb_queues =
471 resources_asked->num_ldb_queues;
473 config_params->num_ldb_ports =
474 resources_asked->num_ldb_ports;
476 config_params->num_ldb_credits =
477 resources_asked->num_ldb_credits;
479 config_params->num_atomic_inflights =
480 dlb->num_atm_inflights_per_queue *
481 config_params->num_ldb_queues;
483 config_params->num_hist_list_entries = config_params->num_ldb_ports *
484 DLB_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
486 /* dlb limited to 1 credit pool per queue type */
487 config_params->num_ldb_credit_pools = 1;
488 config_params->num_dir_credit_pools = 1;
490 DLB_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d, ldb_cred_pools=%d, dir-credit_pools=%d\n",
491 config_params->num_ldb_queues,
492 config_params->num_ldb_ports,
493 config_params->num_dir_ports,
494 config_params->num_atomic_inflights,
495 config_params->num_hist_list_entries,
496 config_params->num_ldb_credits,
497 config_params->num_dir_credits,
498 config_params->num_ldb_credit_pools,
499 config_params->num_dir_credit_pools);
501 /* Configure the QM */
503 ret = dlb_iface_sched_domain_create(handle, config_params);
505 DLB_LOG_ERR("dlb: domain create failed, device_id = %d, (driver ret = %d, extra status: %s)\n",
508 dlb_error_strings[response.status]);
512 handle->domain_id = response.id;
513 handle->domain_id_valid = 1;
515 config_params->response = 0;
517 ret = dlb_ldb_credit_pool_create(handle);
519 DLB_LOG_ERR("dlb: create ldb credit pool failed\n");
523 ret = dlb_dir_credit_pool_create(handle);
525 DLB_LOG_ERR("dlb: create dir credit pool failed\n");
529 handle->cfg.configured = true;
534 dlb_iface_domain_close(dlb);
540 /* End HW specific */
542 dlb_eventdev_info_get(struct rte_eventdev *dev,
543 struct rte_event_dev_info *dev_info)
545 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
548 ret = dlb_hw_query_resources(dlb);
550 const struct rte_eventdev_data *data = dev->data;
552 DLB_LOG_ERR("get resources err=%d, devid=%d\n",
554 /* fn is void, so fall through and return values set up in
559 /* Add num resources currently owned by this domain.
560 * These would become available if the scheduling domain were reset due
561 * to the application recalling eventdev_configure to *reconfigure* the
564 evdev_dlb_default_info.max_event_ports += dlb->num_ldb_ports;
565 evdev_dlb_default_info.max_event_queues += dlb->num_ldb_queues;
566 evdev_dlb_default_info.max_num_events += dlb->num_ldb_credits;
568 /* In DLB A-stepping hardware, applications are limited to 128
569 * configured ports (load-balanced or directed). The reported number of
570 * available ports must reflect this.
572 if (dlb->revision < DLB_REV_B0) {
575 used_ports = DLB_MAX_NUM_LDB_PORTS + DLB_MAX_NUM_DIR_PORTS -
576 dlb->hw_rsrc_query_results.num_ldb_ports -
577 dlb->hw_rsrc_query_results.num_dir_ports;
579 evdev_dlb_default_info.max_event_ports =
580 RTE_MIN(evdev_dlb_default_info.max_event_ports,
584 evdev_dlb_default_info.max_event_queues =
585 RTE_MIN(evdev_dlb_default_info.max_event_queues,
586 RTE_EVENT_MAX_QUEUES_PER_DEV);
588 evdev_dlb_default_info.max_num_events =
589 RTE_MIN(evdev_dlb_default_info.max_num_events,
590 dlb->max_num_events_override);
592 *dev_info = evdev_dlb_default_info;
595 /* Note: 1 QM instance per QM device, QM instance/device == event device */
597 dlb_eventdev_configure(const struct rte_eventdev *dev)
599 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
600 struct dlb_hw_dev *handle = &dlb->qm_instance;
601 struct dlb_hw_rsrcs *rsrcs = &handle->info.hw_rsrc_max;
602 const struct rte_eventdev_data *data = dev->data;
603 const struct rte_event_dev_config *config = &data->dev_conf;
606 /* If this eventdev is already configured, we must release the current
607 * scheduling domain before attempting to configure a new one.
609 if (dlb->configured) {
610 dlb_hw_reset_sched_domain(dev, true);
612 ret = dlb_hw_query_resources(dlb);
614 DLB_LOG_ERR("get resources err=%d, devid=%d\n",
620 if (config->nb_event_queues > rsrcs->num_queues) {
621 DLB_LOG_ERR("nb_event_queues parameter (%d) exceeds the QM device's capabilities (%d).\n",
622 config->nb_event_queues,
626 if (config->nb_event_ports > (rsrcs->num_ldb_ports
627 + rsrcs->num_dir_ports)) {
628 DLB_LOG_ERR("nb_event_ports parameter (%d) exceeds the QM device's capabilities (%d).\n",
629 config->nb_event_ports,
630 (rsrcs->num_ldb_ports + rsrcs->num_dir_ports));
633 if (config->nb_events_limit > rsrcs->nb_events_limit) {
634 DLB_LOG_ERR("nb_events_limit parameter (%d) exceeds the QM device's capabilities (%d).\n",
635 config->nb_events_limit,
636 rsrcs->nb_events_limit);
640 if (config->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
641 dlb->global_dequeue_wait = false;
645 dlb->global_dequeue_wait = true;
647 timeout32 = config->dequeue_timeout_ns;
649 dlb->global_dequeue_wait_ticks =
650 timeout32 * (rte_get_timer_hz() / 1E9);
653 /* Does this platform support umonitor/umwait? */
654 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {
655 if (RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 0 &&
656 RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 1) {
657 DLB_LOG_ERR("invalid value (%d) for RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE must be 0 or 1.\n",
658 RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE);
661 dlb->umwait_allowed = true;
664 rsrcs->num_dir_ports = config->nb_single_link_event_port_queues;
665 rsrcs->num_ldb_ports = config->nb_event_ports - rsrcs->num_dir_ports;
666 /* 1 dir queue per dir port */
667 rsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;
669 /* Scale down nb_events_limit by 4 for directed credits, since there
670 * are 4x as many load-balanced credits.
672 rsrcs->num_ldb_credits = 0;
673 rsrcs->num_dir_credits = 0;
675 if (rsrcs->num_ldb_queues)
676 rsrcs->num_ldb_credits = config->nb_events_limit;
677 if (rsrcs->num_dir_ports)
678 rsrcs->num_dir_credits = config->nb_events_limit / 4;
679 if (dlb->num_dir_credits_override != -1)
680 rsrcs->num_dir_credits = dlb->num_dir_credits_override;
682 if (dlb_hw_create_sched_domain(handle, dlb, rsrcs) < 0) {
683 DLB_LOG_ERR("dlb_hw_create_sched_domain failed\n");
687 dlb->new_event_limit = config->nb_events_limit;
688 __atomic_store_n(&dlb->inflights, 0, __ATOMIC_SEQ_CST);
690 /* Save number of ports/queues for this event dev */
691 dlb->num_ports = config->nb_event_ports;
692 dlb->num_queues = config->nb_event_queues;
693 dlb->num_dir_ports = rsrcs->num_dir_ports;
694 dlb->num_ldb_ports = dlb->num_ports - dlb->num_dir_ports;
695 dlb->num_ldb_queues = dlb->num_queues - dlb->num_dir_ports;
696 dlb->num_dir_queues = dlb->num_dir_ports;
697 dlb->num_ldb_credits = rsrcs->num_ldb_credits;
698 dlb->num_dir_credits = rsrcs->num_dir_credits;
700 dlb->configured = true;
706 dlb_hw_unmap_ldb_qid_from_port(struct dlb_hw_dev *handle,
710 struct dlb_unmap_qid_args cfg;
711 struct dlb_cmd_response response;
717 cfg.response = (uintptr_t)&response;
718 cfg.port_id = qm_port_id;
721 ret = dlb_iface_unmap_qid(handle, &cfg);
723 DLB_LOG_ERR("dlb: unmap qid error, ret=%d (driver status: %s)\n",
724 ret, dlb_error_strings[response.status]);
730 dlb_event_queue_detach_ldb(struct dlb_eventdev *dlb,
731 struct dlb_eventdev_port *ev_port,
732 struct dlb_eventdev_queue *ev_queue)
736 /* Don't unlink until start time. */
737 if (dlb->run_state == DLB_RUN_STATE_STOPPED)
740 for (i = 0; i < DLB_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
741 if (ev_port->link[i].valid &&
742 ev_port->link[i].queue_id == ev_queue->id)
746 /* This is expected with eventdev API!
747 * It blindly attempts to unmap all queues.
749 if (i == DLB_MAX_NUM_QIDS_PER_LDB_CQ) {
750 DLB_LOG_DBG("dlb: ignoring LB QID %d not mapped for qm_port %d.\n",
751 ev_queue->qm_queue.id,
752 ev_port->qm_port.id);
756 ret = dlb_hw_unmap_ldb_qid_from_port(&dlb->qm_instance,
758 ev_queue->qm_queue.id);
760 ev_port->link[i].mapped = false;
766 dlb_eventdev_port_unlink(struct rte_eventdev *dev, void *event_port,
767 uint8_t queues[], uint16_t nb_unlinks)
769 struct dlb_eventdev_port *ev_port = event_port;
770 struct dlb_eventdev *dlb;
775 if (!ev_port->setup_done) {
776 DLB_LOG_ERR("dlb: evport %d is not configured\n",
782 if (queues == NULL || nb_unlinks == 0) {
783 DLB_LOG_DBG("dlb: queues is NULL or nb_unlinks is 0\n");
784 return 0; /* Ignore and return success */
787 if (ev_port->qm_port.is_directed) {
788 DLB_LOG_DBG("dlb: ignore unlink from dir port %d\n",
791 return nb_unlinks; /* as if success */
796 for (i = 0; i < nb_unlinks; i++) {
797 struct dlb_eventdev_queue *ev_queue;
800 if (queues[i] >= dlb->num_queues) {
801 DLB_LOG_ERR("dlb: invalid queue id %d\n", queues[i]);
803 return i; /* return index of offending queue */
806 ev_queue = &dlb->ev_queues[queues[i]];
808 /* Does a link exist? */
809 for (j = 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++)
810 if (ev_port->link[j].queue_id == queues[i] &&
811 ev_port->link[j].valid)
814 if (j == DLB_MAX_NUM_QIDS_PER_LDB_CQ)
817 ret = dlb_event_queue_detach_ldb(dlb, ev_port, ev_queue);
819 DLB_LOG_ERR("unlink err=%d for port %d queue %d\n",
820 ret, ev_port->id, queues[i]);
822 return i; /* return index of offending queue */
825 ev_port->link[j].valid = false;
826 ev_port->num_links--;
827 ev_queue->num_links--;
834 dlb_eventdev_port_unlinks_in_progress(struct rte_eventdev *dev,
837 struct dlb_eventdev_port *ev_port = event_port;
838 struct dlb_eventdev *dlb;
839 struct dlb_hw_dev *handle;
840 struct dlb_pending_port_unmaps_args cfg;
841 struct dlb_cmd_response response;
846 if (!ev_port->setup_done) {
847 DLB_LOG_ERR("dlb: evport %d is not configured\n",
853 cfg.port_id = ev_port->qm_port.id;
854 cfg.response = (uintptr_t)&response;
856 handle = &dlb->qm_instance;
857 ret = dlb_iface_pending_port_unmaps(handle, &cfg);
860 DLB_LOG_ERR("dlb: num_unlinks_in_progress ret=%d (driver status: %s)\n",
861 ret, dlb_error_strings[response.status]);
869 dlb_eventdev_port_default_conf_get(struct rte_eventdev *dev,
871 struct rte_event_port_conf *port_conf)
873 RTE_SET_USED(port_id);
874 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
876 port_conf->new_event_threshold = dlb->new_event_limit;
877 port_conf->dequeue_depth = 32;
878 port_conf->enqueue_depth = DLB_MAX_ENQUEUE_DEPTH;
879 port_conf->event_port_cfg = 0;
883 dlb_eventdev_queue_default_conf_get(struct rte_eventdev *dev,
885 struct rte_event_queue_conf *queue_conf)
888 RTE_SET_USED(queue_id);
889 queue_conf->nb_atomic_flows = 1024;
890 queue_conf->nb_atomic_order_sequences = 32;
891 queue_conf->event_queue_cfg = 0;
892 queue_conf->priority = 0;
896 dlb_hw_create_ldb_port(struct dlb_eventdev *dlb,
897 struct dlb_eventdev_port *ev_port,
898 uint32_t dequeue_depth,
900 uint32_t enqueue_depth,
901 uint16_t rsvd_tokens,
902 bool use_rsvd_token_scheme)
904 struct dlb_hw_dev *handle = &dlb->qm_instance;
905 struct dlb_create_ldb_port_args cfg = {0};
906 struct dlb_cmd_response response = {0};
908 struct dlb_port *qm_port = NULL;
909 char mz_name[RTE_MEMZONE_NAMESIZE];
915 if (cq_depth < DLB_MIN_LDB_CQ_DEPTH) {
916 DLB_LOG_ERR("dlb: invalid cq_depth, must be %d-%d\n",
917 DLB_MIN_LDB_CQ_DEPTH, DLB_MAX_INPUT_QUEUE_DEPTH);
921 if (enqueue_depth < DLB_MIN_ENQUEUE_DEPTH) {
922 DLB_LOG_ERR("dlb: invalid enqueue_depth, must be at least %d\n",
923 DLB_MIN_ENQUEUE_DEPTH);
927 rte_spinlock_lock(&handle->resource_lock);
929 cfg.response = (uintptr_t)&response;
931 /* We round up to the next power of 2 if necessary */
932 cfg.cq_depth = rte_align32pow2(cq_depth);
933 cfg.cq_depth_threshold = rsvd_tokens;
935 cfg.cq_history_list_size = DLB_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
937 /* User controls the LDB high watermark via enqueue depth. The DIR high
938 * watermark is equal, unless the directed credit pool is too small.
940 cfg.ldb_credit_high_watermark = enqueue_depth;
942 /* If there are no directed ports, the kernel driver will ignore this
943 * port's directed credit settings. Don't use enqueue_depth if it would
944 * require more directed credits than are available.
946 cfg.dir_credit_high_watermark =
947 RTE_MIN(enqueue_depth,
948 handle->cfg.num_dir_credits / dlb->num_ports);
950 cfg.ldb_credit_quantum = cfg.ldb_credit_high_watermark / 2;
951 cfg.ldb_credit_low_watermark = RTE_MIN(16, cfg.ldb_credit_quantum);
953 cfg.dir_credit_quantum = cfg.dir_credit_high_watermark / 2;
954 cfg.dir_credit_low_watermark = RTE_MIN(16, cfg.dir_credit_quantum);
958 cfg.ldb_credit_pool_id = handle->cfg.ldb_credit_pool_id;
959 cfg.dir_credit_pool_id = handle->cfg.dir_credit_pool_id;
961 ret = dlb_iface_ldb_port_create(handle, &cfg, dlb->poll_mode);
963 DLB_LOG_ERR("dlb: dlb_ldb_port_create error, ret=%d (driver status: %s)\n",
964 ret, dlb_error_strings[response.status]);
968 qm_port_id = response.id;
970 DLB_LOG_DBG("dlb: ev_port %d uses qm LB port %d <<<<<\n",
971 ev_port->id, qm_port_id);
973 qm_port = &ev_port->qm_port;
974 qm_port->ev_port = ev_port; /* back ptr */
975 qm_port->dlb = dlb; /* back ptr */
978 * Allocate and init local qe struct(s).
979 * Note: MOVDIR64 requires the enqueue QE (qe4) to be aligned.
982 snprintf(mz_name, sizeof(mz_name), "ldb_port%d",
985 ret = dlb_init_qe_mem(qm_port, mz_name);
987 DLB_LOG_ERR("dlb: init_qe_mem failed, ret=%d\n", ret);
991 qm_port->pp_mmio_base = DLB_LDB_PP_BASE + PAGE_SIZE * qm_port_id;
992 qm_port->id = qm_port_id;
994 /* The credit window is one high water mark of QEs */
995 qm_port->ldb_pushcount_at_credit_expiry = 0;
996 qm_port->cached_ldb_credits = cfg.ldb_credit_high_watermark;
997 /* The credit window is one high water mark of QEs */
998 qm_port->dir_pushcount_at_credit_expiry = 0;
999 qm_port->cached_dir_credits = cfg.dir_credit_high_watermark;
1000 qm_port->cq_depth = cfg.cq_depth;
1001 /* CQs with depth < 8 use an 8-entry queue, but withhold credits so
1002 * the effective depth is smaller.
1004 qm_port->cq_depth = cfg.cq_depth <= 8 ? 8 : cfg.cq_depth;
1005 qm_port->cq_idx = 0;
1006 qm_port->cq_idx_unmasked = 0;
1007 if (dlb->poll_mode == DLB_CQ_POLL_MODE_SPARSE)
1008 qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
1010 qm_port->cq_depth_mask = qm_port->cq_depth - 1;
1012 qm_port->gen_bit_shift = __builtin_popcount(qm_port->cq_depth_mask);
1013 /* starting value of gen bit - it toggles at wrap time */
1014 qm_port->gen_bit = 1;
1016 qm_port->use_rsvd_token_scheme = use_rsvd_token_scheme;
1017 qm_port->cq_rsvd_token_deficit = rsvd_tokens;
1018 qm_port->int_armed = false;
1020 /* Save off for later use in info and lookup APIs. */
1021 qm_port->qid_mappings = &dlb->qm_ldb_to_ev_queue_id[0];
1023 qm_port->dequeue_depth = dequeue_depth;
1025 /* When using the reserved token scheme, token_pop_thresh is
1026 * initially 2 * dequeue_depth. Once the tokens are reserved,
1027 * the enqueue code re-assigns it to dequeue_depth.
1029 qm_port->token_pop_thresh = cq_depth;
1031 /* When the deferred scheduling vdev arg is selected, use deferred pop
1032 * for all single-entry CQs.
1034 if (cfg.cq_depth == 1 || (cfg.cq_depth == 2 && use_rsvd_token_scheme)) {
1035 if (dlb->defer_sched)
1036 qm_port->token_pop_mode = DEFERRED_POP;
1039 /* The default enqueue functions do not include delayed-pop support for
1040 * performance reasons.
1042 if (qm_port->token_pop_mode == DELAYED_POP) {
1043 dlb->event_dev->enqueue = dlb_event_enqueue_delayed;
1044 dlb->event_dev->enqueue_burst =
1045 dlb_event_enqueue_burst_delayed;
1046 dlb->event_dev->enqueue_new_burst =
1047 dlb_event_enqueue_new_burst_delayed;
1048 dlb->event_dev->enqueue_forward_burst =
1049 dlb_event_enqueue_forward_burst_delayed;
1052 qm_port->owed_tokens = 0;
1053 qm_port->issued_releases = 0;
1056 qm_port->state = PORT_STARTED; /* enabled at create time */
1057 qm_port->config_state = DLB_CONFIGURED;
1059 qm_port->dir_credits = cfg.dir_credit_high_watermark;
1060 qm_port->ldb_credits = cfg.ldb_credit_high_watermark;
1062 DLB_LOG_DBG("dlb: created ldb port %d, depth = %d, ldb credits=%d, dir credits=%d\n",
1065 qm_port->ldb_credits,
1066 qm_port->dir_credits);
1068 rte_spinlock_unlock(&handle->resource_lock);
1074 dlb_free_qe_mem(qm_port);
1075 qm_port->pp_mmio_base = 0;
1078 rte_spinlock_unlock(&handle->resource_lock);
1080 DLB_LOG_ERR("dlb: create ldb port failed!\n");
1086 dlb_hw_create_dir_port(struct dlb_eventdev *dlb,
1087 struct dlb_eventdev_port *ev_port,
1088 uint32_t dequeue_depth,
1090 uint32_t enqueue_depth,
1091 uint16_t rsvd_tokens,
1092 bool use_rsvd_token_scheme)
1094 struct dlb_hw_dev *handle = &dlb->qm_instance;
1095 struct dlb_create_dir_port_args cfg = {0};
1096 struct dlb_cmd_response response = {0};
1098 struct dlb_port *qm_port = NULL;
1099 char mz_name[RTE_MEMZONE_NAMESIZE];
1100 uint32_t qm_port_id;
1102 if (dlb == NULL || handle == NULL)
1105 if (cq_depth < DLB_MIN_DIR_CQ_DEPTH) {
1106 DLB_LOG_ERR("dlb: invalid cq_depth, must be at least %d\n",
1107 DLB_MIN_DIR_CQ_DEPTH);
1111 if (enqueue_depth < DLB_MIN_ENQUEUE_DEPTH) {
1112 DLB_LOG_ERR("dlb: invalid enqueue_depth, must be at least %d\n",
1113 DLB_MIN_ENQUEUE_DEPTH);
1117 rte_spinlock_lock(&handle->resource_lock);
1119 /* Directed queues are configured at link time. */
1122 cfg.response = (uintptr_t)&response;
1124 /* We round up to the next power of 2 if necessary */
1125 cfg.cq_depth = rte_align32pow2(cq_depth);
1126 cfg.cq_depth_threshold = rsvd_tokens;
1128 /* User controls the LDB high watermark via enqueue depth. The DIR high
1129 * watermark is equal, unless the directed credit pool is too small.
1131 cfg.ldb_credit_high_watermark = enqueue_depth;
1133 /* Don't use enqueue_depth if it would require more directed credits
1134 * than are available.
1136 cfg.dir_credit_high_watermark =
1137 RTE_MIN(enqueue_depth,
1138 handle->cfg.num_dir_credits / dlb->num_ports);
1140 cfg.ldb_credit_quantum = cfg.ldb_credit_high_watermark / 2;
1141 cfg.ldb_credit_low_watermark = RTE_MIN(16, cfg.ldb_credit_quantum);
1143 cfg.dir_credit_quantum = cfg.dir_credit_high_watermark / 2;
1144 cfg.dir_credit_low_watermark = RTE_MIN(16, cfg.dir_credit_quantum);
1148 cfg.ldb_credit_pool_id = handle->cfg.ldb_credit_pool_id;
1149 cfg.dir_credit_pool_id = handle->cfg.dir_credit_pool_id;
1151 ret = dlb_iface_dir_port_create(handle, &cfg, dlb->poll_mode);
1153 DLB_LOG_ERR("dlb: dlb_dir_port_create error, ret=%d (driver status: %s)\n",
1154 ret, dlb_error_strings[response.status]);
1158 qm_port_id = response.id;
1160 DLB_LOG_DBG("dlb: ev_port %d uses qm DIR port %d <<<<<\n",
1161 ev_port->id, qm_port_id);
1163 qm_port = &ev_port->qm_port;
1164 qm_port->ev_port = ev_port; /* back ptr */
1165 qm_port->dlb = dlb; /* back ptr */
1168 * Init local qe struct(s).
1169 * Note: MOVDIR64 requires the enqueue QE to be aligned
1172 snprintf(mz_name, sizeof(mz_name), "dir_port%d",
1175 ret = dlb_init_qe_mem(qm_port, mz_name);
1178 DLB_LOG_ERR("dlb: init_qe_mem failed, ret=%d\n", ret);
1182 qm_port->pp_mmio_base = DLB_DIR_PP_BASE + PAGE_SIZE * qm_port_id;
1183 qm_port->id = qm_port_id;
1185 /* The credit window is one high water mark of QEs */
1186 qm_port->ldb_pushcount_at_credit_expiry = 0;
1187 qm_port->cached_ldb_credits = cfg.ldb_credit_high_watermark;
1188 /* The credit window is one high water mark of QEs */
1189 qm_port->dir_pushcount_at_credit_expiry = 0;
1190 qm_port->cached_dir_credits = cfg.dir_credit_high_watermark;
1191 qm_port->cq_depth = cfg.cq_depth;
1192 qm_port->cq_idx = 0;
1193 qm_port->cq_idx_unmasked = 0;
1194 if (dlb->poll_mode == DLB_CQ_POLL_MODE_SPARSE)
1195 qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
1197 qm_port->cq_depth_mask = cfg.cq_depth - 1;
1199 qm_port->gen_bit_shift = __builtin_popcount(qm_port->cq_depth_mask);
1200 /* starting value of gen bit - it toggles at wrap time */
1201 qm_port->gen_bit = 1;
1203 qm_port->use_rsvd_token_scheme = use_rsvd_token_scheme;
1204 qm_port->cq_rsvd_token_deficit = rsvd_tokens;
1205 qm_port->int_armed = false;
1207 /* Save off for later use in info and lookup APIs. */
1208 qm_port->qid_mappings = &dlb->qm_dir_to_ev_queue_id[0];
1210 qm_port->dequeue_depth = dequeue_depth;
1212 /* Directed ports are auto-pop, by default. */
1213 qm_port->token_pop_mode = AUTO_POP;
1214 qm_port->owed_tokens = 0;
1215 qm_port->issued_releases = 0;
1218 qm_port->state = PORT_STARTED; /* enabled at create time */
1219 qm_port->config_state = DLB_CONFIGURED;
1221 qm_port->dir_credits = cfg.dir_credit_high_watermark;
1222 qm_port->ldb_credits = cfg.ldb_credit_high_watermark;
1224 DLB_LOG_DBG("dlb: created dir port %d, depth = %d cr=%d,%d\n",
1227 cfg.dir_credit_high_watermark,
1228 cfg.ldb_credit_high_watermark);
1230 rte_spinlock_unlock(&handle->resource_lock);
1236 qm_port->pp_mmio_base = 0;
1237 dlb_free_qe_mem(qm_port);
1240 rte_spinlock_unlock(&handle->resource_lock);
1242 DLB_LOG_ERR("dlb: create dir port failed!\n");
1248 dlb_hw_create_ldb_queue(struct dlb_eventdev *dlb,
1249 struct dlb_queue *queue,
1250 const struct rte_event_queue_conf *evq_conf)
1252 struct dlb_hw_dev *handle = &dlb->qm_instance;
1253 struct dlb_create_ldb_queue_args cfg;
1254 struct dlb_cmd_response response;
1257 int sched_type = -1;
1259 if (evq_conf == NULL)
1262 if (evq_conf->event_queue_cfg & RTE_EVENT_QUEUE_CFG_ALL_TYPES) {
1263 if (evq_conf->nb_atomic_order_sequences != 0)
1264 sched_type = RTE_SCHED_TYPE_ORDERED;
1266 sched_type = RTE_SCHED_TYPE_PARALLEL;
1268 sched_type = evq_conf->schedule_type;
1270 cfg.response = (uintptr_t)&response;
1271 cfg.num_atomic_inflights = dlb->num_atm_inflights_per_queue;
1272 cfg.num_sequence_numbers = evq_conf->nb_atomic_order_sequences;
1273 cfg.num_qid_inflights = evq_conf->nb_atomic_order_sequences;
1275 if (sched_type != RTE_SCHED_TYPE_ORDERED) {
1276 cfg.num_sequence_numbers = 0;
1277 cfg.num_qid_inflights = DLB_DEF_UNORDERED_QID_INFLIGHTS;
1280 ret = dlb_iface_ldb_queue_create(handle, &cfg);
1282 DLB_LOG_ERR("dlb: create LB event queue error, ret=%d (driver status: %s)\n",
1283 ret, dlb_error_strings[response.status]);
1287 qm_qid = response.id;
1289 /* Save off queue config for debug, resource lookups, and reconfig */
1290 queue->num_qid_inflights = cfg.num_qid_inflights;
1291 queue->num_atm_inflights = cfg.num_atomic_inflights;
1293 queue->sched_type = sched_type;
1294 queue->config_state = DLB_CONFIGURED;
1296 DLB_LOG_DBG("Created LB event queue %d, nb_inflights=%d, nb_seq=%d, qid inflights=%d\n",
1298 cfg.num_atomic_inflights,
1299 cfg.num_sequence_numbers,
1300 cfg.num_qid_inflights);
1306 dlb_get_sn_allocation(struct dlb_eventdev *dlb, int group)
1308 struct dlb_hw_dev *handle = &dlb->qm_instance;
1309 struct dlb_get_sn_allocation_args cfg;
1310 struct dlb_cmd_response response;
1314 cfg.response = (uintptr_t)&response;
1316 ret = dlb_iface_get_sn_allocation(handle, &cfg);
1318 DLB_LOG_ERR("dlb: get_sn_allocation ret=%d (driver status: %s)\n",
1319 ret, dlb_error_strings[response.status]);
1327 dlb_set_sn_allocation(struct dlb_eventdev *dlb, int group, int num)
1329 struct dlb_hw_dev *handle = &dlb->qm_instance;
1330 struct dlb_set_sn_allocation_args cfg;
1331 struct dlb_cmd_response response;
1336 cfg.response = (uintptr_t)&response;
1338 ret = dlb_iface_set_sn_allocation(handle, &cfg);
1340 DLB_LOG_ERR("dlb: set_sn_allocation ret=%d (driver status: %s)\n",
1341 ret, dlb_error_strings[response.status]);
1349 dlb_get_sn_occupancy(struct dlb_eventdev *dlb, int group)
1351 struct dlb_hw_dev *handle = &dlb->qm_instance;
1352 struct dlb_get_sn_occupancy_args cfg;
1353 struct dlb_cmd_response response;
1357 cfg.response = (uintptr_t)&response;
1359 ret = dlb_iface_get_sn_occupancy(handle, &cfg);
1361 DLB_LOG_ERR("dlb: get_sn_occupancy ret=%d (driver status: %s)\n",
1362 ret, dlb_error_strings[response.status]);
1369 /* Query the current sequence number allocations and, if they conflict with the
1370 * requested LDB queue configuration, attempt to re-allocate sequence numbers.
1371 * This is best-effort; if it fails, the PMD will attempt to configure the
1372 * load-balanced queue and return an error.
1375 dlb_program_sn_allocation(struct dlb_eventdev *dlb,
1376 const struct rte_event_queue_conf *queue_conf)
1378 int grp_occupancy[DLB_NUM_SN_GROUPS];
1379 int grp_alloc[DLB_NUM_SN_GROUPS];
1380 int i, sequence_numbers;
1382 sequence_numbers = (int)queue_conf->nb_atomic_order_sequences;
1384 for (i = 0; i < DLB_NUM_SN_GROUPS; i++) {
1387 grp_alloc[i] = dlb_get_sn_allocation(dlb, i);
1388 if (grp_alloc[i] < 0)
1391 total_slots = DLB_MAX_LDB_SN_ALLOC / grp_alloc[i];
1393 grp_occupancy[i] = dlb_get_sn_occupancy(dlb, i);
1394 if (grp_occupancy[i] < 0)
1397 /* DLB has at least one available slot for the requested
1398 * sequence numbers, so no further configuration required.
1400 if (grp_alloc[i] == sequence_numbers &&
1401 grp_occupancy[i] < total_slots)
1405 /* None of the sequence number groups are configured for the requested
1406 * sequence numbers, so we have to reconfigure one of them. This is
1407 * only possible if a group is not in use.
1409 for (i = 0; i < DLB_NUM_SN_GROUPS; i++) {
1410 if (grp_occupancy[i] == 0)
1414 if (i == DLB_NUM_SN_GROUPS) {
1415 DLB_LOG_ERR("[%s()] No groups with %d sequence_numbers are available or have free slots\n",
1416 __func__, sequence_numbers);
1420 /* Attempt to configure slot i with the requested number of sequence
1421 * numbers. Ignore the return value -- if this fails, the error will be
1422 * caught during subsequent queue configuration.
1424 dlb_set_sn_allocation(dlb, i, sequence_numbers);
1428 dlb_eventdev_ldb_queue_setup(struct rte_eventdev *dev,
1429 struct dlb_eventdev_queue *ev_queue,
1430 const struct rte_event_queue_conf *queue_conf)
1432 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
1435 if (queue_conf->nb_atomic_order_sequences)
1436 dlb_program_sn_allocation(dlb, queue_conf);
1438 qm_qid = dlb_hw_create_ldb_queue(dlb,
1439 &ev_queue->qm_queue,
1442 DLB_LOG_ERR("Failed to create the load-balanced queue\n");
1447 dlb->qm_ldb_to_ev_queue_id[qm_qid] = ev_queue->id;
1449 ev_queue->qm_queue.id = qm_qid;
1454 static int dlb_num_dir_queues_setup(struct dlb_eventdev *dlb)
1458 for (i = 0; i < dlb->num_queues; i++) {
1459 if (dlb->ev_queues[i].setup_done &&
1460 dlb->ev_queues[i].qm_queue.is_directed)
1468 dlb_queue_link_teardown(struct dlb_eventdev *dlb,
1469 struct dlb_eventdev_queue *ev_queue)
1471 struct dlb_eventdev_port *ev_port;
1474 for (i = 0; i < dlb->num_ports; i++) {
1475 ev_port = &dlb->ev_ports[i];
1477 for (j = 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++) {
1478 if (!ev_port->link[j].valid ||
1479 ev_port->link[j].queue_id != ev_queue->id)
1482 ev_port->link[j].valid = false;
1483 ev_port->num_links--;
1487 ev_queue->num_links = 0;
1491 dlb_eventdev_queue_setup(struct rte_eventdev *dev,
1493 const struct rte_event_queue_conf *queue_conf)
1495 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
1496 struct dlb_eventdev_queue *ev_queue;
1499 if (queue_conf == NULL)
1502 if (ev_qid >= dlb->num_queues)
1505 ev_queue = &dlb->ev_queues[ev_qid];
1507 ev_queue->qm_queue.is_directed = queue_conf->event_queue_cfg &
1508 RTE_EVENT_QUEUE_CFG_SINGLE_LINK;
1509 ev_queue->id = ev_qid;
1510 ev_queue->conf = *queue_conf;
1512 if (!ev_queue->qm_queue.is_directed) {
1513 ret = dlb_eventdev_ldb_queue_setup(dev, ev_queue, queue_conf);
1515 /* The directed queue isn't setup until link time, at which
1516 * point we know its directed port ID. Directed queue setup
1517 * will only fail if this queue is already setup or there are
1518 * no directed queues left to configure.
1522 ev_queue->qm_queue.config_state = DLB_NOT_CONFIGURED;
1524 if (ev_queue->setup_done ||
1525 dlb_num_dir_queues_setup(dlb) == dlb->num_dir_queues)
1529 /* Tear down pre-existing port->queue links */
1530 if (!ret && dlb->run_state == DLB_RUN_STATE_STOPPED)
1531 dlb_queue_link_teardown(dlb, ev_queue);
1534 ev_queue->setup_done = true;
1540 dlb_port_link_teardown(struct dlb_eventdev *dlb,
1541 struct dlb_eventdev_port *ev_port)
1543 struct dlb_eventdev_queue *ev_queue;
1546 for (i = 0; i < DLB_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
1547 if (!ev_port->link[i].valid)
1550 ev_queue = &dlb->ev_queues[ev_port->link[i].queue_id];
1552 ev_port->link[i].valid = false;
1553 ev_port->num_links--;
1554 ev_queue->num_links--;
1559 dlb_eventdev_port_setup(struct rte_eventdev *dev,
1561 const struct rte_event_port_conf *port_conf)
1563 struct dlb_eventdev *dlb;
1564 struct dlb_eventdev_port *ev_port;
1565 bool use_rsvd_token_scheme;
1566 uint32_t adj_cq_depth;
1567 uint16_t rsvd_tokens;
1570 if (dev == NULL || port_conf == NULL) {
1571 DLB_LOG_ERR("Null parameter\n");
1575 dlb = dlb_pmd_priv(dev);
1577 if (ev_port_id >= DLB_MAX_NUM_PORTS)
1580 if (port_conf->dequeue_depth >
1581 evdev_dlb_default_info.max_event_port_dequeue_depth ||
1582 port_conf->enqueue_depth >
1583 evdev_dlb_default_info.max_event_port_enqueue_depth)
1586 ev_port = &dlb->ev_ports[ev_port_id];
1588 if (ev_port->setup_done) {
1589 DLB_LOG_ERR("evport %d is already configured\n", ev_port_id);
1593 /* The reserved token interrupt arming scheme requires that one or more
1594 * CQ tokens be reserved by the PMD. This limits the amount of CQ space
1595 * usable by the DLB, so in order to give an *effective* CQ depth equal
1596 * to the user-requested value, we double CQ depth and reserve half of
1597 * its tokens. If the user requests the max CQ depth (256) then we
1598 * cannot double it, so we reserve one token and give an effective
1599 * depth of 255 entries.
1601 use_rsvd_token_scheme = true;
1603 adj_cq_depth = port_conf->dequeue_depth;
1605 if (use_rsvd_token_scheme && adj_cq_depth < 256) {
1606 rsvd_tokens = adj_cq_depth;
1610 ev_port->qm_port.is_directed = port_conf->event_port_cfg &
1611 RTE_EVENT_PORT_CFG_SINGLE_LINK;
1613 if (!ev_port->qm_port.is_directed) {
1614 ret = dlb_hw_create_ldb_port(dlb,
1616 port_conf->dequeue_depth,
1618 port_conf->enqueue_depth,
1620 use_rsvd_token_scheme);
1622 DLB_LOG_ERR("Failed to create the lB port ve portId=%d\n",
1627 ret = dlb_hw_create_dir_port(dlb,
1629 port_conf->dequeue_depth,
1631 port_conf->enqueue_depth,
1633 use_rsvd_token_scheme);
1635 DLB_LOG_ERR("Failed to create the DIR port\n");
1640 /* Save off port config for reconfig */
1641 dlb->ev_ports[ev_port_id].conf = *port_conf;
1643 dlb->ev_ports[ev_port_id].id = ev_port_id;
1644 dlb->ev_ports[ev_port_id].enq_configured = true;
1645 dlb->ev_ports[ev_port_id].setup_done = true;
1646 dlb->ev_ports[ev_port_id].inflight_max =
1647 port_conf->new_event_threshold;
1648 dlb->ev_ports[ev_port_id].implicit_release =
1649 !(port_conf->event_port_cfg &
1650 RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL);
1651 dlb->ev_ports[ev_port_id].outstanding_releases = 0;
1652 dlb->ev_ports[ev_port_id].inflight_credits = 0;
1653 dlb->ev_ports[ev_port_id].credit_update_quanta =
1654 RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA;
1655 dlb->ev_ports[ev_port_id].dlb = dlb; /* reverse link */
1657 /* Tear down pre-existing port->queue links */
1658 if (dlb->run_state == DLB_RUN_STATE_STOPPED)
1659 dlb_port_link_teardown(dlb, &dlb->ev_ports[ev_port_id]);
1661 dev->data->ports[ev_port_id] = &dlb->ev_ports[ev_port_id];
1667 dlb_eventdev_reapply_configuration(struct rte_eventdev *dev)
1669 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
1672 /* If an event queue or port was previously configured, but hasn't been
1673 * reconfigured, reapply its original configuration.
1675 for (i = 0; i < dlb->num_queues; i++) {
1676 struct dlb_eventdev_queue *ev_queue;
1678 ev_queue = &dlb->ev_queues[i];
1680 if (ev_queue->qm_queue.config_state != DLB_PREV_CONFIGURED)
1683 ret = dlb_eventdev_queue_setup(dev, i, &ev_queue->conf);
1685 DLB_LOG_ERR("dlb: failed to reconfigure queue %d", i);
1690 for (i = 0; i < dlb->num_ports; i++) {
1691 struct dlb_eventdev_port *ev_port = &dlb->ev_ports[i];
1693 if (ev_port->qm_port.config_state != DLB_PREV_CONFIGURED)
1696 ret = dlb_eventdev_port_setup(dev, i, &ev_port->conf);
1698 DLB_LOG_ERR("dlb: failed to reconfigure ev_port %d",
1708 set_dev_id(const char *key __rte_unused,
1712 int *dev_id = opaque;
1715 if (value == NULL || opaque == NULL) {
1716 DLB_LOG_ERR("NULL pointer\n");
1720 ret = dlb_string_to_int(dev_id, value);
1728 set_defer_sched(const char *key __rte_unused,
1732 int *defer_sched = opaque;
1734 if (value == NULL || opaque == NULL) {
1735 DLB_LOG_ERR("NULL pointer\n");
1739 if (strncmp(value, "on", 2) != 0) {
1740 DLB_LOG_ERR("Invalid defer_sched argument \"%s\" (expected \"on\")\n",
1751 set_num_atm_inflights(const char *key __rte_unused,
1755 int *num_atm_inflights = opaque;
1758 if (value == NULL || opaque == NULL) {
1759 DLB_LOG_ERR("NULL pointer\n");
1763 ret = dlb_string_to_int(num_atm_inflights, value);
1767 if (*num_atm_inflights < 0 ||
1768 *num_atm_inflights > DLB_MAX_NUM_ATM_INFLIGHTS) {
1769 DLB_LOG_ERR("dlb: atm_inflights must be between 0 and %d\n",
1770 DLB_MAX_NUM_ATM_INFLIGHTS);
1778 dlb_validate_port_link(struct dlb_eventdev_port *ev_port,
1783 struct dlb_eventdev *dlb = ev_port->dlb;
1784 struct dlb_eventdev_queue *ev_queue;
1785 bool port_is_dir, queue_is_dir;
1787 if (queue_id > dlb->num_queues) {
1788 DLB_LOG_ERR("queue_id %d > num queues %d\n",
1789 queue_id, dlb->num_queues);
1790 rte_errno = -EINVAL;
1794 ev_queue = &dlb->ev_queues[queue_id];
1796 if (!ev_queue->setup_done &&
1797 ev_queue->qm_queue.config_state != DLB_PREV_CONFIGURED) {
1798 DLB_LOG_ERR("setup not done and not previously configured\n");
1799 rte_errno = -EINVAL;
1803 port_is_dir = ev_port->qm_port.is_directed;
1804 queue_is_dir = ev_queue->qm_queue.is_directed;
1806 if (port_is_dir != queue_is_dir) {
1807 DLB_LOG_ERR("%s queue %u can't link to %s port %u\n",
1808 queue_is_dir ? "DIR" : "LDB", ev_queue->id,
1809 port_is_dir ? "DIR" : "LDB", ev_port->id);
1811 rte_errno = -EINVAL;
1815 /* Check if there is space for the requested link */
1816 if (!link_exists && index == -1) {
1817 DLB_LOG_ERR("no space for new link\n");
1818 rte_errno = -ENOSPC;
1822 /* Check if the directed port is already linked */
1823 if (ev_port->qm_port.is_directed && ev_port->num_links > 0 &&
1825 DLB_LOG_ERR("Can't link DIR port %d to >1 queues\n",
1827 rte_errno = -EINVAL;
1831 /* Check if the directed queue is already linked */
1832 if (ev_queue->qm_queue.is_directed && ev_queue->num_links > 0 &&
1834 DLB_LOG_ERR("Can't link DIR queue %d to >1 ports\n",
1836 rte_errno = -EINVAL;
1844 dlb_hw_create_dir_queue(struct dlb_eventdev *dlb, int32_t qm_port_id)
1846 struct dlb_hw_dev *handle = &dlb->qm_instance;
1847 struct dlb_create_dir_queue_args cfg;
1848 struct dlb_cmd_response response;
1851 cfg.response = (uintptr_t)&response;
1853 /* The directed port is always configured before its queue */
1854 cfg.port_id = qm_port_id;
1856 ret = dlb_iface_dir_queue_create(handle, &cfg);
1858 DLB_LOG_ERR("dlb: create DIR event queue error, ret=%d (driver status: %s)\n",
1859 ret, dlb_error_strings[response.status]);
1867 dlb_eventdev_dir_queue_setup(struct dlb_eventdev *dlb,
1868 struct dlb_eventdev_queue *ev_queue,
1869 struct dlb_eventdev_port *ev_port)
1873 qm_qid = dlb_hw_create_dir_queue(dlb, ev_port->qm_port.id);
1876 DLB_LOG_ERR("Failed to create the DIR queue\n");
1880 dlb->qm_dir_to_ev_queue_id[qm_qid] = ev_queue->id;
1882 ev_queue->qm_queue.id = qm_qid;
1888 dlb_hw_map_ldb_qid_to_port(struct dlb_hw_dev *handle,
1889 uint32_t qm_port_id,
1893 struct dlb_map_qid_args cfg;
1894 struct dlb_cmd_response response;
1901 cfg.response = (uintptr_t)&response;
1902 cfg.port_id = qm_port_id;
1904 cfg.priority = EV_TO_DLB_PRIO(priority);
1906 ret = dlb_iface_map_qid(handle, &cfg);
1908 DLB_LOG_ERR("dlb: map qid error, ret=%d (driver status: %s)\n",
1909 ret, dlb_error_strings[response.status]);
1910 DLB_LOG_ERR("dlb: device_id=%d grp=%d, qm_port=%d, qm_qid=%d prio=%d\n",
1912 handle->domain_id, cfg.port_id,
1916 DLB_LOG_DBG("dlb: mapped queue %d to qm_port %d\n",
1917 qm_qid, qm_port_id);
1924 dlb_event_queue_join_ldb(struct dlb_eventdev *dlb,
1925 struct dlb_eventdev_port *ev_port,
1926 struct dlb_eventdev_queue *ev_queue,
1929 int first_avail = -1;
1932 for (i = 0; i < DLB_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
1933 if (ev_port->link[i].valid) {
1934 if (ev_port->link[i].queue_id == ev_queue->id &&
1935 ev_port->link[i].priority == priority) {
1936 if (ev_port->link[i].mapped)
1937 return 0; /* already mapped */
1941 if (first_avail == -1)
1945 if (first_avail == -1) {
1946 DLB_LOG_ERR("dlb: qm_port %d has no available QID slots.\n",
1947 ev_port->qm_port.id);
1951 ret = dlb_hw_map_ldb_qid_to_port(&dlb->qm_instance,
1952 ev_port->qm_port.id,
1953 ev_queue->qm_queue.id,
1957 ev_port->link[first_avail].mapped = true;
1963 dlb_do_port_link(struct rte_eventdev *dev,
1964 struct dlb_eventdev_queue *ev_queue,
1965 struct dlb_eventdev_port *ev_port,
1968 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
1971 /* Don't link until start time. */
1972 if (dlb->run_state == DLB_RUN_STATE_STOPPED)
1975 if (ev_queue->qm_queue.is_directed)
1976 err = dlb_eventdev_dir_queue_setup(dlb, ev_queue, ev_port);
1978 err = dlb_event_queue_join_ldb(dlb, ev_port, ev_queue, prio);
1981 DLB_LOG_ERR("port link failure for %s ev_q %d, ev_port %d\n",
1982 ev_queue->qm_queue.is_directed ? "DIR" : "LDB",
1983 ev_queue->id, ev_port->id);
1993 dlb_eventdev_apply_port_links(struct rte_eventdev *dev)
1995 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
1998 /* Perform requested port->queue links */
1999 for (i = 0; i < dlb->num_ports; i++) {
2000 struct dlb_eventdev_port *ev_port = &dlb->ev_ports[i];
2003 for (j = 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++) {
2004 struct dlb_eventdev_queue *ev_queue;
2005 uint8_t prio, queue_id;
2007 if (!ev_port->link[j].valid)
2010 prio = ev_port->link[j].priority;
2011 queue_id = ev_port->link[j].queue_id;
2013 if (dlb_validate_port_link(ev_port, queue_id, true, j))
2016 ev_queue = &dlb->ev_queues[queue_id];
2018 if (dlb_do_port_link(dev, ev_queue, ev_port, prio))
2027 dlb_eventdev_port_link(struct rte_eventdev *dev, void *event_port,
2028 const uint8_t queues[], const uint8_t priorities[],
2032 struct dlb_eventdev_port *ev_port = event_port;
2033 struct dlb_eventdev *dlb;
2038 if (ev_port == NULL) {
2039 DLB_LOG_ERR("dlb: evport not setup\n");
2040 rte_errno = -EINVAL;
2044 if (!ev_port->setup_done &&
2045 ev_port->qm_port.config_state != DLB_PREV_CONFIGURED) {
2046 DLB_LOG_ERR("dlb: evport not setup\n");
2047 rte_errno = -EINVAL;
2051 /* Note: rte_event_port_link() ensures the PMD won't receive a NULL
2054 if (nb_links == 0) {
2055 DLB_LOG_DBG("dlb: nb_links is 0\n");
2056 return 0; /* Ignore and return success */
2061 DLB_LOG_DBG("Linking %u queues to %s port %d\n",
2063 ev_port->qm_port.is_directed ? "DIR" : "LDB",
2066 for (i = 0; i < nb_links; i++) {
2067 struct dlb_eventdev_queue *ev_queue;
2068 uint8_t queue_id, prio;
2072 queue_id = queues[i];
2073 prio = priorities[i];
2075 /* Check if the link already exists. */
2076 for (j = 0; j < DLB_MAX_NUM_QIDS_PER_LDB_CQ; j++)
2077 if (ev_port->link[j].valid) {
2078 if (ev_port->link[j].queue_id == queue_id) {
2088 /* could not link */
2092 /* Check if already linked at the requested priority */
2093 if (found && ev_port->link[j].priority == prio)
2096 if (dlb_validate_port_link(ev_port, queue_id, found, index))
2097 break; /* return index of offending queue */
2099 ev_queue = &dlb->ev_queues[queue_id];
2101 if (dlb_do_port_link(dev, ev_queue, ev_port, prio))
2102 break; /* return index of offending queue */
2104 ev_queue->num_links++;
2106 ev_port->link[index].queue_id = queue_id;
2107 ev_port->link[index].priority = prio;
2108 ev_port->link[index].valid = true;
2109 /* Entry already exists? If so, then must be prio change */
2111 ev_port->num_links++;
2117 dlb_eventdev_start(struct rte_eventdev *dev)
2119 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
2120 struct dlb_hw_dev *handle = &dlb->qm_instance;
2121 struct dlb_start_domain_args cfg;
2122 struct dlb_cmd_response response;
2125 rte_spinlock_lock(&dlb->qm_instance.resource_lock);
2126 if (dlb->run_state != DLB_RUN_STATE_STOPPED) {
2127 DLB_LOG_ERR("bad state %d for dev_start\n",
2128 (int)dlb->run_state);
2129 rte_spinlock_unlock(&dlb->qm_instance.resource_lock);
2132 dlb->run_state = DLB_RUN_STATE_STARTING;
2133 rte_spinlock_unlock(&dlb->qm_instance.resource_lock);
2135 /* If the device was configured more than once, some event ports and/or
2136 * queues may need to be reconfigured.
2138 ret = dlb_eventdev_reapply_configuration(dev);
2142 /* The DLB PMD delays port links until the device is started. */
2143 ret = dlb_eventdev_apply_port_links(dev);
2147 cfg.response = (uintptr_t)&response;
2149 for (i = 0; i < dlb->num_ports; i++) {
2150 if (!dlb->ev_ports[i].setup_done) {
2151 DLB_LOG_ERR("dlb: port %d not setup", i);
2156 for (i = 0; i < dlb->num_queues; i++) {
2157 if (dlb->ev_queues[i].num_links == 0) {
2158 DLB_LOG_ERR("dlb: queue %d is not linked", i);
2163 ret = dlb_iface_sched_domain_start(handle, &cfg);
2165 DLB_LOG_ERR("dlb: sched_domain_start ret=%d (driver status: %s)\n",
2166 ret, dlb_error_strings[response.status]);
2170 dlb->run_state = DLB_RUN_STATE_STARTED;
2171 DLB_LOG_DBG("dlb: sched_domain_start completed OK\n");
2177 dlb_check_enqueue_sw_credits(struct dlb_eventdev *dlb,
2178 struct dlb_eventdev_port *ev_port)
2180 uint32_t sw_inflights = __atomic_load_n(&dlb->inflights,
2184 if (unlikely(ev_port->inflight_max < sw_inflights)) {
2185 DLB_INC_STAT(ev_port->stats.traffic.tx_nospc_inflight_max, 1);
2186 rte_errno = -ENOSPC;
2190 if (ev_port->inflight_credits < num) {
2191 /* check if event enqueue brings ev_port over max threshold */
2192 uint32_t credit_update_quanta = ev_port->credit_update_quanta;
2194 if (sw_inflights + credit_update_quanta >
2195 dlb->new_event_limit) {
2197 ev_port->stats.traffic.tx_nospc_new_event_limit,
2199 rte_errno = -ENOSPC;
2203 __atomic_fetch_add(&dlb->inflights, credit_update_quanta,
2205 ev_port->inflight_credits += (credit_update_quanta);
2207 if (ev_port->inflight_credits < num) {
2209 ev_port->stats.traffic.tx_nospc_inflight_credits,
2211 rte_errno = -ENOSPC;
2220 dlb_replenish_sw_credits(struct dlb_eventdev *dlb,
2221 struct dlb_eventdev_port *ev_port)
2223 uint16_t quanta = ev_port->credit_update_quanta;
2225 if (ev_port->inflight_credits >= quanta * 2) {
2226 /* Replenish credits, saving one quanta for enqueues */
2227 uint16_t val = ev_port->inflight_credits - quanta;
2229 __atomic_fetch_sub(&dlb->inflights, val, __ATOMIC_SEQ_CST);
2230 ev_port->inflight_credits -= val;
2234 static __rte_always_inline uint16_t
2235 dlb_read_pc(struct process_local_port_data *port_data, bool ldb)
2237 volatile uint16_t *popcount;
2240 popcount = port_data->ldb_popcount;
2242 popcount = port_data->dir_popcount;
2248 dlb_check_enqueue_hw_ldb_credits(struct dlb_port *qm_port,
2249 struct process_local_port_data *port_data)
2251 if (unlikely(qm_port->cached_ldb_credits == 0)) {
2254 pc = dlb_read_pc(port_data, true);
2256 qm_port->cached_ldb_credits = pc -
2257 qm_port->ldb_pushcount_at_credit_expiry;
2258 if (unlikely(qm_port->cached_ldb_credits == 0)) {
2260 qm_port->ev_port->stats.traffic.tx_nospc_ldb_hw_credits,
2263 DLB_LOG_DBG("ldb credits exhausted\n");
2266 qm_port->ldb_pushcount_at_credit_expiry +=
2267 qm_port->cached_ldb_credits;
2274 dlb_check_enqueue_hw_dir_credits(struct dlb_port *qm_port,
2275 struct process_local_port_data *port_data)
2277 if (unlikely(qm_port->cached_dir_credits == 0)) {
2280 pc = dlb_read_pc(port_data, false);
2282 qm_port->cached_dir_credits = pc -
2283 qm_port->dir_pushcount_at_credit_expiry;
2285 if (unlikely(qm_port->cached_dir_credits == 0)) {
2287 qm_port->ev_port->stats.traffic.tx_nospc_dir_hw_credits,
2290 DLB_LOG_DBG("dir credits exhausted\n");
2293 qm_port->dir_pushcount_at_credit_expiry +=
2294 qm_port->cached_dir_credits;
2301 dlb_event_enqueue_prep(struct dlb_eventdev_port *ev_port,
2302 struct dlb_port *qm_port,
2303 const struct rte_event ev[],
2304 struct process_local_port_data *port_data,
2305 uint8_t *sched_type,
2308 struct dlb_eventdev *dlb = ev_port->dlb;
2309 struct dlb_eventdev_queue *ev_queue;
2310 uint16_t *cached_credits = NULL;
2311 struct dlb_queue *qm_queue;
2313 ev_queue = &dlb->ev_queues[ev->queue_id];
2314 qm_queue = &ev_queue->qm_queue;
2315 *queue_id = qm_queue->id;
2317 /* Ignore sched_type and hardware credits on release events */
2318 if (ev->op == RTE_EVENT_OP_RELEASE)
2321 if (!qm_queue->is_directed) {
2322 /* Load balanced destination queue */
2324 if (dlb_check_enqueue_hw_ldb_credits(qm_port, port_data)) {
2325 rte_errno = -ENOSPC;
2328 cached_credits = &qm_port->cached_ldb_credits;
2330 switch (ev->sched_type) {
2331 case RTE_SCHED_TYPE_ORDERED:
2332 DLB_LOG_DBG("dlb: put_qe: RTE_SCHED_TYPE_ORDERED\n");
2333 if (qm_queue->sched_type != RTE_SCHED_TYPE_ORDERED) {
2334 DLB_LOG_ERR("dlb: tried to send ordered event to unordered queue %d\n",
2336 rte_errno = -EINVAL;
2339 *sched_type = DLB_SCHED_ORDERED;
2341 case RTE_SCHED_TYPE_ATOMIC:
2342 DLB_LOG_DBG("dlb: put_qe: RTE_SCHED_TYPE_ATOMIC\n");
2343 *sched_type = DLB_SCHED_ATOMIC;
2345 case RTE_SCHED_TYPE_PARALLEL:
2346 DLB_LOG_DBG("dlb: put_qe: RTE_SCHED_TYPE_PARALLEL\n");
2347 if (qm_queue->sched_type == RTE_SCHED_TYPE_ORDERED)
2348 *sched_type = DLB_SCHED_ORDERED;
2350 *sched_type = DLB_SCHED_UNORDERED;
2353 DLB_LOG_ERR("Unsupported LDB sched type in put_qe\n");
2354 DLB_INC_STAT(ev_port->stats.tx_invalid, 1);
2355 rte_errno = -EINVAL;
2359 /* Directed destination queue */
2361 if (dlb_check_enqueue_hw_dir_credits(qm_port, port_data)) {
2362 rte_errno = -ENOSPC;
2365 cached_credits = &qm_port->cached_dir_credits;
2367 DLB_LOG_DBG("dlb: put_qe: RTE_SCHED_TYPE_DIRECTED\n");
2369 *sched_type = DLB_SCHED_DIRECTED;
2374 case RTE_EVENT_OP_NEW:
2375 /* Check that a sw credit is available */
2376 if (dlb_check_enqueue_sw_credits(dlb, ev_port)) {
2377 rte_errno = -ENOSPC;
2380 ev_port->inflight_credits--;
2381 (*cached_credits)--;
2383 case RTE_EVENT_OP_FORWARD:
2384 /* Check for outstanding_releases underflow. If this occurs,
2385 * the application is not using the EVENT_OPs correctly; for
2386 * example, forwarding or releasing events that were not
2389 RTE_ASSERT(ev_port->outstanding_releases > 0);
2390 ev_port->outstanding_releases--;
2391 qm_port->issued_releases++;
2392 (*cached_credits)--;
2394 case RTE_EVENT_OP_RELEASE:
2395 ev_port->inflight_credits++;
2396 /* Check for outstanding_releases underflow. If this occurs,
2397 * the application is not using the EVENT_OPs correctly; for
2398 * example, forwarding or releasing events that were not
2401 RTE_ASSERT(ev_port->outstanding_releases > 0);
2402 ev_port->outstanding_releases--;
2403 qm_port->issued_releases++;
2404 /* Replenish s/w credits if enough are cached */
2405 dlb_replenish_sw_credits(dlb, ev_port);
2409 DLB_INC_STAT(ev_port->stats.tx_op_cnt[ev->op], 1);
2410 DLB_INC_STAT(ev_port->stats.traffic.tx_ok, 1);
2412 #ifndef RTE_LIBRTE_PMD_DLB_QUELL_STATS
2413 if (ev->op != RTE_EVENT_OP_RELEASE) {
2414 DLB_INC_STAT(ev_port->stats.enq_ok[ev->queue_id], 1);
2415 DLB_INC_STAT(ev_port->stats.tx_sched_cnt[*sched_type], 1);
2422 static uint8_t cmd_byte_map[NUM_DLB_PORT_TYPES][DLB_NUM_HW_SCHED_TYPES] = {
2424 /* Load-balanced cmd bytes */
2425 [RTE_EVENT_OP_NEW] = DLB_NEW_CMD_BYTE,
2426 [RTE_EVENT_OP_FORWARD] = DLB_FWD_CMD_BYTE,
2427 [RTE_EVENT_OP_RELEASE] = DLB_COMP_CMD_BYTE,
2430 /* Directed cmd bytes */
2431 [RTE_EVENT_OP_NEW] = DLB_NEW_CMD_BYTE,
2432 [RTE_EVENT_OP_FORWARD] = DLB_NEW_CMD_BYTE,
2433 [RTE_EVENT_OP_RELEASE] = DLB_NOOP_CMD_BYTE,
2438 dlb_event_build_hcws(struct dlb_port *qm_port,
2439 const struct rte_event ev[],
2441 uint8_t *sched_type,
2444 struct dlb_enqueue_qe *qe;
2445 uint16_t sched_word[4];
2451 sse_qe[0] = _mm_setzero_si128();
2452 sse_qe[1] = _mm_setzero_si128();
2456 /* Construct the metadata portion of two HCWs in one 128b SSE
2457 * register. HCW metadata is constructed in the SSE registers
2459 * sse_qe[0][63:0]: qe[0]'s metadata
2460 * sse_qe[0][127:64]: qe[1]'s metadata
2461 * sse_qe[1][63:0]: qe[2]'s metadata
2462 * sse_qe[1][127:64]: qe[3]'s metadata
2465 /* Convert the event operation into a command byte and store it
2467 * sse_qe[0][63:56] = cmd_byte_map[is_directed][ev[0].op]
2468 * sse_qe[0][127:120] = cmd_byte_map[is_directed][ev[1].op]
2469 * sse_qe[1][63:56] = cmd_byte_map[is_directed][ev[2].op]
2470 * sse_qe[1][127:120] = cmd_byte_map[is_directed][ev[3].op]
2472 #define DLB_QE_CMD_BYTE 7
2473 sse_qe[0] = _mm_insert_epi8(sse_qe[0],
2474 cmd_byte_map[qm_port->is_directed][ev[0].op],
2476 sse_qe[0] = _mm_insert_epi8(sse_qe[0],
2477 cmd_byte_map[qm_port->is_directed][ev[1].op],
2478 DLB_QE_CMD_BYTE + 8);
2479 sse_qe[1] = _mm_insert_epi8(sse_qe[1],
2480 cmd_byte_map[qm_port->is_directed][ev[2].op],
2482 sse_qe[1] = _mm_insert_epi8(sse_qe[1],
2483 cmd_byte_map[qm_port->is_directed][ev[3].op],
2484 DLB_QE_CMD_BYTE + 8);
2486 /* Store priority, scheduling type, and queue ID in the sched
2487 * word array because these values are re-used when the
2488 * destination is a directed queue.
2490 sched_word[0] = EV_TO_DLB_PRIO(ev[0].priority) << 10 |
2491 sched_type[0] << 8 |
2493 sched_word[1] = EV_TO_DLB_PRIO(ev[1].priority) << 10 |
2494 sched_type[1] << 8 |
2496 sched_word[2] = EV_TO_DLB_PRIO(ev[2].priority) << 10 |
2497 sched_type[2] << 8 |
2499 sched_word[3] = EV_TO_DLB_PRIO(ev[3].priority) << 10 |
2500 sched_type[3] << 8 |
2503 /* Store the event priority, scheduling type, and queue ID in
2505 * sse_qe[0][31:16] = sched_word[0]
2506 * sse_qe[0][95:80] = sched_word[1]
2507 * sse_qe[1][31:16] = sched_word[2]
2508 * sse_qe[1][95:80] = sched_word[3]
2510 #define DLB_QE_QID_SCHED_WORD 1
2511 sse_qe[0] = _mm_insert_epi16(sse_qe[0],
2513 DLB_QE_QID_SCHED_WORD);
2514 sse_qe[0] = _mm_insert_epi16(sse_qe[0],
2516 DLB_QE_QID_SCHED_WORD + 4);
2517 sse_qe[1] = _mm_insert_epi16(sse_qe[1],
2519 DLB_QE_QID_SCHED_WORD);
2520 sse_qe[1] = _mm_insert_epi16(sse_qe[1],
2522 DLB_QE_QID_SCHED_WORD + 4);
2524 /* If the destination is a load-balanced queue, store the lock
2525 * ID. If it is a directed queue, DLB places this field in
2526 * bytes 10-11 of the received QE, so we format it accordingly:
2527 * sse_qe[0][47:32] = dir queue ? sched_word[0] : flow_id[0]
2528 * sse_qe[0][111:96] = dir queue ? sched_word[1] : flow_id[1]
2529 * sse_qe[1][47:32] = dir queue ? sched_word[2] : flow_id[2]
2530 * sse_qe[1][111:96] = dir queue ? sched_word[3] : flow_id[3]
2532 #define DLB_QE_LOCK_ID_WORD 2
2533 sse_qe[0] = _mm_insert_epi16(sse_qe[0],
2534 (sched_type[0] == DLB_SCHED_DIRECTED) ?
2535 sched_word[0] : ev[0].flow_id,
2536 DLB_QE_LOCK_ID_WORD);
2537 sse_qe[0] = _mm_insert_epi16(sse_qe[0],
2538 (sched_type[1] == DLB_SCHED_DIRECTED) ?
2539 sched_word[1] : ev[1].flow_id,
2540 DLB_QE_LOCK_ID_WORD + 4);
2541 sse_qe[1] = _mm_insert_epi16(sse_qe[1],
2542 (sched_type[2] == DLB_SCHED_DIRECTED) ?
2543 sched_word[2] : ev[2].flow_id,
2544 DLB_QE_LOCK_ID_WORD);
2545 sse_qe[1] = _mm_insert_epi16(sse_qe[1],
2546 (sched_type[3] == DLB_SCHED_DIRECTED) ?
2547 sched_word[3] : ev[3].flow_id,
2548 DLB_QE_LOCK_ID_WORD + 4);
2550 /* Store the event type and sub event type in the metadata:
2551 * sse_qe[0][15:0] = flow_id[0]
2552 * sse_qe[0][79:64] = flow_id[1]
2553 * sse_qe[1][15:0] = flow_id[2]
2554 * sse_qe[1][79:64] = flow_id[3]
2556 #define DLB_QE_EV_TYPE_WORD 0
2557 sse_qe[0] = _mm_insert_epi16(sse_qe[0],
2558 ev[0].sub_event_type << 8 |
2560 DLB_QE_EV_TYPE_WORD);
2561 sse_qe[0] = _mm_insert_epi16(sse_qe[0],
2562 ev[1].sub_event_type << 8 |
2564 DLB_QE_EV_TYPE_WORD + 4);
2565 sse_qe[1] = _mm_insert_epi16(sse_qe[1],
2566 ev[2].sub_event_type << 8 |
2568 DLB_QE_EV_TYPE_WORD);
2569 sse_qe[1] = _mm_insert_epi16(sse_qe[1],
2570 ev[3].sub_event_type << 8 |
2572 DLB_QE_EV_TYPE_WORD + 4);
2574 /* Store the metadata to memory (use the double-precision
2575 * _mm_storeh_pd because there is no integer function for
2576 * storing the upper 64b):
2577 * qe[0] metadata = sse_qe[0][63:0]
2578 * qe[1] metadata = sse_qe[0][127:64]
2579 * qe[2] metadata = sse_qe[1][63:0]
2580 * qe[3] metadata = sse_qe[1][127:64]
2582 _mm_storel_epi64((__m128i *)&qe[0].u.opaque_data, sse_qe[0]);
2583 _mm_storeh_pd((double *)&qe[1].u.opaque_data,
2584 (__m128d) sse_qe[0]);
2585 _mm_storel_epi64((__m128i *)&qe[2].u.opaque_data, sse_qe[1]);
2586 _mm_storeh_pd((double *)&qe[3].u.opaque_data,
2587 (__m128d) sse_qe[1]);
2589 qe[0].data = ev[0].u64;
2590 qe[1].data = ev[1].u64;
2591 qe[2].data = ev[2].u64;
2592 qe[3].data = ev[3].u64;
2598 for (i = 0; i < num; i++) {
2600 cmd_byte_map[qm_port->is_directed][ev[i].op];
2601 qe[i].sched_type = sched_type[i];
2602 qe[i].data = ev[i].u64;
2603 qe[i].qid = queue_id[i];
2604 qe[i].priority = EV_TO_DLB_PRIO(ev[i].priority);
2605 qe[i].lock_id = ev[i].flow_id;
2606 if (sched_type[i] == DLB_SCHED_DIRECTED) {
2607 struct dlb_msg_info *info =
2608 (struct dlb_msg_info *)&qe[i].lock_id;
2610 info->qid = queue_id[i];
2611 info->sched_type = DLB_SCHED_DIRECTED;
2612 info->priority = qe[i].priority;
2614 qe[i].u.event_type.major = ev[i].event_type;
2615 qe[i].u.event_type.sub = ev[i].sub_event_type;
2624 dlb_construct_token_pop_qe(struct dlb_port *qm_port, int idx)
2626 struct dlb_cq_pop_qe *qe = (void *)qm_port->qe4;
2627 int num = qm_port->owed_tokens;
2629 if (qm_port->use_rsvd_token_scheme) {
2630 /* Check if there's a deficit of reserved tokens, and return
2631 * early if there are no (unreserved) tokens to consume.
2633 if (num <= qm_port->cq_rsvd_token_deficit) {
2634 qm_port->cq_rsvd_token_deficit -= num;
2635 qm_port->owed_tokens = 0;
2638 num -= qm_port->cq_rsvd_token_deficit;
2639 qm_port->cq_rsvd_token_deficit = 0;
2642 qe[idx].cmd_byte = DLB_POP_CMD_BYTE;
2643 qe[idx].tokens = num - 1;
2644 qm_port->owed_tokens = 0;
2647 static __rte_always_inline void
2648 dlb_pp_write(struct dlb_enqueue_qe *qe4,
2649 struct process_local_port_data *port_data)
2651 dlb_movdir64b(port_data->pp_addr, qe4);
2655 dlb_hw_do_enqueue(struct dlb_port *qm_port,
2657 struct process_local_port_data *port_data)
2659 DLB_LOG_DBG("dlb: Flushing QE(s) to DLB\n");
2661 /* Since MOVDIR64B is weakly-ordered, use an SFENCE to ensure that
2662 * application writes complete before enqueueing the release HCW.
2667 dlb_pp_write(qm_port->qe4, port_data);
2671 dlb_consume_qe_immediate(struct dlb_port *qm_port, int num)
2673 struct process_local_port_data *port_data;
2674 struct dlb_cq_pop_qe *qe;
2676 RTE_ASSERT(qm_port->config_state == DLB_CONFIGURED);
2678 if (qm_port->use_rsvd_token_scheme) {
2679 /* Check if there's a deficit of reserved tokens, and return
2680 * early if there are no (unreserved) tokens to consume.
2682 if (num <= qm_port->cq_rsvd_token_deficit) {
2683 qm_port->cq_rsvd_token_deficit -= num;
2684 qm_port->owed_tokens = 0;
2687 num -= qm_port->cq_rsvd_token_deficit;
2688 qm_port->cq_rsvd_token_deficit = 0;
2691 qe = qm_port->consume_qe;
2693 qe->tokens = num - 1;
2696 /* No store fence needed since no pointer is being sent, and CQ token
2697 * pops can be safely reordered with other HCWs.
2699 port_data = &dlb_port[qm_port->id][PORT_TYPE(qm_port)];
2701 dlb_movntdq_single(port_data->pp_addr, qe);
2703 DLB_LOG_DBG("dlb: consume immediate - %d QEs\n", num);
2705 qm_port->owed_tokens = 0;
2710 static inline uint16_t
2711 __dlb_event_enqueue_burst(void *event_port,
2712 const struct rte_event events[],
2716 struct dlb_eventdev_port *ev_port = event_port;
2717 struct dlb_port *qm_port = &ev_port->qm_port;
2718 struct process_local_port_data *port_data;
2721 RTE_ASSERT(ev_port->enq_configured);
2722 RTE_ASSERT(events != NULL);
2727 port_data = &dlb_port[qm_port->id][PORT_TYPE(qm_port)];
2730 uint8_t sched_types[DLB_NUM_QES_PER_CACHE_LINE];
2731 uint8_t queue_ids[DLB_NUM_QES_PER_CACHE_LINE];
2735 memset(qm_port->qe4,
2737 DLB_NUM_QES_PER_CACHE_LINE *
2738 sizeof(struct dlb_enqueue_qe));
2740 for (; j < DLB_NUM_QES_PER_CACHE_LINE && (i + j) < num; j++) {
2741 const struct rte_event *ev = &events[i + j];
2742 int16_t thresh = qm_port->token_pop_thresh;
2745 qm_port->token_pop_mode == DELAYED_POP &&
2746 (ev->op == RTE_EVENT_OP_FORWARD ||
2747 ev->op == RTE_EVENT_OP_RELEASE) &&
2748 qm_port->issued_releases >= thresh - 1) {
2749 /* Insert the token pop QE and break out. This
2750 * may result in a partial HCW, but that is
2751 * simpler than supporting arbitrary QE
2754 dlb_construct_token_pop_qe(qm_port, j);
2756 /* Reset the releases for the next QE batch */
2757 qm_port->issued_releases -= thresh;
2759 /* When using delayed token pop mode, the
2760 * initial token threshold is the full CQ
2761 * depth. After the first token pop, we need to
2762 * reset it to the dequeue_depth.
2764 qm_port->token_pop_thresh =
2765 qm_port->dequeue_depth;
2772 if (dlb_event_enqueue_prep(ev_port, qm_port, ev,
2773 port_data, &sched_types[j],
2781 dlb_event_build_hcws(qm_port, &events[i], j - pop_offs,
2782 sched_types, queue_ids);
2784 dlb_hw_do_enqueue(qm_port, i == 0, port_data);
2786 /* Don't include the token pop QE in the enqueue count */
2789 /* Don't interpret j < DLB_NUM_... as out-of-credits if
2792 if (j < DLB_NUM_QES_PER_CACHE_LINE && pop_offs == 0)
2796 RTE_ASSERT(!((i == 0 && rte_errno != -ENOSPC)));
2801 static inline uint16_t
2802 dlb_event_enqueue_burst(void *event_port,
2803 const struct rte_event events[],
2806 return __dlb_event_enqueue_burst(event_port, events, num, false);
2809 static inline uint16_t
2810 dlb_event_enqueue_burst_delayed(void *event_port,
2811 const struct rte_event events[],
2814 return __dlb_event_enqueue_burst(event_port, events, num, true);
2817 static inline uint16_t
2818 dlb_event_enqueue(void *event_port,
2819 const struct rte_event events[])
2821 return __dlb_event_enqueue_burst(event_port, events, 1, false);
2824 static inline uint16_t
2825 dlb_event_enqueue_delayed(void *event_port,
2826 const struct rte_event events[])
2828 return __dlb_event_enqueue_burst(event_port, events, 1, true);
2832 dlb_event_enqueue_new_burst(void *event_port,
2833 const struct rte_event events[],
2836 return __dlb_event_enqueue_burst(event_port, events, num, false);
2840 dlb_event_enqueue_new_burst_delayed(void *event_port,
2841 const struct rte_event events[],
2844 return __dlb_event_enqueue_burst(event_port, events, num, true);
2848 dlb_event_enqueue_forward_burst(void *event_port,
2849 const struct rte_event events[],
2852 return __dlb_event_enqueue_burst(event_port, events, num, false);
2856 dlb_event_enqueue_forward_burst_delayed(void *event_port,
2857 const struct rte_event events[],
2860 return __dlb_event_enqueue_burst(event_port, events, num, true);
2863 static __rte_always_inline int
2864 dlb_recv_qe(struct dlb_port *qm_port, struct dlb_dequeue_qe *qe,
2867 uint8_t xor_mask[2][4] = { {0x0F, 0x0E, 0x0C, 0x08},
2868 {0x00, 0x01, 0x03, 0x07} };
2869 uint8_t and_mask[4] = {0x0F, 0x0E, 0x0C, 0x08};
2870 volatile struct dlb_dequeue_qe *cq_addr;
2871 __m128i *qes = (__m128i *)qe;
2872 uint64_t *cache_line_base;
2875 cq_addr = dlb_port[qm_port->id][PORT_TYPE(qm_port)].cq_base;
2876 cq_addr = &cq_addr[qm_port->cq_idx];
2878 cache_line_base = (void *)(((uintptr_t)cq_addr) & ~0x3F);
2879 *offset = ((uintptr_t)cq_addr & 0x30) >> 4;
2881 /* Load the next CQ cache line from memory. Pack these reads as tight
2882 * as possible to reduce the chance that DLB invalidates the line while
2883 * the CPU is reading it. Read the cache line backwards to ensure that
2884 * if QE[N] (N > 0) is valid, then QEs[0:N-1] are too.
2886 * (Valid QEs start at &qe[offset])
2888 qes[3] = _mm_load_si128((__m128i *)&cache_line_base[6]);
2889 qes[2] = _mm_load_si128((__m128i *)&cache_line_base[4]);
2890 qes[1] = _mm_load_si128((__m128i *)&cache_line_base[2]);
2891 qes[0] = _mm_load_si128((__m128i *)&cache_line_base[0]);
2893 /* Evict the cache line ASAP */
2894 rte_cldemote(cache_line_base);
2896 /* Extract and combine the gen bits */
2897 gen_bits = ((_mm_extract_epi8(qes[0], 15) & 0x1) << 0) |
2898 ((_mm_extract_epi8(qes[1], 15) & 0x1) << 1) |
2899 ((_mm_extract_epi8(qes[2], 15) & 0x1) << 2) |
2900 ((_mm_extract_epi8(qes[3], 15) & 0x1) << 3);
2902 /* XOR the combined bits such that a 1 represents a valid QE */
2903 gen_bits ^= xor_mask[qm_port->gen_bit][*offset];
2905 /* Mask off gen bits we don't care about */
2906 gen_bits &= and_mask[*offset];
2908 return __builtin_popcount(gen_bits);
2912 dlb_inc_cq_idx(struct dlb_port *qm_port, int cnt)
2914 uint16_t idx = qm_port->cq_idx_unmasked + cnt;
2916 qm_port->cq_idx_unmasked = idx;
2917 qm_port->cq_idx = idx & qm_port->cq_depth_mask;
2918 qm_port->gen_bit = (~(idx >> qm_port->gen_bit_shift)) & 0x1;
2922 dlb_process_dequeue_qes(struct dlb_eventdev_port *ev_port,
2923 struct dlb_port *qm_port,
2924 struct rte_event *events,
2925 struct dlb_dequeue_qe *qes,
2928 uint8_t *qid_mappings = qm_port->qid_mappings;
2931 RTE_SET_USED(ev_port); /* avoids unused variable error */
2933 for (i = 0, num = 0; i < cnt; i++) {
2934 struct dlb_dequeue_qe *qe = &qes[i];
2935 int sched_type_map[4] = {
2936 [DLB_SCHED_ATOMIC] = RTE_SCHED_TYPE_ATOMIC,
2937 [DLB_SCHED_UNORDERED] = RTE_SCHED_TYPE_PARALLEL,
2938 [DLB_SCHED_ORDERED] = RTE_SCHED_TYPE_ORDERED,
2939 [DLB_SCHED_DIRECTED] = RTE_SCHED_TYPE_ATOMIC,
2942 DLB_LOG_DBG("dequeue success, data = 0x%llx, qid=%d, event_type=%d, subevent=%d\npp_id = %d, sched_type = %d, qid = %d, err=%d\n",
2943 (long long)qe->data, qe->qid,
2944 qe->u.event_type.major,
2945 qe->u.event_type.sub,
2946 qe->pp_id, qe->sched_type, qe->qid, qe->error);
2948 /* Fill in event information.
2949 * Note that flow_id must be embedded in the data by
2950 * the app, such as the mbuf RSS hash field if the data
2953 if (unlikely(qe->error)) {
2954 DLB_LOG_ERR("QE error bit ON\n");
2955 DLB_INC_STAT(ev_port->stats.traffic.rx_drop, 1);
2956 dlb_consume_qe_immediate(qm_port, 1);
2957 continue; /* Ignore */
2960 events[num].u64 = qe->data;
2961 events[num].queue_id = qid_mappings[qe->qid];
2962 events[num].priority = DLB_TO_EV_PRIO((uint8_t)qe->priority);
2963 events[num].event_type = qe->u.event_type.major;
2964 events[num].sub_event_type = qe->u.event_type.sub;
2965 events[num].sched_type = sched_type_map[qe->sched_type];
2966 DLB_INC_STAT(ev_port->stats.rx_sched_cnt[qe->sched_type], 1);
2969 DLB_INC_STAT(ev_port->stats.traffic.rx_ok, num);
2975 dlb_process_dequeue_four_qes(struct dlb_eventdev_port *ev_port,
2976 struct dlb_port *qm_port,
2977 struct rte_event *events,
2978 struct dlb_dequeue_qe *qes)
2980 int sched_type_map[] = {
2981 [DLB_SCHED_ATOMIC] = RTE_SCHED_TYPE_ATOMIC,
2982 [DLB_SCHED_UNORDERED] = RTE_SCHED_TYPE_PARALLEL,
2983 [DLB_SCHED_ORDERED] = RTE_SCHED_TYPE_ORDERED,
2984 [DLB_SCHED_DIRECTED] = RTE_SCHED_TYPE_ATOMIC,
2986 const int num_events = DLB_NUM_QES_PER_CACHE_LINE;
2987 uint8_t *qid_mappings = qm_port->qid_mappings;
2991 /* In the unlikely case that any of the QE error bits are set, process
2992 * them one at a time.
2994 if (unlikely(qes[0].error || qes[1].error ||
2995 qes[2].error || qes[3].error))
2996 return dlb_process_dequeue_qes(ev_port, qm_port, events,
2999 for (i = 0; i < DLB_NUM_QES_PER_CACHE_LINE; i++) {
3000 DLB_LOG_DBG("dequeue success, data = 0x%llx, qid=%d, event_type=%d, subevent=%d\npp_id = %d, sched_type = %d, qid = %d, err=%d\n",
3001 (long long)qes[i].data, qes[i].qid,
3002 qes[i].u.event_type.major,
3003 qes[i].u.event_type.sub,
3004 qes[i].pp_id, qes[i].sched_type, qes[i].qid,
3008 events[0].u64 = qes[0].data;
3009 events[1].u64 = qes[1].data;
3010 events[2].u64 = qes[2].data;
3011 events[3].u64 = qes[3].data;
3013 /* Construct the metadata portion of two struct rte_events
3014 * in one 128b SSE register. Event metadata is constructed in the SSE
3015 * registers like so:
3016 * sse_evt[0][63:0]: event[0]'s metadata
3017 * sse_evt[0][127:64]: event[1]'s metadata
3018 * sse_evt[1][63:0]: event[2]'s metadata
3019 * sse_evt[1][127:64]: event[3]'s metadata
3021 sse_evt[0] = _mm_setzero_si128();
3022 sse_evt[1] = _mm_setzero_si128();
3024 /* Convert the hardware queue ID to an event queue ID and store it in
3026 * sse_evt[0][47:40] = qid_mappings[qes[0].qid]
3027 * sse_evt[0][111:104] = qid_mappings[qes[1].qid]
3028 * sse_evt[1][47:40] = qid_mappings[qes[2].qid]
3029 * sse_evt[1][111:104] = qid_mappings[qes[3].qid]
3031 #define DLB_EVENT_QUEUE_ID_BYTE 5
3032 sse_evt[0] = _mm_insert_epi8(sse_evt[0],
3033 qid_mappings[qes[0].qid],
3034 DLB_EVENT_QUEUE_ID_BYTE);
3035 sse_evt[0] = _mm_insert_epi8(sse_evt[0],
3036 qid_mappings[qes[1].qid],
3037 DLB_EVENT_QUEUE_ID_BYTE + 8);
3038 sse_evt[1] = _mm_insert_epi8(sse_evt[1],
3039 qid_mappings[qes[2].qid],
3040 DLB_EVENT_QUEUE_ID_BYTE);
3041 sse_evt[1] = _mm_insert_epi8(sse_evt[1],
3042 qid_mappings[qes[3].qid],
3043 DLB_EVENT_QUEUE_ID_BYTE + 8);
3045 /* Convert the hardware priority to an event priority and store it in
3047 * sse_evt[0][55:48] = DLB_TO_EV_PRIO(qes[0].priority)
3048 * sse_evt[0][119:112] = DLB_TO_EV_PRIO(qes[1].priority)
3049 * sse_evt[1][55:48] = DLB_TO_EV_PRIO(qes[2].priority)
3050 * sse_evt[1][119:112] = DLB_TO_EV_PRIO(qes[3].priority)
3052 #define DLB_EVENT_PRIO_BYTE 6
3053 sse_evt[0] = _mm_insert_epi8(sse_evt[0],
3054 DLB_TO_EV_PRIO((uint8_t)qes[0].priority),
3055 DLB_EVENT_PRIO_BYTE);
3056 sse_evt[0] = _mm_insert_epi8(sse_evt[0],
3057 DLB_TO_EV_PRIO((uint8_t)qes[1].priority),
3058 DLB_EVENT_PRIO_BYTE + 8);
3059 sse_evt[1] = _mm_insert_epi8(sse_evt[1],
3060 DLB_TO_EV_PRIO((uint8_t)qes[2].priority),
3061 DLB_EVENT_PRIO_BYTE);
3062 sse_evt[1] = _mm_insert_epi8(sse_evt[1],
3063 DLB_TO_EV_PRIO((uint8_t)qes[3].priority),
3064 DLB_EVENT_PRIO_BYTE + 8);
3066 /* Write the event type and sub event type to the event metadata. Leave
3067 * flow ID unspecified, since the hardware does not maintain it during
3069 * sse_evt[0][31:0] = qes[0].u.event_type.major << 28 |
3070 * qes[0].u.event_type.sub << 20;
3071 * sse_evt[0][95:64] = qes[1].u.event_type.major << 28 |
3072 * qes[1].u.event_type.sub << 20;
3073 * sse_evt[1][31:0] = qes[2].u.event_type.major << 28 |
3074 * qes[2].u.event_type.sub << 20;
3075 * sse_evt[1][95:64] = qes[3].u.event_type.major << 28 |
3076 * qes[3].u.event_type.sub << 20;
3078 #define DLB_EVENT_EV_TYPE_DW 0
3079 #define DLB_EVENT_EV_TYPE_SHIFT 28
3080 #define DLB_EVENT_SUB_EV_TYPE_SHIFT 20
3081 sse_evt[0] = _mm_insert_epi32(sse_evt[0],
3082 qes[0].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |
3083 qes[0].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,
3084 DLB_EVENT_EV_TYPE_DW);
3085 sse_evt[0] = _mm_insert_epi32(sse_evt[0],
3086 qes[1].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |
3087 qes[1].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,
3088 DLB_EVENT_EV_TYPE_DW + 2);
3089 sse_evt[1] = _mm_insert_epi32(sse_evt[1],
3090 qes[2].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |
3091 qes[2].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,
3092 DLB_EVENT_EV_TYPE_DW);
3093 sse_evt[1] = _mm_insert_epi32(sse_evt[1],
3094 qes[3].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |
3095 qes[3].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,
3096 DLB_EVENT_EV_TYPE_DW + 2);
3098 /* Write the sched type to the event metadata. 'op' and 'rsvd' are not
3100 * sse_evt[0][39:32] = sched_type_map[qes[0].sched_type] << 6
3101 * sse_evt[0][103:96] = sched_type_map[qes[1].sched_type] << 6
3102 * sse_evt[1][39:32] = sched_type_map[qes[2].sched_type] << 6
3103 * sse_evt[1][103:96] = sched_type_map[qes[3].sched_type] << 6
3105 #define DLB_EVENT_SCHED_TYPE_BYTE 4
3106 #define DLB_EVENT_SCHED_TYPE_SHIFT 6
3107 sse_evt[0] = _mm_insert_epi8(sse_evt[0],
3108 sched_type_map[qes[0].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,
3109 DLB_EVENT_SCHED_TYPE_BYTE);
3110 sse_evt[0] = _mm_insert_epi8(sse_evt[0],
3111 sched_type_map[qes[1].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,
3112 DLB_EVENT_SCHED_TYPE_BYTE + 8);
3113 sse_evt[1] = _mm_insert_epi8(sse_evt[1],
3114 sched_type_map[qes[2].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,
3115 DLB_EVENT_SCHED_TYPE_BYTE);
3116 sse_evt[1] = _mm_insert_epi8(sse_evt[1],
3117 sched_type_map[qes[3].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,
3118 DLB_EVENT_SCHED_TYPE_BYTE + 8);
3120 /* Store the metadata to the event (use the double-precision
3121 * _mm_storeh_pd because there is no integer function for storing the
3123 * events[0].event = sse_evt[0][63:0]
3124 * events[1].event = sse_evt[0][127:64]
3125 * events[2].event = sse_evt[1][63:0]
3126 * events[3].event = sse_evt[1][127:64]
3128 _mm_storel_epi64((__m128i *)&events[0].event, sse_evt[0]);
3129 _mm_storeh_pd((double *)&events[1].event, (__m128d) sse_evt[0]);
3130 _mm_storel_epi64((__m128i *)&events[2].event, sse_evt[1]);
3131 _mm_storeh_pd((double *)&events[3].event, (__m128d) sse_evt[1]);
3133 DLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[0].sched_type], 1);
3134 DLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[1].sched_type], 1);
3135 DLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[2].sched_type], 1);
3136 DLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[3].sched_type], 1);
3138 DLB_INC_STAT(ev_port->stats.traffic.rx_ok, num_events);
3144 dlb_dequeue_wait(struct dlb_eventdev *dlb,
3145 struct dlb_eventdev_port *ev_port,
3146 struct dlb_port *qm_port,
3148 uint64_t start_ticks)
3150 struct process_local_port_data *port_data;
3151 uint64_t elapsed_ticks;
3153 port_data = &dlb_port[qm_port->id][PORT_TYPE(qm_port)];
3155 elapsed_ticks = rte_get_timer_cycles() - start_ticks;
3157 /* Wait/poll time expired */
3158 if (elapsed_ticks >= timeout) {
3159 /* Interrupts not supported by PF PMD */
3161 } else if (dlb->umwait_allowed) {
3162 volatile struct dlb_dequeue_qe *cq_base;
3165 struct dlb_dequeue_qe qe;
3167 uint64_t expected_value;
3168 volatile uint64_t *monitor_addr;
3170 qe_mask.qe.cq_gen = 1; /* set mask */
3172 cq_base = port_data->cq_base;
3173 monitor_addr = (volatile uint64_t *)(volatile void *)
3174 &cq_base[qm_port->cq_idx];
3175 monitor_addr++; /* cq_gen bit is in second 64bit location */
3177 if (qm_port->gen_bit)
3178 expected_value = qe_mask.raw_qe[1];
3182 rte_power_monitor(monitor_addr, expected_value,
3183 qe_mask.raw_qe[1], timeout + start_ticks,
3186 DLB_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);
3188 uint64_t poll_interval = RTE_LIBRTE_PMD_DLB_POLL_INTERVAL;
3189 uint64_t curr_ticks = rte_get_timer_cycles();
3190 uint64_t init_ticks = curr_ticks;
3192 while ((curr_ticks - start_ticks < timeout) &&
3193 (curr_ticks - init_ticks < poll_interval))
3194 curr_ticks = rte_get_timer_cycles();
3200 static inline int16_t
3201 dlb_hw_dequeue(struct dlb_eventdev *dlb,
3202 struct dlb_eventdev_port *ev_port,
3203 struct rte_event *events,
3205 uint64_t dequeue_timeout_ticks)
3208 uint64_t start_ticks = 0ULL;
3209 struct dlb_port *qm_port;
3212 qm_port = &ev_port->qm_port;
3214 /* If configured for per dequeue wait, then use wait value provided
3215 * to this API. Otherwise we must use the global
3216 * value from eventdev config time.
3218 if (!dlb->global_dequeue_wait)
3219 timeout = dequeue_timeout_ticks;
3221 timeout = dlb->global_dequeue_wait_ticks;
3224 start_ticks = rte_get_timer_cycles();
3226 while (num < max_num) {
3227 struct dlb_dequeue_qe qes[DLB_NUM_QES_PER_CACHE_LINE];
3231 /* Copy up to 4 QEs from the current cache line into qes */
3232 num_avail = dlb_recv_qe(qm_port, qes, &offset);
3234 /* But don't process more than the user requested */
3235 num_avail = RTE_MIN(num_avail, max_num - num);
3237 dlb_inc_cq_idx(qm_port, num_avail);
3239 if (num_avail == DLB_NUM_QES_PER_CACHE_LINE)
3240 num += dlb_process_dequeue_four_qes(ev_port,
3245 num += dlb_process_dequeue_qes(ev_port,
3250 else if ((timeout == 0) || (num > 0))
3251 /* Not waiting in any form, or 1+ events received? */
3253 else if (dlb_dequeue_wait(dlb, ev_port, qm_port,
3254 timeout, start_ticks))
3258 qm_port->owed_tokens += num;
3260 if (num && qm_port->token_pop_mode == AUTO_POP)
3261 dlb_consume_qe_immediate(qm_port, num);
3263 ev_port->outstanding_releases += num;
3268 static __rte_always_inline int
3269 dlb_recv_qe_sparse(struct dlb_port *qm_port, struct dlb_dequeue_qe *qe)
3271 volatile struct dlb_dequeue_qe *cq_addr;
3272 uint8_t xor_mask[2] = {0x0F, 0x00};
3273 const uint8_t and_mask = 0x0F;
3274 __m128i *qes = (__m128i *)qe;
3275 uint8_t gen_bits, gen_bit;
3279 cq_addr = dlb_port[qm_port->id][PORT_TYPE(qm_port)].cq_base;
3281 idx = qm_port->cq_idx;
3283 /* Load the next 4 QEs */
3284 addr[0] = (uintptr_t)&cq_addr[idx];
3285 addr[1] = (uintptr_t)&cq_addr[(idx + 4) & qm_port->cq_depth_mask];
3286 addr[2] = (uintptr_t)&cq_addr[(idx + 8) & qm_port->cq_depth_mask];
3287 addr[3] = (uintptr_t)&cq_addr[(idx + 12) & qm_port->cq_depth_mask];
3289 /* Prefetch next batch of QEs (all CQs occupy minimum 8 cache lines) */
3290 rte_prefetch0(&cq_addr[(idx + 16) & qm_port->cq_depth_mask]);
3291 rte_prefetch0(&cq_addr[(idx + 20) & qm_port->cq_depth_mask]);
3292 rte_prefetch0(&cq_addr[(idx + 24) & qm_port->cq_depth_mask]);
3293 rte_prefetch0(&cq_addr[(idx + 28) & qm_port->cq_depth_mask]);
3295 /* Correct the xor_mask for wrap-around QEs */
3296 gen_bit = qm_port->gen_bit;
3297 xor_mask[gen_bit] ^= !!((idx + 4) > qm_port->cq_depth_mask) << 1;
3298 xor_mask[gen_bit] ^= !!((idx + 8) > qm_port->cq_depth_mask) << 2;
3299 xor_mask[gen_bit] ^= !!((idx + 12) > qm_port->cq_depth_mask) << 3;
3301 /* Read the cache lines backwards to ensure that if QE[N] (N > 0) is
3302 * valid, then QEs[0:N-1] are too.
3304 qes[3] = _mm_load_si128((__m128i *)(void *)addr[3]);
3305 rte_compiler_barrier();
3306 qes[2] = _mm_load_si128((__m128i *)(void *)addr[2]);
3307 rte_compiler_barrier();
3308 qes[1] = _mm_load_si128((__m128i *)(void *)addr[1]);
3309 rte_compiler_barrier();
3310 qes[0] = _mm_load_si128((__m128i *)(void *)addr[0]);
3312 /* Extract and combine the gen bits */
3313 gen_bits = ((_mm_extract_epi8(qes[0], 15) & 0x1) << 0) |
3314 ((_mm_extract_epi8(qes[1], 15) & 0x1) << 1) |
3315 ((_mm_extract_epi8(qes[2], 15) & 0x1) << 2) |
3316 ((_mm_extract_epi8(qes[3], 15) & 0x1) << 3);
3318 /* XOR the combined bits such that a 1 represents a valid QE */
3319 gen_bits ^= xor_mask[gen_bit];
3321 /* Mask off gen bits we don't care about */
3322 gen_bits &= and_mask;
3324 return __builtin_popcount(gen_bits);
3327 static inline int16_t
3328 dlb_hw_dequeue_sparse(struct dlb_eventdev *dlb,
3329 struct dlb_eventdev_port *ev_port,
3330 struct rte_event *events,
3332 uint64_t dequeue_timeout_ticks)
3335 uint64_t start_ticks = 0ULL;
3336 struct dlb_port *qm_port;
3339 qm_port = &ev_port->qm_port;
3341 /* If configured for per dequeue wait, then use wait value provided
3342 * to this API. Otherwise we must use the global
3343 * value from eventdev config time.
3345 if (!dlb->global_dequeue_wait)
3346 timeout = dequeue_timeout_ticks;
3348 timeout = dlb->global_dequeue_wait_ticks;
3351 start_ticks = rte_get_timer_cycles();
3353 while (num < max_num) {
3354 struct dlb_dequeue_qe qes[DLB_NUM_QES_PER_CACHE_LINE];
3357 /* Copy up to 4 QEs from the current cache line into qes */
3358 num_avail = dlb_recv_qe_sparse(qm_port, qes);
3360 /* But don't process more than the user requested */
3361 num_avail = RTE_MIN(num_avail, max_num - num);
3363 dlb_inc_cq_idx(qm_port, num_avail << 2);
3365 if (num_avail == DLB_NUM_QES_PER_CACHE_LINE)
3366 num += dlb_process_dequeue_four_qes(ev_port,
3371 num += dlb_process_dequeue_qes(ev_port,
3376 else if ((timeout == 0) || (num > 0))
3377 /* Not waiting in any form, or 1+ events received? */
3379 else if (dlb_dequeue_wait(dlb, ev_port, qm_port,
3380 timeout, start_ticks))
3384 qm_port->owed_tokens += num;
3386 if (num && qm_port->token_pop_mode == AUTO_POP)
3387 dlb_consume_qe_immediate(qm_port, num);
3389 ev_port->outstanding_releases += num;
3395 dlb_event_release(struct dlb_eventdev *dlb, uint8_t port_id, int n)
3397 struct process_local_port_data *port_data;
3398 struct dlb_eventdev_port *ev_port;
3399 struct dlb_port *qm_port;
3402 if (port_id > dlb->num_ports) {
3403 DLB_LOG_ERR("Invalid port id %d in dlb-event_release\n",
3405 rte_errno = -EINVAL;
3409 ev_port = &dlb->ev_ports[port_id];
3410 qm_port = &ev_port->qm_port;
3411 port_data = &dlb_port[qm_port->id][PORT_TYPE(qm_port)];
3415 if (qm_port->is_directed) {
3417 goto sw_credit_update;
3425 qm_port->qe4[0].cmd_byte = 0;
3426 qm_port->qe4[1].cmd_byte = 0;
3427 qm_port->qe4[2].cmd_byte = 0;
3428 qm_port->qe4[3].cmd_byte = 0;
3430 for (; j < DLB_NUM_QES_PER_CACHE_LINE && (i + j) < n; j++) {
3431 int16_t thresh = qm_port->token_pop_thresh;
3433 if (qm_port->token_pop_mode == DELAYED_POP &&
3434 qm_port->issued_releases >= thresh - 1) {
3435 /* Insert the token pop QE */
3436 dlb_construct_token_pop_qe(qm_port, j);
3438 /* Reset the releases for the next QE batch */
3439 qm_port->issued_releases -= thresh;
3441 /* When using delayed token pop mode, the
3442 * initial token threshold is the full CQ
3443 * depth. After the first token pop, we need to
3444 * reset it to the dequeue_depth.
3446 qm_port->token_pop_thresh =
3447 qm_port->dequeue_depth;
3454 qm_port->qe4[j].cmd_byte = DLB_COMP_CMD_BYTE;
3455 qm_port->issued_releases++;
3458 dlb_hw_do_enqueue(qm_port, i == 0, port_data);
3460 /* Don't include the token pop QE in the release count */
3465 /* each release returns one credit */
3466 if (!ev_port->outstanding_releases) {
3467 DLB_LOG_ERR("Unrecoverable application error. Outstanding releases underflowed.\n");
3468 rte_errno = -ENOTRECOVERABLE;
3472 ev_port->outstanding_releases -= i;
3473 ev_port->inflight_credits += i;
3475 /* Replenish s/w credits if enough releases are performed */
3476 dlb_replenish_sw_credits(dlb, ev_port);
3481 dlb_event_dequeue_burst(void *event_port, struct rte_event *ev, uint16_t num,
3484 struct dlb_eventdev_port *ev_port = event_port;
3485 struct dlb_port *qm_port = &ev_port->qm_port;
3486 struct dlb_eventdev *dlb = ev_port->dlb;
3492 RTE_ASSERT(ev_port->setup_done);
3493 RTE_ASSERT(ev != NULL);
3495 if (ev_port->implicit_release && ev_port->outstanding_releases > 0) {
3496 uint16_t out_rels = ev_port->outstanding_releases;
3498 ret = dlb_event_release(dlb, ev_port->id, out_rels);
3502 DLB_INC_STAT(ev_port->stats.tx_implicit_rel, out_rels);
3505 if (qm_port->token_pop_mode == DEFERRED_POP &&
3506 qm_port->owed_tokens)
3507 dlb_consume_qe_immediate(qm_port, qm_port->owed_tokens);
3509 cnt = dlb_hw_dequeue(dlb, ev_port, ev, num, wait);
3511 DLB_INC_STAT(ev_port->stats.traffic.total_polls, 1);
3512 DLB_INC_STAT(ev_port->stats.traffic.zero_polls, ((cnt == 0) ? 1 : 0));
3517 dlb_event_dequeue(void *event_port, struct rte_event *ev, uint64_t wait)
3519 return dlb_event_dequeue_burst(event_port, ev, 1, wait);
3523 dlb_event_dequeue_burst_sparse(void *event_port, struct rte_event *ev,
3524 uint16_t num, uint64_t wait)
3526 struct dlb_eventdev_port *ev_port = event_port;
3527 struct dlb_port *qm_port = &ev_port->qm_port;
3528 struct dlb_eventdev *dlb = ev_port->dlb;
3534 RTE_ASSERT(ev_port->setup_done);
3535 RTE_ASSERT(ev != NULL);
3537 if (ev_port->implicit_release && ev_port->outstanding_releases > 0) {
3538 uint16_t out_rels = ev_port->outstanding_releases;
3540 ret = dlb_event_release(dlb, ev_port->id, out_rels);
3544 DLB_INC_STAT(ev_port->stats.tx_implicit_rel, out_rels);
3547 if (qm_port->token_pop_mode == DEFERRED_POP &&
3548 qm_port->owed_tokens)
3549 dlb_consume_qe_immediate(qm_port, qm_port->owed_tokens);
3551 cnt = dlb_hw_dequeue_sparse(dlb, ev_port, ev, num, wait);
3553 DLB_INC_STAT(ev_port->stats.traffic.total_polls, 1);
3554 DLB_INC_STAT(ev_port->stats.traffic.zero_polls, ((cnt == 0) ? 1 : 0));
3559 dlb_event_dequeue_sparse(void *event_port, struct rte_event *ev, uint64_t wait)
3561 return dlb_event_dequeue_burst_sparse(event_port, ev, 1, wait);
3565 dlb_get_ldb_queue_depth(struct dlb_eventdev *dlb,
3566 struct dlb_eventdev_queue *queue)
3568 struct dlb_hw_dev *handle = &dlb->qm_instance;
3569 struct dlb_get_ldb_queue_depth_args cfg;
3570 struct dlb_cmd_response response;
3573 cfg.queue_id = queue->qm_queue.id;
3574 cfg.response = (uintptr_t)&response;
3576 ret = dlb_iface_get_ldb_queue_depth(handle, &cfg);
3578 DLB_LOG_ERR("dlb: get_ldb_queue_depth ret=%d (driver status: %s)\n",
3579 ret, dlb_error_strings[response.status]);
3587 dlb_get_dir_queue_depth(struct dlb_eventdev *dlb,
3588 struct dlb_eventdev_queue *queue)
3590 struct dlb_hw_dev *handle = &dlb->qm_instance;
3591 struct dlb_get_dir_queue_depth_args cfg;
3592 struct dlb_cmd_response response;
3595 cfg.queue_id = queue->qm_queue.id;
3596 cfg.response = (uintptr_t)&response;
3598 ret = dlb_iface_get_dir_queue_depth(handle, &cfg);
3600 DLB_LOG_ERR("dlb: get_dir_queue_depth ret=%d (driver status: %s)\n",
3601 ret, dlb_error_strings[response.status]);
3609 dlb_get_queue_depth(struct dlb_eventdev *dlb,
3610 struct dlb_eventdev_queue *queue)
3612 if (queue->qm_queue.is_directed)
3613 return dlb_get_dir_queue_depth(dlb, queue);
3615 return dlb_get_ldb_queue_depth(dlb, queue);
3619 dlb_queue_is_empty(struct dlb_eventdev *dlb,
3620 struct dlb_eventdev_queue *queue)
3622 return dlb_get_queue_depth(dlb, queue) == 0;
3626 dlb_linked_queues_empty(struct dlb_eventdev *dlb)
3630 for (i = 0; i < dlb->num_queues; i++) {
3631 if (dlb->ev_queues[i].num_links == 0)
3633 if (!dlb_queue_is_empty(dlb, &dlb->ev_queues[i]))
3641 dlb_queues_empty(struct dlb_eventdev *dlb)
3645 for (i = 0; i < dlb->num_queues; i++) {
3646 if (!dlb_queue_is_empty(dlb, &dlb->ev_queues[i]))
3654 dlb_flush_port(struct rte_eventdev *dev, int port_id)
3656 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
3657 eventdev_stop_flush_t flush;
3658 struct rte_event ev;
3663 flush = dev->dev_ops->dev_stop_flush;
3664 dev_id = dev->data->dev_id;
3665 arg = dev->data->dev_stop_flush_arg;
3667 while (rte_event_dequeue_burst(dev_id, port_id, &ev, 1, 0)) {
3669 flush(dev_id, ev, arg);
3671 if (dlb->ev_ports[port_id].qm_port.is_directed)
3674 ev.op = RTE_EVENT_OP_RELEASE;
3676 rte_event_enqueue_burst(dev_id, port_id, &ev, 1);
3679 /* Enqueue any additional outstanding releases */
3680 ev.op = RTE_EVENT_OP_RELEASE;
3682 for (i = dlb->ev_ports[port_id].outstanding_releases; i > 0; i--)
3683 rte_event_enqueue_burst(dev_id, port_id, &ev, 1);
3687 dlb_drain(struct rte_eventdev *dev)
3689 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
3690 struct dlb_eventdev_port *ev_port = NULL;
3694 dev_id = dev->data->dev_id;
3696 while (!dlb_linked_queues_empty(dlb)) {
3697 /* Flush all the ev_ports, which will drain all their connected
3700 for (i = 0; i < dlb->num_ports; i++)
3701 dlb_flush_port(dev, i);
3704 /* The queues are empty, but there may be events left in the ports. */
3705 for (i = 0; i < dlb->num_ports; i++)
3706 dlb_flush_port(dev, i);
3708 /* If the domain's queues are empty, we're done. */
3709 if (dlb_queues_empty(dlb))
3712 /* Else, there must be at least one unlinked load-balanced queue.
3713 * Select a load-balanced port with which to drain the unlinked
3716 for (i = 0; i < dlb->num_ports; i++) {
3717 ev_port = &dlb->ev_ports[i];
3719 if (!ev_port->qm_port.is_directed)
3723 if (i == dlb->num_ports) {
3724 DLB_LOG_ERR("internal error: no LDB ev_ports\n");
3729 rte_event_port_unlink(dev_id, ev_port->id, NULL, 0);
3732 DLB_LOG_ERR("internal error: failed to unlink ev_port %d\n",
3737 for (i = 0; i < dlb->num_queues; i++) {
3741 if (dlb_queue_is_empty(dlb, &dlb->ev_queues[i]))
3747 /* Link the ev_port to the queue */
3748 ret = rte_event_port_link(dev_id, ev_port->id, &qid, &prio, 1);
3750 DLB_LOG_ERR("internal error: failed to link ev_port %d to queue %d\n",
3755 /* Flush the queue */
3756 while (!dlb_queue_is_empty(dlb, &dlb->ev_queues[i]))
3757 dlb_flush_port(dev, ev_port->id);
3759 /* Drain any extant events in the ev_port. */
3760 dlb_flush_port(dev, ev_port->id);
3762 /* Unlink the ev_port from the queue */
3763 ret = rte_event_port_unlink(dev_id, ev_port->id, &qid, 1);
3765 DLB_LOG_ERR("internal error: failed to unlink ev_port %d to queue %d\n",
3773 dlb_eventdev_stop(struct rte_eventdev *dev)
3775 struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
3777 rte_spinlock_lock(&dlb->qm_instance.resource_lock);
3779 if (dlb->run_state == DLB_RUN_STATE_STOPPED) {
3780 DLB_LOG_DBG("Internal error: already stopped\n");
3781 rte_spinlock_unlock(&dlb->qm_instance.resource_lock);
3783 } else if (dlb->run_state != DLB_RUN_STATE_STARTED) {
3784 DLB_LOG_ERR("Internal error: bad state %d for dev_stop\n",
3785 (int)dlb->run_state);
3786 rte_spinlock_unlock(&dlb->qm_instance.resource_lock);
3790 dlb->run_state = DLB_RUN_STATE_STOPPING;
3792 rte_spinlock_unlock(&dlb->qm_instance.resource_lock);
3796 dlb->run_state = DLB_RUN_STATE_STOPPED;
3800 dlb_eventdev_close(struct rte_eventdev *dev)
3802 dlb_hw_reset_sched_domain(dev, false);
3808 dlb_entry_points_init(struct rte_eventdev *dev)
3810 struct dlb_eventdev *dlb;
3812 static struct rte_eventdev_ops dlb_eventdev_entry_ops = {
3813 .dev_infos_get = dlb_eventdev_info_get,
3814 .dev_configure = dlb_eventdev_configure,
3815 .dev_start = dlb_eventdev_start,
3816 .dev_stop = dlb_eventdev_stop,
3817 .dev_close = dlb_eventdev_close,
3818 .queue_def_conf = dlb_eventdev_queue_default_conf_get,
3819 .port_def_conf = dlb_eventdev_port_default_conf_get,
3820 .queue_setup = dlb_eventdev_queue_setup,
3821 .port_setup = dlb_eventdev_port_setup,
3822 .port_link = dlb_eventdev_port_link,
3823 .port_unlink = dlb_eventdev_port_unlink,
3824 .port_unlinks_in_progress =
3825 dlb_eventdev_port_unlinks_in_progress,
3826 .dump = dlb_eventdev_dump,
3827 .xstats_get = dlb_eventdev_xstats_get,
3828 .xstats_get_names = dlb_eventdev_xstats_get_names,
3829 .xstats_get_by_name = dlb_eventdev_xstats_get_by_name,
3830 .xstats_reset = dlb_eventdev_xstats_reset,
3831 .dev_selftest = test_dlb_eventdev,
3834 /* Expose PMD's eventdev interface */
3835 dev->dev_ops = &dlb_eventdev_entry_ops;
3837 dev->enqueue = dlb_event_enqueue;
3838 dev->enqueue_burst = dlb_event_enqueue_burst;
3839 dev->enqueue_new_burst = dlb_event_enqueue_new_burst;
3840 dev->enqueue_forward_burst = dlb_event_enqueue_forward_burst;
3841 dev->dequeue = dlb_event_dequeue;
3842 dev->dequeue_burst = dlb_event_dequeue_burst;
3844 dlb = dev->data->dev_private;
3846 if (dlb->poll_mode == DLB_CQ_POLL_MODE_SPARSE) {
3847 dev->dequeue = dlb_event_dequeue_sparse;
3848 dev->dequeue_burst = dlb_event_dequeue_burst_sparse;
3853 dlb_primary_eventdev_probe(struct rte_eventdev *dev,
3855 struct dlb_devargs *dlb_args)
3857 struct dlb_eventdev *dlb;
3860 dlb = dev->data->dev_private;
3862 dlb->event_dev = dev; /* backlink */
3864 evdev_dlb_default_info.driver_name = name;
3866 dlb->max_num_events_override = dlb_args->max_num_events;
3867 dlb->num_dir_credits_override = dlb_args->num_dir_credits_override;
3868 dlb->defer_sched = dlb_args->defer_sched;
3869 dlb->num_atm_inflights_per_queue = dlb_args->num_atm_inflights;
3871 /* Open the interface.
3872 * For vdev mode, this means open the dlb kernel module.
3874 err = dlb_iface_open(&dlb->qm_instance, name);
3876 DLB_LOG_ERR("could not open event hardware device, err=%d\n",
3881 err = dlb_iface_get_device_version(&dlb->qm_instance, &dlb->revision);
3883 DLB_LOG_ERR("dlb: failed to get the device version, err=%d\n",
3888 err = dlb_hw_query_resources(dlb);
3890 DLB_LOG_ERR("get resources err=%d for %s\n", err, name);
3894 err = dlb_iface_get_cq_poll_mode(&dlb->qm_instance, &dlb->poll_mode);
3896 DLB_LOG_ERR("dlb: failed to get the poll mode, err=%d\n", err);
3900 /* Complete xtstats runtime initialization */
3901 err = dlb_xstats_init(dlb);
3903 DLB_LOG_ERR("dlb: failed to init xstats, err=%d\n", err);
3907 /* Initialize each port's token pop mode */
3908 for (i = 0; i < DLB_MAX_NUM_PORTS; i++)
3909 dlb->ev_ports[i].qm_port.token_pop_mode = AUTO_POP;
3911 rte_spinlock_init(&dlb->qm_instance.resource_lock);
3913 dlb_iface_low_level_io_init(dlb);
3915 dlb_entry_points_init(dev);
3921 dlb_secondary_eventdev_probe(struct rte_eventdev *dev,
3924 struct dlb_eventdev *dlb;
3927 dlb = dev->data->dev_private;
3929 evdev_dlb_default_info.driver_name = name;
3931 err = dlb_iface_open(&dlb->qm_instance, name);
3933 DLB_LOG_ERR("could not open event hardware device, err=%d\n",
3938 err = dlb_hw_query_resources(dlb);
3940 DLB_LOG_ERR("get resources err=%d for %s\n", err, name);
3944 dlb_iface_low_level_io_init(dlb);
3946 dlb_entry_points_init(dev);
3952 dlb_parse_params(const char *params,
3954 struct dlb_devargs *dlb_args)
3957 static const char * const args[] = { NUMA_NODE_ARG,
3959 DLB_NUM_DIR_CREDITS,
3961 DLB_DEFER_SCHED_ARG,
3962 DLB_NUM_ATM_INFLIGHTS_ARG,
3965 if (params && params[0] != '\0') {
3966 struct rte_kvargs *kvlist = rte_kvargs_parse(params, args);
3968 if (kvlist == NULL) {
3969 DLB_LOG_INFO("Ignoring unsupported parameters when creating device '%s'\n",
3972 int ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,
3974 &dlb_args->socket_id);
3976 DLB_LOG_ERR("%s: Error parsing numa node parameter",
3978 rte_kvargs_free(kvlist);
3982 ret = rte_kvargs_process(kvlist, DLB_MAX_NUM_EVENTS,
3984 &dlb_args->max_num_events);
3986 DLB_LOG_ERR("%s: Error parsing max_num_events parameter",
3988 rte_kvargs_free(kvlist);
3992 ret = rte_kvargs_process(kvlist,
3993 DLB_NUM_DIR_CREDITS,
3994 set_num_dir_credits,
3995 &dlb_args->num_dir_credits_override);
3997 DLB_LOG_ERR("%s: Error parsing num_dir_credits parameter",
3999 rte_kvargs_free(kvlist);
4003 ret = rte_kvargs_process(kvlist, DEV_ID_ARG,
4007 DLB_LOG_ERR("%s: Error parsing dev_id parameter",
4009 rte_kvargs_free(kvlist);
4013 ret = rte_kvargs_process(kvlist, DLB_DEFER_SCHED_ARG,
4015 &dlb_args->defer_sched);
4017 DLB_LOG_ERR("%s: Error parsing defer_sched parameter",
4019 rte_kvargs_free(kvlist);
4023 ret = rte_kvargs_process(kvlist,
4024 DLB_NUM_ATM_INFLIGHTS_ARG,
4025 set_num_atm_inflights,
4026 &dlb_args->num_atm_inflights);
4028 DLB_LOG_ERR("%s: Error parsing atm_inflights parameter",
4030 rte_kvargs_free(kvlist);
4034 rte_kvargs_free(kvlist);
4039 RTE_LOG_REGISTER(eventdev_dlb_log_level, pmd.event.dlb, NOTICE);