1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2020 Intel Corporation
11 #include <rte_eventdev.h>
12 #include <rte_config.h>
13 #include "dlb2_user.h"
15 #include "rte_pmd_dlb2.h"
17 #ifndef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
18 #define DLB2_INC_STAT(_stat, _incr_val) ((_stat) += _incr_val)
20 #define DLB2_INC_STAT(_stat, _incr_val)
23 #define EVDEV_DLB2_NAME_PMD dlb2_event
25 /* command line arg strings */
26 #define NUMA_NODE_ARG "numa_node"
27 #define DLB2_MAX_NUM_EVENTS "max_num_events"
28 #define DLB2_NUM_DIR_CREDITS "num_dir_credits"
29 #define DEV_ID_ARG "dev_id"
30 #define DLB2_DEFER_SCHED_ARG "defer_sched"
31 #define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh"
32 #define DLB2_COS_ARG "cos"
34 /* Begin HW related defines and structs */
37 #define DLB2_HW_V2_5 1
38 #define DLB2_MAX_NUM_DOMAINS 32
39 #define DLB2_MAX_NUM_VFS 16
40 #define DLB2_MAX_NUM_LDB_QUEUES 32
41 #define DLB2_MAX_NUM_LDB_PORTS 64
42 #define DLB2_MAX_NUM_DIR_PORTS_V2 DLB2_MAX_NUM_DIR_QUEUES_V2
43 #define DLB2_MAX_NUM_DIR_PORTS_V2_5 DLB2_MAX_NUM_DIR_QUEUES_V2_5
44 #define DLB2_MAX_NUM_DIR_PORTS(ver) (ver == DLB2_HW_V2 ? \
45 DLB2_MAX_NUM_DIR_PORTS_V2 : \
46 DLB2_MAX_NUM_DIR_PORTS_V2_5)
47 #define DLB2_MAX_NUM_DIR_QUEUES_V2 64 /* DIR == directed */
48 #define DLB2_MAX_NUM_DIR_QUEUES_V2_5 96
49 /* When needed for array sizing, the DLB 2.5 macro is used */
50 #define DLB2_MAX_NUM_DIR_QUEUES(ver) (ver == DLB2_HW_V2 ? \
51 DLB2_MAX_NUM_DIR_QUEUES_V2 : \
52 DLB2_MAX_NUM_DIR_QUEUES_V2_5)
53 #define DLB2_MAX_NUM_FLOWS (64 * 1024)
54 #define DLB2_MAX_NUM_LDB_CREDITS (8 * 1024)
55 #define DLB2_MAX_NUM_DIR_CREDITS(ver) (ver == DLB2_HW_V2 ? 4096 : 0)
56 #define DLB2_MAX_NUM_CREDITS(ver) (ver == DLB2_HW_V2 ? \
57 0 : DLB2_MAX_NUM_LDB_CREDITS)
58 #define DLB2_MAX_NUM_LDB_CREDIT_POOLS 64
59 #define DLB2_MAX_NUM_DIR_CREDIT_POOLS 64
60 #define DLB2_MAX_NUM_HIST_LIST_ENTRIES 2048
61 #define DLB2_MAX_NUM_QIDS_PER_LDB_CQ 8
62 #define DLB2_QID_PRIORITIES 8
63 #define DLB2_MAX_DEVICE_PATH 32
64 #define DLB2_MIN_DEQUEUE_TIMEOUT_NS 1
65 /* Note: "- 1" here to support the timeout range check in eventdev_autotest */
66 #define DLB2_MAX_DEQUEUE_TIMEOUT_NS (UINT32_MAX - 1)
67 #define DLB2_SW_CREDIT_BATCH_SZ 32
68 #define DLB2_NUM_SN_GROUPS 2
69 #define DLB2_MAX_LDB_SN_ALLOC 1024
70 #define DLB2_MAX_QUEUE_DEPTH_THRESHOLD 8191
72 /* 2048 total hist list entries and 64 total ldb ports, which
73 * makes for 2048/64 == 32 hist list entries per port. However, CQ
74 * depth must be a power of 2 and must also be >= HIST LIST entries.
75 * As a result we just limit the maximum dequeue depth to 32.
77 #define DLB2_MIN_CQ_DEPTH 1
78 #define DLB2_MAX_CQ_DEPTH 32
79 #define DLB2_MIN_HARDWARE_CQ_DEPTH 8
80 #define DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT \
83 #define DLB2_HW_DEVICE_FROM_PCI_ID(_pdev) \
84 (((_pdev->id.device_id == PCI_DEVICE_ID_INTEL_DLB2_5_PF) || \
85 (_pdev->id.device_id == PCI_DEVICE_ID_INTEL_DLB2_5_VF)) ? \
86 DLB2_HW_V2_5 : DLB2_HW_V2)
89 * Static per queue/port provisioning values
91 #define DLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE 64
93 #define CQ_BASE(is_dir) ((is_dir) ? DLB2_DIR_CQ_BASE : DLB2_LDB_CQ_BASE)
94 #define CQ_SIZE(is_dir) ((is_dir) ? DLB2_DIR_CQ_MAX_SIZE : \
96 #define PP_BASE(is_dir) ((is_dir) ? DLB2_DIR_PP_BASE : DLB2_LDB_PP_BASE)
98 #define DLB2_NUM_QES_PER_CACHE_LINE 4
100 #define DLB2_MAX_ENQUEUE_DEPTH 64
101 #define DLB2_MIN_ENQUEUE_DEPTH 4
103 #define DLB2_NAME_SIZE 64
106 #define DLB2_2K (2 * DLB2_1K)
107 #define DLB2_4K (4 * DLB2_1K)
108 #define DLB2_16K (16 * DLB2_1K)
109 #define DLB2_32K (32 * DLB2_1K)
110 #define DLB2_1MB (DLB2_1K * DLB2_1K)
111 #define DLB2_16MB (16 * DLB2_1MB)
113 /* Use the upper 3 bits of the event priority to select the DLB2 priority */
114 #define EV_TO_DLB2_PRIO(x) ((x) >> 5)
115 #define DLB2_TO_EV_PRIO(x) ((x) << 5)
122 enum dlb2_hw_port_types {
125 DLB2_NUM_PORT_TYPES /* Must be last */
128 enum dlb2_hw_queue_types {
131 DLB2_NUM_QUEUE_TYPES /* Must be last */
134 #define DLB2_COMBINED_POOL DLB2_LDB_QUEUE
136 #define PORT_TYPE(p) ((p)->is_directed ? DLB2_DIR_PORT : DLB2_LDB_PORT)
138 /* Do not change - must match hardware! */
139 enum dlb2_hw_sched_type {
140 DLB2_SCHED_ATOMIC = 0,
141 DLB2_SCHED_UNORDERED,
144 /* DLB2_NUM_HW_SCHED_TYPES must be last */
145 DLB2_NUM_HW_SCHED_TYPES
148 struct dlb2_hw_rsrcs {
149 int32_t nb_events_limit;
150 uint32_t num_queues; /* Total queues (lb + dir) */
151 uint32_t num_ldb_queues; /* Number of available ldb queues */
152 uint32_t num_ldb_ports; /* Number of load balanced ports */
153 uint32_t num_dir_ports; /* Number of directed ports */
156 uint32_t num_ldb_credits; /* Number of ldb credits */
157 uint32_t num_dir_credits; /* Number of dir credits */
160 uint32_t num_credits; /* Number of combined credits */
163 uint32_t reorder_window_size; /* Size of reorder window */
166 struct dlb2_hw_resource_info {
167 /**> Max resources that can be provided */
168 struct dlb2_hw_rsrcs hw_rsrc_max;
169 int num_sched_domains;
173 enum dlb2_enqueue_type {
175 * New : Used to inject a new packet into the QM.
179 * Forward : Enqueues a packet, and
180 * - if atomic: release any lock it holds in the QM
181 * - if ordered: release the packet for egress re-ordering
185 * Enqueue Drop : Release an inflight packet. Must be called with
186 * event == NULL. Used to drop a packet.
188 * Note that all packets dequeued from a load-balanced port must be
189 * released, either with DLB2_ENQ_DROP or DLB2_ENQ_FWD.
193 /* marker for array sizing etc. */
197 /* hw-specific format - do not change */
199 struct dlb2_event_type {
205 union dlb2_opaque_data {
206 uint16_t opaque_data;
207 struct dlb2_event_type event_type;
210 struct dlb2_msg_info {
212 uint8_t sched_type:2;
217 #define DLB2_NEW_CMD_BYTE 0x08
218 #define DLB2_FWD_CMD_BYTE 0x0A
219 #define DLB2_COMP_CMD_BYTE 0x02
220 #define DLB2_POP_CMD_BYTE 0x01
221 #define DLB2_NOOP_CMD_BYTE 0x00
223 /* hw-specific format - do not change */
224 struct dlb2_enqueue_qe {
227 union dlb2_opaque_data u;
229 uint8_t sched_type:2;
252 /* hw-specific format - do not change */
253 struct dlb2_cq_pop_qe {
255 union dlb2_opaque_data u;
257 uint8_t sched_type:2;
280 /* hw-specific format - do not change */
281 struct dlb2_dequeue_qe {
283 union dlb2_opaque_data u;
285 uint8_t sched_type:2;
288 uint16_t flow_id:16; /* was pp_id in v1 */
291 uint8_t qid_depth:2; /* 2 bits in v2 */
297 union dlb2_port_config {
298 struct dlb2_create_ldb_port_args ldb;
299 struct dlb2_create_dir_port_args dir;
302 enum dlb2_port_state {
308 enum dlb2_configuration_state {
309 /* The resource has not been configured */
311 /* The resource was configured, but the device was stopped */
312 DLB2_PREV_CONFIGURED,
313 /* The resource is currently configured */
321 uint16_t dir_credits;
322 uint32_t dequeue_depth;
323 enum dlb2_token_pop_mode token_pop_mode;
324 union dlb2_port_config cfg;
325 uint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */
328 uint16_t cached_ldb_credits;
329 uint16_t ldb_credits;
330 uint16_t cached_dir_credits;
333 uint16_t cached_credits;
338 uint16_t owed_tokens;
339 int16_t issued_releases;
340 int16_t token_pop_thresh;
343 uint16_t cq_idx_unmasked;
344 uint16_t cq_depth_mask;
345 uint16_t gen_bit_shift;
346 enum dlb2_port_state state;
347 enum dlb2_configuration_state config_state;
349 uint8_t *qid_mappings;
350 struct dlb2_enqueue_qe *qe4; /* Cache line's worth of QEs (4) */
351 struct dlb2_enqueue_qe *int_arm_qe;
352 struct dlb2_cq_pop_qe *consume_qe;
353 struct dlb2_eventdev *dlb2; /* back ptr */
354 struct dlb2_eventdev_port *ev_port; /* back ptr */
357 /* Per-process per-port mmio and memory pointers */
358 struct process_local_port_data {
360 struct dlb2_dequeue_qe *cq_base;
361 const struct rte_memzone *mz;
365 struct dlb2_eventdev;
367 struct dlb2_port_low_level_io_functions {
368 void (*pp_enqueue_four)(void *qe4, void *pp_addr);
376 uint32_t num_ldb_credits;
377 uint32_t num_dir_credits;
380 uint32_t num_credits;
383 struct dlb2_create_sched_domain_args resources;
387 DLB2_COS_DEFAULT = -1,
395 struct dlb2_config cfg;
396 struct dlb2_hw_resource_info info;
397 void *pf_dev; /* opaque pointer to PF PMD dev (struct dlb2_dev) */
399 enum dlb2_cos cos_id;
400 rte_spinlock_t resource_lock; /* for MP support */
401 } __rte_cache_aligned;
403 /* End HW related defines and structs */
405 /* Begin DLB2 PMD Eventdev related defines and structs */
407 #define DLB2_MAX_NUM_QUEUES(ver) \
408 (DLB2_MAX_NUM_DIR_QUEUES(ver) + DLB2_MAX_NUM_LDB_QUEUES)
410 #define DLB2_MAX_NUM_PORTS(ver) \
411 (DLB2_MAX_NUM_DIR_PORTS(ver) + DLB2_MAX_NUM_LDB_PORTS)
413 #define DLB2_MAX_NUM_DIR_QUEUES_V2_5 96
414 #define DLB2_MAX_NUM_DIR_PORTS_V2_5 DLB2_MAX_NUM_DIR_QUEUES_V2_5
415 #define DLB2_MAX_NUM_QUEUES_ALL \
416 (DLB2_MAX_NUM_DIR_QUEUES_V2_5 + DLB2_MAX_NUM_LDB_QUEUES)
417 #define DLB2_MAX_NUM_PORTS_ALL \
418 (DLB2_MAX_NUM_DIR_PORTS_V2_5 + DLB2_MAX_NUM_LDB_PORTS)
419 #define DLB2_MAX_INPUT_QUEUE_DEPTH 256
421 /** Structure to hold the queue to port link establishment attributes */
423 struct dlb2_event_queue_link {
430 struct dlb2_traffic_stats {
433 uint64_t rx_interrupt_wait;
434 uint64_t rx_umonitor_umwait;
436 uint64_t total_polls;
440 uint64_t tx_nospc_ldb_hw_credits;
441 uint64_t tx_nospc_dir_hw_credits;
444 uint64_t tx_nospc_hw_credits;
447 uint64_t tx_nospc_inflight_max;
448 uint64_t tx_nospc_new_event_limit;
449 uint64_t tx_nospc_inflight_credits;
452 /* DLB2 HW sets the 2bit qid_depth in rx QEs based on the programmable depth
453 * threshold. The global default value in config/common_base (or rte_config.h)
454 * can be overridden on a per-qid basis using a vdev command line parameter.
455 * 3: depth > threshold
456 * 2: threshold >= depth > 3/4 threshold
457 * 1: 3/4 threshold >= depth > 1/2 threshold
458 * 0: depth <= 1/2 threshold.
460 #define DLB2_QID_DEPTH_LE50 0
461 #define DLB2_QID_DEPTH_GT50_LE75 1
462 #define DLB2_QID_DEPTH_GT75_LE100 2
463 #define DLB2_QID_DEPTH_GT100 3
464 #define DLB2_NUM_QID_DEPTH_STAT_VALS 4 /* 2 bits */
466 struct dlb2_queue_stats {
468 uint64_t qid_depth[DLB2_NUM_QID_DEPTH_STAT_VALS];
471 struct dlb2_port_stats {
472 struct dlb2_traffic_stats traffic;
473 uint64_t tx_op_cnt[4]; /* indexed by rte_event.op */
474 uint64_t tx_implicit_rel;
475 uint64_t tx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];
477 uint64_t rx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];
478 uint64_t rx_sched_invalid;
479 struct dlb2_queue_stats queue[DLB2_MAX_NUM_QUEUES_ALL];
482 struct dlb2_eventdev_port {
483 struct dlb2_port qm_port; /* hw specific data structure */
484 struct rte_event_port_conf conf; /* user-supplied configuration */
485 uint16_t inflight_credits; /* num credits this port has right now */
486 uint16_t credit_update_quanta;
487 struct dlb2_eventdev *dlb2; /* backlink optimization */
488 struct dlb2_port_stats stats __rte_cache_aligned;
489 struct dlb2_event_queue_link link[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];
491 uint32_t id; /* port id */
492 /* num releases yet to be completed on this port.
493 * Only applies to load-balanced ports.
495 uint16_t outstanding_releases;
496 uint16_t inflight_max; /* app requested max inflights for this port */
497 /* setup_done is set when the event port is setup */
499 /* enq_configured is set when the qm port is created */
501 uint8_t implicit_release; /* release events before dequeueing */
502 } __rte_cache_aligned;
505 uint32_t num_qid_inflights; /* User config */
506 uint32_t num_atm_inflights; /* User config */
507 enum dlb2_configuration_state config_state;
508 int sched_type; /* LB queue only */
513 struct dlb2_eventdev_queue {
514 struct dlb2_queue qm_queue;
515 struct rte_event_queue_conf conf; /* User config */
516 int depth_threshold; /* use default if 0 */
522 enum dlb2_run_state {
523 DLB2_RUN_STATE_STOPPED = 0,
524 DLB2_RUN_STATE_STOPPING,
525 DLB2_RUN_STATE_STARTING,
526 DLB2_RUN_STATE_STARTED
529 struct dlb2_eventdev {
530 struct dlb2_eventdev_port ev_ports[DLB2_MAX_NUM_PORTS_ALL];
531 struct dlb2_eventdev_queue ev_queues[DLB2_MAX_NUM_QUEUES_ALL];
532 uint8_t qm_ldb_to_ev_queue_id[DLB2_MAX_NUM_QUEUES_ALL];
533 uint8_t qm_dir_to_ev_queue_id[DLB2_MAX_NUM_QUEUES_ALL];
534 /* store num stats and offset of the stats for each queue */
535 uint16_t xstats_count_per_qid[DLB2_MAX_NUM_QUEUES_ALL];
536 uint16_t xstats_offset_for_qid[DLB2_MAX_NUM_QUEUES_ALL];
537 /* store num stats and offset of the stats for each port */
538 uint16_t xstats_count_per_port[DLB2_MAX_NUM_PORTS_ALL];
539 uint16_t xstats_offset_for_port[DLB2_MAX_NUM_PORTS_ALL];
540 struct dlb2_get_num_resources_args hw_rsrc_query_results;
541 uint32_t xstats_count_mode_queue;
542 struct dlb2_hw_dev qm_instance; /* strictly hw related */
543 uint64_t global_dequeue_wait_ticks;
544 struct dlb2_xstats_entry *xstats;
545 struct rte_eventdev *event_dev; /* backlink to dev */
546 uint32_t xstats_count_mode_dev;
547 uint32_t xstats_count_mode_port;
548 uint32_t xstats_count;
549 uint32_t inflights; /* use __atomic builtins */
550 uint32_t new_event_limit;
551 int max_num_events_override;
552 int num_dir_credits_override;
553 volatile enum dlb2_run_state run_state;
554 uint16_t num_dir_queues; /* total num of evdev dir queues requested */
557 uint16_t num_dir_credits;
558 uint16_t num_ldb_credits;
561 uint16_t num_credits;
564 uint16_t num_queues; /* total queues */
565 uint16_t num_ldb_queues; /* total num of evdev ldb queues requested */
566 uint16_t num_ports; /* total num of evdev ports requested */
567 uint16_t num_ldb_ports; /* total num of ldb ports requested */
568 uint16_t num_dir_ports; /* total num of dir ports requested */
570 bool global_dequeue_wait; /* Not using per dequeue wait if true */
572 enum dlb2_cq_poll_modes poll_mode;
578 uint16_t max_ldb_credits;
579 uint16_t max_dir_credits;
580 /* use __atomic builtins */ /* shared hw cred */
581 uint32_t ldb_credit_pool __rte_cache_aligned;
582 /* use __atomic builtins */ /* shared hw cred */
583 uint32_t dir_credit_pool __rte_cache_aligned;
586 uint16_t max_credits;
587 /* use __atomic builtins */ /* shared hw cred */
588 uint32_t credit_pool __rte_cache_aligned;
593 /* used for collecting and passing around the dev args */
594 struct dlb2_qid_depth_thresholds {
595 int val[DLB2_MAX_NUM_QUEUES_ALL];
598 struct dlb2_devargs {
601 int num_dir_credits_override;
604 struct dlb2_qid_depth_thresholds qid_depth_thresholds;
605 enum dlb2_cos cos_id;
608 /* End Eventdev related defines and structs */
610 /* Forwards for non-inlined functions */
612 void dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f);
614 int dlb2_xstats_init(struct dlb2_eventdev *dlb2);
616 void dlb2_xstats_uninit(struct dlb2_eventdev *dlb2);
618 int dlb2_eventdev_xstats_get(const struct rte_eventdev *dev,
619 enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
620 const unsigned int ids[], uint64_t values[], unsigned int n);
622 int dlb2_eventdev_xstats_get_names(const struct rte_eventdev *dev,
623 enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
624 struct rte_event_dev_xstats_name *xstat_names,
625 unsigned int *ids, unsigned int size);
627 uint64_t dlb2_eventdev_xstats_get_by_name(const struct rte_eventdev *dev,
628 const char *name, unsigned int *id);
630 int dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
631 enum rte_event_dev_xstats_mode mode,
632 int16_t queue_port_id,
633 const uint32_t ids[],
636 int test_dlb2_eventdev(void);
638 int dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
640 struct dlb2_devargs *dlb2_args);
642 int dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,
645 uint32_t dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,
646 struct dlb2_eventdev_queue *queue);
648 int dlb2_parse_params(const char *params,
650 struct dlb2_devargs *dlb2_args,
654 extern struct process_local_port_data dlb2_port[][DLB2_NUM_PORT_TYPES];
656 #endif /* _DLB2_PRIV_H_ */