1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2020 Intel Corporation
5 #ifndef __DLB2_HW_TYPES_H
6 #define __DLB2_HW_TYPES_H
8 #include "../../dlb2_priv.h"
11 #include "dlb2_osdep_list.h"
12 #include "dlb2_osdep_types.h"
14 #define DLB2_MAX_NUM_VDEVS 16
15 #define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS 2
16 #define DLB2_NUM_ARB_WEIGHTS 8
17 #define DLB2_MAX_NUM_AQED_ENTRIES 2048
18 #define DLB2_MAX_WEIGHT 255
19 #define DLB2_NUM_COS_DOMAINS 4
20 #define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS 2
21 #define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES 5
22 #define DLB2_MAX_CQ_COMP_CHECK_LOOPS 409600
23 #define DLB2_MAX_QID_EMPTY_CHECK_LOOPS (32 * 64 * 1024 * (800 / 30))
25 #define DLB2_FUNC_BAR 0
26 #define DLB2_CSR_BAR 2
28 #define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710
29 #define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711
31 #define PCI_DEVICE_ID_INTEL_DLB2_5_PF 0x2714
32 #define PCI_DEVICE_ID_INTEL_DLB2_5_VF 0x2715
34 #define DLB2_ALARM_HW_SOURCE_SYS 0
35 #define DLB2_ALARM_HW_SOURCE_DLB 1
37 #define DLB2_ALARM_HW_UNIT_CHP 4
39 #define DLB2_ALARM_SYS_AID_ILLEGAL_QID 3
40 #define DLB2_ALARM_SYS_AID_DISABLED_QID 4
41 #define DLB2_ALARM_SYS_AID_ILLEGAL_HCW 5
42 #define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ 1
43 #define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2
46 * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by
49 #define DLB2_DRV_LDB_PP_BASE 0x2300000
50 #define DLB2_DRV_LDB_PP_STRIDE 0x1000
51 #define DLB2_DRV_LDB_PP_BOUND (DLB2_DRV_LDB_PP_BASE + \
52 DLB2_DRV_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)
53 #define DLB2_DRV_DIR_PP_BASE 0x2200000
54 #define DLB2_DRV_DIR_PP_STRIDE 0x1000
55 #define DLB2_DRV_DIR_PP_BOUND (DLB2_DRV_DIR_PP_BASE + \
56 DLB2_DRV_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)
57 #define DLB2_LDB_PP_BASE 0x2100000
58 #define DLB2_LDB_PP_STRIDE 0x1000
59 #define DLB2_LDB_PP_BOUND (DLB2_LDB_PP_BASE + \
60 DLB2_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)
61 #define DLB2_LDB_PP_OFFS(id) (DLB2_LDB_PP_BASE + (id) * DLB2_PP_SIZE)
62 #define DLB2_DIR_PP_BASE 0x2000000
63 #define DLB2_DIR_PP_STRIDE 0x1000
64 #define DLB2_DIR_PP_BOUND (DLB2_DIR_PP_BASE + \
65 DLB2_DIR_PP_STRIDE * \
66 DLB2_MAX_NUM_DIR_PORTS_V2_5)
67 #define DLB2_DIR_PP_OFFS(id) (DLB2_DIR_PP_BASE + (id) * DLB2_PP_SIZE)
69 struct dlb2_resource_id {
76 struct dlb2_freelist {
82 static inline u32 dlb2_freelist_count(struct dlb2_freelist *list)
84 return list->bound - list->base - list->offset;
110 struct dlb2_ldb_queue {
111 struct dlb2_list_entry domain_list;
112 struct dlb2_list_entry func_list;
113 struct dlb2_resource_id id;
114 struct dlb2_resource_id domain_id;
115 u32 num_qid_inflights;
117 u32 sn_group; /* sn == sequence number */
121 u8 num_pending_additions;
127 * Directed ports and queues are paired by nature, so the driver tracks them
128 * with a single data structure.
130 struct dlb2_dir_pq_pair {
131 struct dlb2_list_entry domain_list;
132 struct dlb2_list_entry func_list;
133 struct dlb2_resource_id id;
134 struct dlb2_resource_id domain_id;
143 enum dlb2_qid_map_state {
144 /* The slot doesn't contain a valid queue mapping */
146 /* The slot contains a valid queue mapping */
148 /* The driver is mapping a queue into this slot */
149 DLB2_QUEUE_MAP_IN_PROG,
150 /* The driver is unmapping a queue from this slot */
151 DLB2_QUEUE_UNMAP_IN_PROG,
153 * The driver is unmapping a queue from this slot, and once complete
154 * will replace it with another mapping.
156 DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP,
159 struct dlb2_ldb_port_qid_map {
160 enum dlb2_qid_map_state state;
167 struct dlb2_ldb_port {
168 struct dlb2_list_entry domain_list;
169 struct dlb2_list_entry func_list;
170 struct dlb2_resource_id id;
171 struct dlb2_resource_id domain_id;
172 /* The qid_map represents the hardware QID mapping state. */
173 struct dlb2_ldb_port_qid_map qid_map[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];
174 u32 hist_list_entry_base;
175 u32 hist_list_entry_limit;
178 u8 num_pending_removals;
185 struct dlb2_sn_group {
187 u32 sequence_numbers_per_queue;
192 static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)
195 0x0000ffff, /* 64 SNs per queue */
196 0x000000ff, /* 128 SNs per queue */
197 0x0000000f, /* 256 SNs per queue */
198 0x00000003, /* 512 SNs per queue */
199 0x00000001}; /* 1024 SNs per queue */
201 return group->slot_use_bitmap == mask[group->mode];
204 static inline int dlb2_sn_group_alloc_slot(struct dlb2_sn_group *group)
206 const u32 bound[] = {16, 8, 4, 2, 1};
209 for (i = 0; i < bound[group->mode]; i++) {
210 if (!(group->slot_use_bitmap & (1 << i))) {
211 group->slot_use_bitmap |= 1 << i;
220 dlb2_sn_group_free_slot(struct dlb2_sn_group *group, int slot)
222 group->slot_use_bitmap &= ~(1 << slot);
225 static inline int dlb2_sn_group_used_slots(struct dlb2_sn_group *group)
229 for (i = 0; i < 32; i++)
230 cnt += !!(group->slot_use_bitmap & (1 << i));
235 struct dlb2_hw_domain {
236 struct dlb2_function_resources *parent_func;
237 struct dlb2_list_entry func_list;
238 struct dlb2_list_head used_ldb_queues;
239 struct dlb2_list_head used_ldb_ports[DLB2_NUM_COS_DOMAINS];
240 struct dlb2_list_head used_dir_pq_pairs;
241 struct dlb2_list_head avail_ldb_queues;
242 struct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
243 struct dlb2_list_head avail_dir_pq_pairs;
244 u32 total_hist_list_entries;
245 u32 avail_hist_list_entries;
246 u32 hist_list_entry_base;
247 u32 hist_list_entry_offset;
250 u32 num_avail_aqed_entries;
251 u32 num_used_aqed_entries;
252 struct dlb2_resource_id id;
253 int num_pending_removals;
254 int num_pending_additions;
261 struct dlb2_function_resources {
262 struct dlb2_list_head avail_domains;
263 struct dlb2_list_head used_domains;
264 struct dlb2_list_head avail_ldb_queues;
265 struct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
266 struct dlb2_list_head avail_dir_pq_pairs;
267 struct dlb2_bitmap *avail_hist_list_entries;
268 u32 num_avail_domains;
269 u32 num_avail_ldb_queues;
270 u32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];
271 u32 num_avail_dir_pq_pairs;
272 u32 num_avail_qed_entries;
273 u32 num_avail_dqed_entries;
274 u32 num_avail_aqed_entries;
275 u8 locked; /* (VDEV only) */
279 * After initialization, each resource in dlb2_hw_resources is located in one
280 * of the following lists:
281 * -- The PF's available resources list. These are unconfigured resources owned
282 * by the PF and not allocated to a dlb2 scheduling domain.
283 * -- A VDEV's available resources list. These are VDEV-owned unconfigured
284 * resources not allocated to a dlb2 scheduling domain.
285 * -- A domain's available resources list. These are domain-owned unconfigured
287 * -- A domain's used resources list. These are domain-owned configured
290 * A resource moves to a new list when a VDEV or domain is created or destroyed,
291 * or when the resource is configured.
293 struct dlb2_hw_resources {
294 struct dlb2_ldb_queue ldb_queues[DLB2_MAX_NUM_LDB_QUEUES];
295 struct dlb2_ldb_port ldb_ports[DLB2_MAX_NUM_LDB_PORTS];
296 struct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS_V2_5];
297 struct dlb2_sn_group sn_groups[DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS];
302 u32 *isr_in_progress;
305 struct dlb2_sw_mbox {
306 struct dlb2_mbox vdev_to_pf;
307 struct dlb2_mbox pf_to_vdev;
308 void (*pf_to_vdev_inject)(void *arg);
309 void *pf_to_vdev_inject_arg;
317 unsigned long csr_phys_addr;
320 unsigned long func_phys_addr;
322 /* Resource tracking */
323 struct dlb2_hw_resources rsrcs;
324 struct dlb2_function_resources pf;
325 struct dlb2_function_resources vdev[DLB2_MAX_NUM_VDEVS];
326 struct dlb2_hw_domain domains[DLB2_MAX_NUM_DOMAINS];
327 u8 cos_reservation[DLB2_NUM_COS_DOMAINS];
331 struct dlb2_sw_mbox mbox[DLB2_MAX_NUM_VDEVS];
332 unsigned int pasid[DLB2_MAX_NUM_VDEVS];
335 #endif /* __DLB2_HW_TYPES_H */