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40 #include <sys/epoll.h>
42 #include <rte_atomic.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_debug.h>
48 #include <rte_fslmc.h>
49 #include <rte_lcore.h>
51 #include <rte_malloc.h>
52 #include <rte_memcpy.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
58 #include <fslmc_vfio.h>
59 #include <dpaa2_hw_pvt.h>
60 #include <dpaa2_hw_mempool.h>
61 #include <dpaa2_hw_dpio.h>
62 #include "dpaa2_eventdev.h"
63 #include <portal/dpaa2_hw_pvt.h>
64 #include <mc/fsl_dpci.h>
67 * Evendev = SoC Instance
68 * Eventport = DPIO Instance
69 * Eventqueue = DPCON Instance
70 * 1 Eventdev can have N Eventqueue
71 * Soft Event Flow is DPCI Instance
75 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
78 struct rte_eventdev *ev_dev =
79 ((struct dpaa2_io_portal_t *)port)->eventdev;
80 struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
81 uint32_t queue_id = ev[0].queue_id;
82 struct evq_info_t *evq_info = &priv->evq_info[queue_id];
84 struct qbman_swp *swp;
85 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
86 uint32_t loop, frames_to_send;
87 struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
93 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
94 ret = dpaa2_affine_qbman_swp();
96 PMD_DRV_LOG(ERR, PMD, "Failure in affining portal\n");
101 swp = DPAA2_PER_LCORE_PORTAL;
104 frames_to_send = (nb_events >> 3) ?
105 MAX_TX_RING_SLOTS : nb_events;
107 for (loop = 0; loop < frames_to_send; loop++) {
108 const struct rte_event *event = &ev[num_tx + loop];
110 if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
111 fqid = evq_info->dpci->queue[
112 DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
114 fqid = evq_info->dpci->queue[
115 DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
117 /* Prepare enqueue descriptor */
118 qbman_eq_desc_clear(&eqdesc[loop]);
119 qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
120 qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
121 qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
123 if (event->impl_opaque) {
124 uint8_t dqrr_index = event->impl_opaque - 1;
126 qbman_eq_desc_set_dca(&eqdesc[loop], 1,
128 DPAA2_PER_LCORE_DPIO->dqrr_size--;
129 DPAA2_PER_LCORE_DPIO->dqrr_held &=
133 memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
136 * todo - need to align with hw context data
139 struct rte_event *ev_temp = rte_malloc(NULL,
140 sizeof(struct rte_event), 0);
141 rte_memcpy(ev_temp, event, sizeof(struct rte_event));
142 DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
143 DPAA2_SET_FD_LEN((&fd_arr[loop]),
144 sizeof(struct rte_event));
147 while (loop < frames_to_send) {
148 loop += qbman_swp_enqueue_multiple_eqdesc(swp,
149 &eqdesc[loop], &fd_arr[loop],
150 frames_to_send - loop);
152 num_tx += frames_to_send;
153 nb_events -= frames_to_send;
160 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
162 return dpaa2_eventdev_enqueue_burst(port, ev, 1);
165 static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
167 struct epoll_event epoll_ev;
170 qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
171 QBMAN_SWP_INTERRUPT_DQRI);
174 ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
175 &epoll_ev, 1, timeout_ticks);
177 /* sometimes due to some spurious interrupts epoll_wait fails
178 * with errno EINTR. so here we are retrying epoll_wait in such
179 * case to avoid the problem.
181 if (errno == EINTR) {
182 PMD_DRV_LOG(DEBUG, PMD, "epoll_wait fails\n");
184 PMD_DRV_LOG(DEBUG, PMD,
185 "Dequeue burst Failed\n");
191 static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
192 const struct qbman_fd *fd,
193 const struct qbman_result *dq,
194 struct rte_event *ev)
196 struct rte_event *ev_temp =
197 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
198 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
201 qbman_swp_dqrr_consume(swp, dq);
204 static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
205 const struct qbman_fd *fd,
206 const struct qbman_result *dq,
207 struct rte_event *ev)
209 struct rte_event *ev_temp =
210 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
211 uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
215 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
217 ev->impl_opaque = dqrr_index + 1;
218 DPAA2_PER_LCORE_DPIO->dqrr_size++;
219 DPAA2_PER_LCORE_DPIO->dqrr_held |= 1 << dqrr_index;
223 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
224 uint16_t nb_events, uint64_t timeout_ticks)
226 const struct qbman_result *dq;
227 struct qbman_swp *swp;
228 const struct qbman_fd *fd;
229 struct dpaa2_queue *rxq;
230 int num_pkts = 0, ret, i = 0;
234 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
235 ret = dpaa2_affine_qbman_swp();
237 PMD_DRV_LOG(ERR, PMD, "Failure in affining portal\n");
242 swp = DPAA2_PER_LCORE_PORTAL;
244 /* Check if there are atomic contexts to be released */
245 while (DPAA2_PER_LCORE_DPIO->dqrr_size) {
246 if (DPAA2_PER_LCORE_DPIO->dqrr_held & (1 << i)) {
247 dq = qbman_get_dqrr_from_idx(swp, i);
248 qbman_swp_dqrr_consume(swp, dq);
249 DPAA2_PER_LCORE_DPIO->dqrr_size--;
253 DPAA2_PER_LCORE_DPIO->dqrr_held = 0;
256 dq = qbman_swp_dqrr_next(swp);
258 if (!num_pkts && timeout_ticks) {
259 dpaa2_eventdev_dequeue_wait(timeout_ticks);
266 fd = qbman_result_DQ_fd(dq);
268 rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
270 rxq->cb(swp, fd, dq, &ev[num_pkts]);
272 qbman_swp_dqrr_consume(swp, dq);
273 PMD_DRV_LOG(ERR, PMD, "Null Return VQ received\n");
278 } while (num_pkts < nb_events);
284 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
285 uint64_t timeout_ticks)
287 return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
291 dpaa2_eventdev_info_get(struct rte_eventdev *dev,
292 struct rte_event_dev_info *dev_info)
294 struct dpaa2_eventdev *priv = dev->data->dev_private;
296 PMD_DRV_FUNC_TRACE();
300 memset(dev_info, 0, sizeof(struct rte_event_dev_info));
301 dev_info->min_dequeue_timeout_ns =
302 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
303 dev_info->max_dequeue_timeout_ns =
304 DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
305 dev_info->dequeue_timeout_ns =
306 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
307 dev_info->max_event_queues = priv->max_event_queues;
308 dev_info->max_event_queue_flows =
309 DPAA2_EVENT_MAX_QUEUE_FLOWS;
310 dev_info->max_event_queue_priority_levels =
311 DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
312 dev_info->max_event_priority_levels =
313 DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
314 dev_info->max_event_ports = RTE_MAX_LCORE;
315 dev_info->max_event_port_dequeue_depth =
316 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
317 dev_info->max_event_port_enqueue_depth =
318 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
319 dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
320 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED;
324 dpaa2_eventdev_configure(const struct rte_eventdev *dev)
326 struct dpaa2_eventdev *priv = dev->data->dev_private;
327 struct rte_event_dev_config *conf = &dev->data->dev_conf;
329 PMD_DRV_FUNC_TRACE();
331 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
332 priv->nb_event_queues = conf->nb_event_queues;
333 priv->nb_event_ports = conf->nb_event_ports;
334 priv->nb_event_queue_flows = conf->nb_event_queue_flows;
335 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
336 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
337 priv->event_dev_cfg = conf->event_dev_cfg;
339 PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id);
344 dpaa2_eventdev_start(struct rte_eventdev *dev)
346 PMD_DRV_FUNC_TRACE();
354 dpaa2_eventdev_stop(struct rte_eventdev *dev)
356 PMD_DRV_FUNC_TRACE();
362 dpaa2_eventdev_close(struct rte_eventdev *dev)
364 PMD_DRV_FUNC_TRACE();
372 dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
373 struct rte_event_queue_conf *queue_conf)
375 PMD_DRV_FUNC_TRACE();
378 RTE_SET_USED(queue_id);
379 RTE_SET_USED(queue_conf);
381 queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
382 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY |
383 RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;
384 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
388 dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
390 PMD_DRV_FUNC_TRACE();
393 RTE_SET_USED(queue_id);
397 dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
398 const struct rte_event_queue_conf *queue_conf)
400 struct dpaa2_eventdev *priv = dev->data->dev_private;
401 struct evq_info_t *evq_info =
402 &priv->evq_info[queue_id];
404 PMD_DRV_FUNC_TRACE();
406 evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
412 dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
413 struct rte_event_port_conf *port_conf)
415 PMD_DRV_FUNC_TRACE();
418 RTE_SET_USED(port_id);
419 RTE_SET_USED(port_conf);
421 port_conf->new_event_threshold =
422 DPAA2_EVENT_MAX_NUM_EVENTS;
423 port_conf->dequeue_depth =
424 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
425 port_conf->enqueue_depth =
426 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
430 dpaa2_eventdev_port_release(void *port)
432 PMD_DRV_FUNC_TRACE();
438 dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
439 const struct rte_event_port_conf *port_conf)
441 PMD_DRV_FUNC_TRACE();
443 RTE_SET_USED(port_conf);
445 if (!dpaa2_io_portal[port_id].dpio_dev) {
446 dpaa2_io_portal[port_id].dpio_dev =
447 dpaa2_get_qbman_swp(port_id);
448 rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
449 if (!dpaa2_io_portal[port_id].dpio_dev)
453 dpaa2_io_portal[port_id].eventdev = dev;
454 dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
459 dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
460 uint8_t queues[], uint16_t nb_unlinks)
462 struct dpaa2_eventdev *priv = dev->data->dev_private;
463 struct dpaa2_io_portal_t *dpaa2_portal = port;
464 struct evq_info_t *evq_info;
467 PMD_DRV_FUNC_TRACE();
469 for (i = 0; i < nb_unlinks; i++) {
470 evq_info = &priv->evq_info[queues[i]];
471 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
472 evq_info->dpcon->channel_index, 0);
473 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
474 0, dpaa2_portal->dpio_dev->token,
475 evq_info->dpcon->dpcon_id);
479 return (int)nb_unlinks;
483 dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
484 const uint8_t queues[], const uint8_t priorities[],
487 struct dpaa2_eventdev *priv = dev->data->dev_private;
488 struct dpaa2_io_portal_t *dpaa2_portal = port;
489 struct evq_info_t *evq_info;
490 uint8_t channel_index;
493 PMD_DRV_FUNC_TRACE();
495 for (i = 0; i < nb_links; i++) {
496 evq_info = &priv->evq_info[queues[i]];
500 ret = dpio_add_static_dequeue_channel(
501 dpaa2_portal->dpio_dev->dpio,
502 CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
503 evq_info->dpcon->dpcon_id, &channel_index);
505 PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n",
510 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
512 evq_info->dpcon->channel_index = channel_index;
516 RTE_SET_USED(priorities);
518 return (int)nb_links;
520 for (n = 0; n < i; n++) {
521 evq_info = &priv->evq_info[queues[n]];
522 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
523 evq_info->dpcon->channel_index, 0);
524 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
525 0, dpaa2_portal->dpio_dev->token,
526 evq_info->dpcon->dpcon_id);
533 dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
534 uint64_t *timeout_ticks)
538 PMD_DRV_FUNC_TRACE();
541 *timeout_ticks = ns * scale;
547 dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
549 PMD_DRV_FUNC_TRACE();
555 static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
556 .dev_infos_get = dpaa2_eventdev_info_get,
557 .dev_configure = dpaa2_eventdev_configure,
558 .dev_start = dpaa2_eventdev_start,
559 .dev_stop = dpaa2_eventdev_stop,
560 .dev_close = dpaa2_eventdev_close,
561 .queue_def_conf = dpaa2_eventdev_queue_def_conf,
562 .queue_setup = dpaa2_eventdev_queue_setup,
563 .queue_release = dpaa2_eventdev_queue_release,
564 .port_def_conf = dpaa2_eventdev_port_def_conf,
565 .port_setup = dpaa2_eventdev_port_setup,
566 .port_release = dpaa2_eventdev_port_release,
567 .port_link = dpaa2_eventdev_port_link,
568 .port_unlink = dpaa2_eventdev_port_unlink,
569 .timeout_ticks = dpaa2_eventdev_timeout_ticks,
570 .dump = dpaa2_eventdev_dump
574 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
575 struct dpaa2_dpcon_dev *dpcon_dev)
577 struct dpci_rx_queue_cfg rx_queue_cfg;
580 /*Do settings to get the frame on a DPCON object*/
581 rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
582 DPCI_QUEUE_OPT_USER_CTX;
583 rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
584 rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
585 rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
587 dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
588 dpaa2_eventdev_process_parallel;
589 dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
590 dpaa2_eventdev_process_atomic;
592 for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
593 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
594 ret = dpci_set_rx_queue(&dpci_dev->dpci,
599 PMD_DRV_LOG(ERR, PMD,
600 "set_rx_q failed with err code: %d", ret);
608 dpaa2_eventdev_create(const char *name)
610 struct rte_eventdev *eventdev;
611 struct dpaa2_eventdev *priv;
612 struct dpaa2_dpcon_dev *dpcon_dev = NULL;
613 struct dpaa2_dpci_dev *dpci_dev = NULL;
616 eventdev = rte_event_pmd_vdev_init(name,
617 sizeof(struct dpaa2_eventdev),
619 if (eventdev == NULL) {
620 PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
624 eventdev->dev_ops = &dpaa2_eventdev_ops;
625 eventdev->schedule = NULL;
626 eventdev->enqueue = dpaa2_eventdev_enqueue;
627 eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
628 eventdev->enqueue_new_burst = dpaa2_eventdev_enqueue_burst;
629 eventdev->enqueue_forward_burst = dpaa2_eventdev_enqueue_burst;
630 eventdev->dequeue = dpaa2_eventdev_dequeue;
631 eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
633 /* For secondary processes, the primary has done all the work */
634 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
637 priv = eventdev->data->dev_private;
638 priv->max_event_queues = 0;
641 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
644 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
646 dpci_dev = rte_dpaa2_alloc_dpci_dev();
648 rte_dpaa2_free_dpcon_dev(dpcon_dev);
651 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
653 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
655 PMD_DRV_LOG(ERR, PMD,
656 "dpci setup failed with err code: %d", ret);
659 priv->max_event_queues++;
660 } while (dpcon_dev && dpci_dev);
668 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
672 name = rte_vdev_device_name(vdev);
673 PMD_DRV_LOG(INFO, PMD, "Initializing %s\n", name);
674 return dpaa2_eventdev_create(name);
678 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
682 name = rte_vdev_device_name(vdev);
683 PMD_DRV_LOG(INFO, "Closing %s", name);
685 return rte_event_pmd_vdev_uninit(name);
688 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
689 .probe = dpaa2_eventdev_probe,
690 .remove = dpaa2_eventdev_remove
693 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);