1 /* SPDX-License-Identifier: BSD-3-Clause
13 #include <sys/epoll.h>
15 #include <rte_atomic.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_debug.h>
21 #include <rte_fslmc.h>
22 #include <rte_lcore.h>
24 #include <rte_malloc.h>
25 #include <rte_memcpy.h>
26 #include <rte_memory.h>
28 #include <rte_bus_vdev.h>
29 #include <rte_ethdev.h>
30 #include <rte_event_eth_rx_adapter.h>
32 #include <fslmc_vfio.h>
33 #include <dpaa2_hw_pvt.h>
34 #include <dpaa2_hw_mempool.h>
35 #include <dpaa2_hw_dpio.h>
36 #include <dpaa2_ethdev.h>
37 #include "dpaa2_eventdev.h"
38 #include <portal/dpaa2_hw_pvt.h>
39 #include <mc/fsl_dpci.h>
42 * Evendev = SoC Instance
43 * Eventport = DPIO Instance
44 * Eventqueue = DPCON Instance
45 * 1 Eventdev can have N Eventqueue
46 * Soft Event Flow is DPCI Instance
50 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
53 struct rte_eventdev *ev_dev =
54 ((struct dpaa2_io_portal_t *)port)->eventdev;
55 struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
56 uint32_t queue_id = ev[0].queue_id;
57 struct evq_info_t *evq_info = &priv->evq_info[queue_id];
59 struct qbman_swp *swp;
60 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
61 uint32_t loop, frames_to_send;
62 struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
68 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
69 ret = dpaa2_affine_qbman_swp();
71 PMD_DRV_LOG(ERR, "Failure in affining portal\n");
76 swp = DPAA2_PER_LCORE_PORTAL;
79 frames_to_send = (nb_events >> 3) ?
80 MAX_TX_RING_SLOTS : nb_events;
82 for (loop = 0; loop < frames_to_send; loop++) {
83 const struct rte_event *event = &ev[num_tx + loop];
85 if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
86 fqid = evq_info->dpci->queue[
87 DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
89 fqid = evq_info->dpci->queue[
90 DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
92 /* Prepare enqueue descriptor */
93 qbman_eq_desc_clear(&eqdesc[loop]);
94 qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
95 qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
96 qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
98 if (event->impl_opaque) {
99 uint8_t dqrr_index = event->impl_opaque - 1;
101 qbman_eq_desc_set_dca(&eqdesc[loop], 1,
103 DPAA2_PER_LCORE_DPIO->dqrr_size--;
104 DPAA2_PER_LCORE_DPIO->dqrr_held &=
108 memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
111 * todo - need to align with hw context data
114 struct rte_event *ev_temp = rte_malloc(NULL,
115 sizeof(struct rte_event), 0);
120 frames_to_send = loop;
121 PMD_DRV_LOG(ERR, "Unable to allocate memory");
124 rte_memcpy(ev_temp, event, sizeof(struct rte_event));
125 DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
126 DPAA2_SET_FD_LEN((&fd_arr[loop]),
127 sizeof(struct rte_event));
131 while (loop < frames_to_send) {
132 loop += qbman_swp_enqueue_multiple_desc(swp,
133 &eqdesc[loop], &fd_arr[loop],
134 frames_to_send - loop);
136 num_tx += frames_to_send;
137 nb_events -= frames_to_send;
144 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
146 return dpaa2_eventdev_enqueue_burst(port, ev, 1);
149 static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
151 struct epoll_event epoll_ev;
154 qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
155 QBMAN_SWP_INTERRUPT_DQRI);
158 ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
159 &epoll_ev, 1, timeout_ticks);
161 /* sometimes due to some spurious interrupts epoll_wait fails
162 * with errno EINTR. so here we are retrying epoll_wait in such
163 * case to avoid the problem.
165 if (errno == EINTR) {
166 PMD_DRV_LOG(DEBUG, "epoll_wait fails\n");
168 PMD_DRV_LOG(DEBUG, "Dequeue burst Failed\n");
174 static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
175 const struct qbman_fd *fd,
176 const struct qbman_result *dq,
177 struct dpaa2_queue *rxq,
178 struct rte_event *ev)
180 struct rte_event *ev_temp =
181 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
185 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
188 qbman_swp_dqrr_consume(swp, dq);
191 static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
192 const struct qbman_fd *fd,
193 const struct qbman_result *dq,
194 struct dpaa2_queue *rxq,
195 struct rte_event *ev)
197 struct rte_event *ev_temp =
198 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
199 uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
204 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
206 ev->impl_opaque = dqrr_index + 1;
207 DPAA2_PER_LCORE_DPIO->dqrr_size++;
208 DPAA2_PER_LCORE_DPIO->dqrr_held |= 1 << dqrr_index;
212 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
213 uint16_t nb_events, uint64_t timeout_ticks)
215 const struct qbman_result *dq;
216 struct qbman_swp *swp;
217 const struct qbman_fd *fd;
218 struct dpaa2_queue *rxq;
219 int num_pkts = 0, ret, i = 0;
223 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
224 ret = dpaa2_affine_qbman_swp();
226 PMD_DRV_LOG(ERR, "Failure in affining portal\n");
231 swp = DPAA2_PER_LCORE_PORTAL;
233 /* Check if there are atomic contexts to be released */
234 while (DPAA2_PER_LCORE_DPIO->dqrr_size) {
235 if (DPAA2_PER_LCORE_DPIO->dqrr_held & (1 << i)) {
236 dq = qbman_get_dqrr_from_idx(swp, i);
237 qbman_swp_dqrr_consume(swp, dq);
238 DPAA2_PER_LCORE_DPIO->dqrr_size--;
242 DPAA2_PER_LCORE_DPIO->dqrr_held = 0;
245 dq = qbman_swp_dqrr_next(swp);
247 if (!num_pkts && timeout_ticks) {
248 dpaa2_eventdev_dequeue_wait(timeout_ticks);
255 fd = qbman_result_DQ_fd(dq);
257 rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
259 rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
261 qbman_swp_dqrr_consume(swp, dq);
262 PMD_DRV_LOG(ERR, "Null Return VQ received\n");
267 } while (num_pkts < nb_events);
273 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
274 uint64_t timeout_ticks)
276 return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
280 dpaa2_eventdev_info_get(struct rte_eventdev *dev,
281 struct rte_event_dev_info *dev_info)
283 struct dpaa2_eventdev *priv = dev->data->dev_private;
285 PMD_DRV_FUNC_TRACE();
289 memset(dev_info, 0, sizeof(struct rte_event_dev_info));
290 dev_info->min_dequeue_timeout_ns =
291 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
292 dev_info->max_dequeue_timeout_ns =
293 DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
294 dev_info->dequeue_timeout_ns =
295 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
296 dev_info->max_event_queues = priv->max_event_queues;
297 dev_info->max_event_queue_flows =
298 DPAA2_EVENT_MAX_QUEUE_FLOWS;
299 dev_info->max_event_queue_priority_levels =
300 DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
301 dev_info->max_event_priority_levels =
302 DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
303 dev_info->max_event_ports = RTE_MAX_LCORE;
304 dev_info->max_event_port_dequeue_depth =
305 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
306 dev_info->max_event_port_enqueue_depth =
307 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
308 dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
309 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
310 RTE_EVENT_DEV_CAP_BURST_MODE;
314 dpaa2_eventdev_configure(const struct rte_eventdev *dev)
316 struct dpaa2_eventdev *priv = dev->data->dev_private;
317 struct rte_event_dev_config *conf = &dev->data->dev_conf;
319 PMD_DRV_FUNC_TRACE();
321 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
322 priv->nb_event_queues = conf->nb_event_queues;
323 priv->nb_event_ports = conf->nb_event_ports;
324 priv->nb_event_queue_flows = conf->nb_event_queue_flows;
325 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
326 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
327 priv->event_dev_cfg = conf->event_dev_cfg;
329 PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id);
334 dpaa2_eventdev_start(struct rte_eventdev *dev)
336 PMD_DRV_FUNC_TRACE();
344 dpaa2_eventdev_stop(struct rte_eventdev *dev)
346 PMD_DRV_FUNC_TRACE();
352 dpaa2_eventdev_close(struct rte_eventdev *dev)
354 PMD_DRV_FUNC_TRACE();
362 dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
363 struct rte_event_queue_conf *queue_conf)
365 PMD_DRV_FUNC_TRACE();
368 RTE_SET_USED(queue_id);
369 RTE_SET_USED(queue_conf);
371 queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
372 queue_conf->schedule_type = RTE_SCHED_TYPE_ATOMIC |
373 RTE_SCHED_TYPE_PARALLEL;
374 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
378 dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
380 PMD_DRV_FUNC_TRACE();
383 RTE_SET_USED(queue_id);
387 dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
388 const struct rte_event_queue_conf *queue_conf)
390 struct dpaa2_eventdev *priv = dev->data->dev_private;
391 struct evq_info_t *evq_info =
392 &priv->evq_info[queue_id];
394 PMD_DRV_FUNC_TRACE();
396 evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
402 dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
403 struct rte_event_port_conf *port_conf)
405 PMD_DRV_FUNC_TRACE();
408 RTE_SET_USED(port_id);
409 RTE_SET_USED(port_conf);
411 port_conf->new_event_threshold =
412 DPAA2_EVENT_MAX_NUM_EVENTS;
413 port_conf->dequeue_depth =
414 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
415 port_conf->enqueue_depth =
416 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
417 port_conf->disable_implicit_release = 0;
421 dpaa2_eventdev_port_release(void *port)
423 PMD_DRV_FUNC_TRACE();
429 dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
430 const struct rte_event_port_conf *port_conf)
432 PMD_DRV_FUNC_TRACE();
434 RTE_SET_USED(port_conf);
436 if (!dpaa2_io_portal[port_id].dpio_dev) {
437 dpaa2_io_portal[port_id].dpio_dev =
438 dpaa2_get_qbman_swp(port_id);
439 rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
440 if (!dpaa2_io_portal[port_id].dpio_dev)
444 dpaa2_io_portal[port_id].eventdev = dev;
445 dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
450 dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
451 uint8_t queues[], uint16_t nb_unlinks)
453 struct dpaa2_eventdev *priv = dev->data->dev_private;
454 struct dpaa2_io_portal_t *dpaa2_portal = port;
455 struct evq_info_t *evq_info;
458 PMD_DRV_FUNC_TRACE();
460 for (i = 0; i < nb_unlinks; i++) {
461 evq_info = &priv->evq_info[queues[i]];
462 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
463 evq_info->dpcon->channel_index, 0);
464 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
465 0, dpaa2_portal->dpio_dev->token,
466 evq_info->dpcon->dpcon_id);
470 return (int)nb_unlinks;
474 dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
475 const uint8_t queues[], const uint8_t priorities[],
478 struct dpaa2_eventdev *priv = dev->data->dev_private;
479 struct dpaa2_io_portal_t *dpaa2_portal = port;
480 struct evq_info_t *evq_info;
481 uint8_t channel_index;
484 PMD_DRV_FUNC_TRACE();
486 for (i = 0; i < nb_links; i++) {
487 evq_info = &priv->evq_info[queues[i]];
491 ret = dpio_add_static_dequeue_channel(
492 dpaa2_portal->dpio_dev->dpio,
493 CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
494 evq_info->dpcon->dpcon_id, &channel_index);
496 PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n",
501 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
503 evq_info->dpcon->channel_index = channel_index;
507 RTE_SET_USED(priorities);
509 return (int)nb_links;
511 for (n = 0; n < i; n++) {
512 evq_info = &priv->evq_info[queues[n]];
513 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
514 evq_info->dpcon->channel_index, 0);
515 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
516 0, dpaa2_portal->dpio_dev->token,
517 evq_info->dpcon->dpcon_id);
524 dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
525 uint64_t *timeout_ticks)
529 PMD_DRV_FUNC_TRACE();
532 *timeout_ticks = ns * scale;
538 dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
540 PMD_DRV_FUNC_TRACE();
547 dpaa2_eventdev_eth_caps_get(const struct rte_eventdev *dev,
548 const struct rte_eth_dev *eth_dev,
551 const char *ethdev_driver = eth_dev->device->driver->name;
553 PMD_DRV_FUNC_TRACE();
557 if (!strcmp(ethdev_driver, "net_dpaa2"))
558 *caps = RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP;
560 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
566 dpaa2_eventdev_eth_queue_add_all(const struct rte_eventdev *dev,
567 const struct rte_eth_dev *eth_dev,
568 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
570 struct dpaa2_eventdev *priv = dev->data->dev_private;
571 uint8_t ev_qid = queue_conf->ev.queue_id;
572 uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
575 PMD_DRV_FUNC_TRACE();
577 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
578 ret = dpaa2_eth_eventq_attach(eth_dev, i,
579 dpcon_id, queue_conf);
581 PMD_DRV_ERR("dpaa2_eth_eventq_attach failed: ret %d\n",
588 for (i = (i - 1); i >= 0 ; i--)
589 dpaa2_eth_eventq_detach(eth_dev, i);
595 dpaa2_eventdev_eth_queue_add(const struct rte_eventdev *dev,
596 const struct rte_eth_dev *eth_dev,
598 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
600 struct dpaa2_eventdev *priv = dev->data->dev_private;
601 uint8_t ev_qid = queue_conf->ev.queue_id;
602 uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
605 PMD_DRV_FUNC_TRACE();
607 if (rx_queue_id == -1)
608 return dpaa2_eventdev_eth_queue_add_all(dev,
609 eth_dev, queue_conf);
611 ret = dpaa2_eth_eventq_attach(eth_dev, rx_queue_id,
612 dpcon_id, queue_conf);
614 PMD_DRV_ERR("dpaa2_eth_eventq_attach failed: ret: %d\n", ret);
621 dpaa2_eventdev_eth_queue_del_all(const struct rte_eventdev *dev,
622 const struct rte_eth_dev *eth_dev)
626 PMD_DRV_FUNC_TRACE();
630 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
631 ret = dpaa2_eth_eventq_detach(eth_dev, i);
633 PMD_DRV_ERR("dpaa2_eth_eventq_detach failed: ret %d\n",
643 dpaa2_eventdev_eth_queue_del(const struct rte_eventdev *dev,
644 const struct rte_eth_dev *eth_dev,
649 PMD_DRV_FUNC_TRACE();
651 if (rx_queue_id == -1)
652 return dpaa2_eventdev_eth_queue_del_all(dev, eth_dev);
654 ret = dpaa2_eth_eventq_detach(eth_dev, rx_queue_id);
656 PMD_DRV_ERR("dpaa2_eth_eventq_detach failed: ret: %d\n", ret);
664 dpaa2_eventdev_eth_start(const struct rte_eventdev *dev,
665 const struct rte_eth_dev *eth_dev)
667 PMD_DRV_FUNC_TRACE();
670 RTE_SET_USED(eth_dev);
676 dpaa2_eventdev_eth_stop(const struct rte_eventdev *dev,
677 const struct rte_eth_dev *eth_dev)
679 PMD_DRV_FUNC_TRACE();
682 RTE_SET_USED(eth_dev);
687 static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
688 .dev_infos_get = dpaa2_eventdev_info_get,
689 .dev_configure = dpaa2_eventdev_configure,
690 .dev_start = dpaa2_eventdev_start,
691 .dev_stop = dpaa2_eventdev_stop,
692 .dev_close = dpaa2_eventdev_close,
693 .queue_def_conf = dpaa2_eventdev_queue_def_conf,
694 .queue_setup = dpaa2_eventdev_queue_setup,
695 .queue_release = dpaa2_eventdev_queue_release,
696 .port_def_conf = dpaa2_eventdev_port_def_conf,
697 .port_setup = dpaa2_eventdev_port_setup,
698 .port_release = dpaa2_eventdev_port_release,
699 .port_link = dpaa2_eventdev_port_link,
700 .port_unlink = dpaa2_eventdev_port_unlink,
701 .timeout_ticks = dpaa2_eventdev_timeout_ticks,
702 .dump = dpaa2_eventdev_dump,
703 .eth_rx_adapter_caps_get = dpaa2_eventdev_eth_caps_get,
704 .eth_rx_adapter_queue_add = dpaa2_eventdev_eth_queue_add,
705 .eth_rx_adapter_queue_del = dpaa2_eventdev_eth_queue_del,
706 .eth_rx_adapter_start = dpaa2_eventdev_eth_start,
707 .eth_rx_adapter_stop = dpaa2_eventdev_eth_stop,
711 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
712 struct dpaa2_dpcon_dev *dpcon_dev)
714 struct dpci_rx_queue_cfg rx_queue_cfg;
717 /*Do settings to get the frame on a DPCON object*/
718 rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
719 DPCI_QUEUE_OPT_USER_CTX;
720 rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
721 rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
722 rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
724 dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
725 dpaa2_eventdev_process_parallel;
726 dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
727 dpaa2_eventdev_process_atomic;
729 for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
730 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
731 ret = dpci_set_rx_queue(&dpci_dev->dpci,
737 "set_rx_q failed with err code: %d", ret);
745 dpaa2_eventdev_create(const char *name)
747 struct rte_eventdev *eventdev;
748 struct dpaa2_eventdev *priv;
749 struct dpaa2_dpcon_dev *dpcon_dev = NULL;
750 struct dpaa2_dpci_dev *dpci_dev = NULL;
753 eventdev = rte_event_pmd_vdev_init(name,
754 sizeof(struct dpaa2_eventdev),
756 if (eventdev == NULL) {
757 PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
761 eventdev->dev_ops = &dpaa2_eventdev_ops;
762 eventdev->enqueue = dpaa2_eventdev_enqueue;
763 eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
764 eventdev->enqueue_new_burst = dpaa2_eventdev_enqueue_burst;
765 eventdev->enqueue_forward_burst = dpaa2_eventdev_enqueue_burst;
766 eventdev->dequeue = dpaa2_eventdev_dequeue;
767 eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
769 /* For secondary processes, the primary has done all the work */
770 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
773 priv = eventdev->data->dev_private;
774 priv->max_event_queues = 0;
777 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
780 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
782 dpci_dev = rte_dpaa2_alloc_dpci_dev();
784 rte_dpaa2_free_dpcon_dev(dpcon_dev);
787 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
789 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
792 "dpci setup failed with err code: %d", ret);
795 priv->max_event_queues++;
796 } while (dpcon_dev && dpci_dev);
804 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
808 name = rte_vdev_device_name(vdev);
809 PMD_DRV_LOG(INFO, "Initializing %s", name);
810 return dpaa2_eventdev_create(name);
814 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
818 name = rte_vdev_device_name(vdev);
819 PMD_DRV_LOG(INFO, "Closing %s", name);
821 return rte_event_pmd_vdev_uninit(name);
824 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
825 .probe = dpaa2_eventdev_probe,
826 .remove = dpaa2_eventdev_remove
829 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);