1 /* SPDX-License-Identifier: BSD-3-Clause
13 #include <sys/epoll.h>
15 #include <rte_atomic.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_debug.h>
21 #include <rte_fslmc.h>
22 #include <rte_lcore.h>
24 #include <rte_malloc.h>
25 #include <rte_memcpy.h>
26 #include <rte_memory.h>
28 #include <rte_bus_vdev.h>
29 #include <rte_ethdev.h>
30 #include <rte_event_eth_rx_adapter.h>
32 #include <fslmc_vfio.h>
33 #include <dpaa2_hw_pvt.h>
34 #include <dpaa2_hw_mempool.h>
35 #include <dpaa2_hw_dpio.h>
36 #include <dpaa2_ethdev.h>
37 #include "dpaa2_eventdev.h"
38 #include "dpaa2_eventdev_logs.h"
39 #include <portal/dpaa2_hw_pvt.h>
40 #include <mc/fsl_dpci.h>
43 * Evendev = SoC Instance
44 * Eventport = DPIO Instance
45 * Eventqueue = DPCON Instance
46 * 1 Eventdev can have N Eventqueue
47 * Soft Event Flow is DPCI Instance
50 /* Dynamic logging identified for mempool */
51 int dpaa2_logtype_event;
54 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
57 struct rte_eventdev *ev_dev =
58 ((struct dpaa2_io_portal_t *)port)->eventdev;
59 struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
60 uint32_t queue_id = ev[0].queue_id;
61 struct evq_info_t *evq_info = &priv->evq_info[queue_id];
63 struct qbman_swp *swp;
64 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
65 uint32_t loop, frames_to_send;
66 struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
72 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
73 ret = dpaa2_affine_qbman_swp();
75 DPAA2_EVENTDEV_ERR("Failure in affining portal\n");
80 swp = DPAA2_PER_LCORE_PORTAL;
83 frames_to_send = (nb_events >> 3) ?
84 MAX_TX_RING_SLOTS : nb_events;
86 for (loop = 0; loop < frames_to_send; loop++) {
87 const struct rte_event *event = &ev[num_tx + loop];
89 if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
90 fqid = evq_info->dpci->queue[
91 DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
93 fqid = evq_info->dpci->queue[
94 DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
96 /* Prepare enqueue descriptor */
97 qbman_eq_desc_clear(&eqdesc[loop]);
98 qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
99 qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
100 qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
102 if (event->mbuf->seqn) {
103 uint8_t dqrr_index = event->mbuf->seqn - 1;
105 qbman_eq_desc_set_dca(&eqdesc[loop], 1,
107 DPAA2_PER_LCORE_DQRR_SIZE--;
108 DPAA2_PER_LCORE_DQRR_HELD &=
112 memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
115 * todo - need to align with hw context data
118 struct rte_event *ev_temp = rte_malloc(NULL,
119 sizeof(struct rte_event), 0);
124 frames_to_send = loop;
125 DPAA2_EVENTDEV_ERR("Unable to allocate memory");
128 rte_memcpy(ev_temp, event, sizeof(struct rte_event));
129 DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
130 DPAA2_SET_FD_LEN((&fd_arr[loop]),
131 sizeof(struct rte_event));
135 while (loop < frames_to_send) {
136 loop += qbman_swp_enqueue_multiple_desc(swp,
137 &eqdesc[loop], &fd_arr[loop],
138 frames_to_send - loop);
140 num_tx += frames_to_send;
141 nb_events -= frames_to_send;
148 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
150 return dpaa2_eventdev_enqueue_burst(port, ev, 1);
153 static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
155 struct epoll_event epoll_ev;
158 qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
159 QBMAN_SWP_INTERRUPT_DQRI);
162 ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
163 &epoll_ev, 1, timeout_ticks);
165 /* sometimes due to some spurious interrupts epoll_wait fails
166 * with errno EINTR. so here we are retrying epoll_wait in such
167 * case to avoid the problem.
169 if (errno == EINTR) {
170 DPAA2_EVENTDEV_DEBUG("epoll_wait fails\n");
172 DPAA2_EVENTDEV_DEBUG("Dequeue burst Failed\n");
178 static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
179 const struct qbman_fd *fd,
180 const struct qbman_result *dq,
181 struct dpaa2_queue *rxq,
182 struct rte_event *ev)
184 struct rte_event *ev_temp =
185 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
189 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
192 qbman_swp_dqrr_consume(swp, dq);
195 static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
196 const struct qbman_fd *fd,
197 const struct qbman_result *dq,
198 struct dpaa2_queue *rxq,
199 struct rte_event *ev)
201 struct rte_event *ev_temp =
202 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
203 uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
208 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
210 ev->mbuf->seqn = dqrr_index + 1;
211 DPAA2_PER_LCORE_DQRR_SIZE++;
212 DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
216 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
217 uint16_t nb_events, uint64_t timeout_ticks)
219 const struct qbman_result *dq;
220 struct qbman_swp *swp;
221 const struct qbman_fd *fd;
222 struct dpaa2_queue *rxq;
223 int num_pkts = 0, ret, i = 0;
227 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
228 ret = dpaa2_affine_qbman_swp();
230 DPAA2_EVENTDEV_ERR("Failure in affining portal\n");
234 swp = DPAA2_PER_LCORE_PORTAL;
236 /* Check if there are atomic contexts to be released */
237 while (DPAA2_PER_LCORE_DQRR_SIZE) {
238 if (DPAA2_PER_LCORE_DQRR_HELD & (1 << i)) {
239 qbman_swp_dqrr_idx_consume(swp, i);
240 DPAA2_PER_LCORE_DQRR_SIZE--;
241 DPAA2_PER_LCORE_DQRR_MBUF(i)->seqn =
242 DPAA2_INVALID_MBUF_SEQN;
246 DPAA2_PER_LCORE_DQRR_HELD = 0;
249 dq = qbman_swp_dqrr_next(swp);
251 if (!num_pkts && timeout_ticks) {
252 dpaa2_eventdev_dequeue_wait(timeout_ticks);
259 fd = qbman_result_DQ_fd(dq);
261 rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
263 rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
265 qbman_swp_dqrr_consume(swp, dq);
266 DPAA2_EVENTDEV_ERR("Null Return VQ received\n");
271 } while (num_pkts < nb_events);
277 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
278 uint64_t timeout_ticks)
280 return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
284 dpaa2_eventdev_info_get(struct rte_eventdev *dev,
285 struct rte_event_dev_info *dev_info)
287 struct dpaa2_eventdev *priv = dev->data->dev_private;
289 EVENTDEV_INIT_FUNC_TRACE();
293 memset(dev_info, 0, sizeof(struct rte_event_dev_info));
294 dev_info->min_dequeue_timeout_ns =
295 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
296 dev_info->max_dequeue_timeout_ns =
297 DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
298 dev_info->dequeue_timeout_ns =
299 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
300 dev_info->max_event_queues = priv->max_event_queues;
301 dev_info->max_event_queue_flows =
302 DPAA2_EVENT_MAX_QUEUE_FLOWS;
303 dev_info->max_event_queue_priority_levels =
304 DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
305 dev_info->max_event_priority_levels =
306 DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
307 dev_info->max_event_ports = RTE_MAX_LCORE;
308 dev_info->max_event_port_dequeue_depth =
309 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
310 dev_info->max_event_port_enqueue_depth =
311 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
312 dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
313 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
314 RTE_EVENT_DEV_CAP_BURST_MODE|
315 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
316 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
317 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
322 dpaa2_eventdev_configure(const struct rte_eventdev *dev)
324 struct dpaa2_eventdev *priv = dev->data->dev_private;
325 struct rte_event_dev_config *conf = &dev->data->dev_conf;
327 EVENTDEV_INIT_FUNC_TRACE();
329 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
330 priv->nb_event_queues = conf->nb_event_queues;
331 priv->nb_event_ports = conf->nb_event_ports;
332 priv->nb_event_queue_flows = conf->nb_event_queue_flows;
333 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
334 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
335 priv->event_dev_cfg = conf->event_dev_cfg;
337 DPAA2_EVENTDEV_DEBUG("Configured eventdev devid=%d",
343 dpaa2_eventdev_start(struct rte_eventdev *dev)
345 EVENTDEV_INIT_FUNC_TRACE();
353 dpaa2_eventdev_stop(struct rte_eventdev *dev)
355 EVENTDEV_INIT_FUNC_TRACE();
361 dpaa2_eventdev_close(struct rte_eventdev *dev)
363 EVENTDEV_INIT_FUNC_TRACE();
371 dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
372 struct rte_event_queue_conf *queue_conf)
374 EVENTDEV_INIT_FUNC_TRACE();
377 RTE_SET_USED(queue_id);
378 RTE_SET_USED(queue_conf);
380 queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
381 queue_conf->schedule_type = RTE_SCHED_TYPE_ATOMIC |
382 RTE_SCHED_TYPE_PARALLEL;
383 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
387 dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
389 EVENTDEV_INIT_FUNC_TRACE();
392 RTE_SET_USED(queue_id);
396 dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
397 const struct rte_event_queue_conf *queue_conf)
399 struct dpaa2_eventdev *priv = dev->data->dev_private;
400 struct evq_info_t *evq_info =
401 &priv->evq_info[queue_id];
403 EVENTDEV_INIT_FUNC_TRACE();
405 evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
411 dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
412 struct rte_event_port_conf *port_conf)
414 EVENTDEV_INIT_FUNC_TRACE();
417 RTE_SET_USED(port_id);
418 RTE_SET_USED(port_conf);
420 port_conf->new_event_threshold =
421 DPAA2_EVENT_MAX_NUM_EVENTS;
422 port_conf->dequeue_depth =
423 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
424 port_conf->enqueue_depth =
425 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
426 port_conf->disable_implicit_release = 0;
430 dpaa2_eventdev_port_release(void *port)
432 EVENTDEV_INIT_FUNC_TRACE();
438 dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
439 const struct rte_event_port_conf *port_conf)
441 EVENTDEV_INIT_FUNC_TRACE();
443 RTE_SET_USED(port_conf);
445 if (!dpaa2_io_portal[port_id].dpio_dev) {
446 dpaa2_io_portal[port_id].dpio_dev =
447 dpaa2_get_qbman_swp(port_id);
448 rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
449 if (!dpaa2_io_portal[port_id].dpio_dev)
453 dpaa2_io_portal[port_id].eventdev = dev;
454 dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
459 dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
460 uint8_t queues[], uint16_t nb_unlinks)
462 struct dpaa2_eventdev *priv = dev->data->dev_private;
463 struct dpaa2_io_portal_t *dpaa2_portal = port;
464 struct evq_info_t *evq_info;
467 EVENTDEV_INIT_FUNC_TRACE();
469 for (i = 0; i < nb_unlinks; i++) {
470 evq_info = &priv->evq_info[queues[i]];
471 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
472 evq_info->dpcon->channel_index, 0);
473 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
474 0, dpaa2_portal->dpio_dev->token,
475 evq_info->dpcon->dpcon_id);
479 return (int)nb_unlinks;
483 dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
484 const uint8_t queues[], const uint8_t priorities[],
487 struct dpaa2_eventdev *priv = dev->data->dev_private;
488 struct dpaa2_io_portal_t *dpaa2_portal = port;
489 struct evq_info_t *evq_info;
490 uint8_t channel_index;
493 EVENTDEV_INIT_FUNC_TRACE();
495 for (i = 0; i < nb_links; i++) {
496 evq_info = &priv->evq_info[queues[i]];
500 ret = dpio_add_static_dequeue_channel(
501 dpaa2_portal->dpio_dev->dpio,
502 CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
503 evq_info->dpcon->dpcon_id, &channel_index);
505 DPAA2_EVENTDEV_ERR("Static dequeue cfg failed with ret: %d\n",
510 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
512 evq_info->dpcon->channel_index = channel_index;
516 RTE_SET_USED(priorities);
518 return (int)nb_links;
520 for (n = 0; n < i; n++) {
521 evq_info = &priv->evq_info[queues[n]];
522 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
523 evq_info->dpcon->channel_index, 0);
524 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
525 0, dpaa2_portal->dpio_dev->token,
526 evq_info->dpcon->dpcon_id);
533 dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
534 uint64_t *timeout_ticks)
538 EVENTDEV_INIT_FUNC_TRACE();
541 *timeout_ticks = ns * scale;
547 dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
549 EVENTDEV_INIT_FUNC_TRACE();
556 dpaa2_eventdev_eth_caps_get(const struct rte_eventdev *dev,
557 const struct rte_eth_dev *eth_dev,
560 const char *ethdev_driver = eth_dev->device->driver->name;
562 EVENTDEV_INIT_FUNC_TRACE();
566 if (!strcmp(ethdev_driver, "net_dpaa2"))
567 *caps = RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP;
569 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
575 dpaa2_eventdev_eth_queue_add_all(const struct rte_eventdev *dev,
576 const struct rte_eth_dev *eth_dev,
577 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
579 struct dpaa2_eventdev *priv = dev->data->dev_private;
580 uint8_t ev_qid = queue_conf->ev.queue_id;
581 uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
584 EVENTDEV_INIT_FUNC_TRACE();
586 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
587 ret = dpaa2_eth_eventq_attach(eth_dev, i,
588 dpcon_id, queue_conf);
590 DPAA2_EVENTDEV_ERR("dpaa2_eth_eventq_attach failed: ret %d\n",
597 for (i = (i - 1); i >= 0 ; i--)
598 dpaa2_eth_eventq_detach(eth_dev, i);
604 dpaa2_eventdev_eth_queue_add(const struct rte_eventdev *dev,
605 const struct rte_eth_dev *eth_dev,
607 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
609 struct dpaa2_eventdev *priv = dev->data->dev_private;
610 uint8_t ev_qid = queue_conf->ev.queue_id;
611 uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
614 EVENTDEV_INIT_FUNC_TRACE();
616 if (rx_queue_id == -1)
617 return dpaa2_eventdev_eth_queue_add_all(dev,
618 eth_dev, queue_conf);
620 ret = dpaa2_eth_eventq_attach(eth_dev, rx_queue_id,
621 dpcon_id, queue_conf);
623 DPAA2_EVENTDEV_ERR("dpaa2_eth_eventq_attach failed: ret: %d\n", ret);
630 dpaa2_eventdev_eth_queue_del_all(const struct rte_eventdev *dev,
631 const struct rte_eth_dev *eth_dev)
635 EVENTDEV_INIT_FUNC_TRACE();
639 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
640 ret = dpaa2_eth_eventq_detach(eth_dev, i);
642 DPAA2_EVENTDEV_ERR("dpaa2_eth_eventq_detach failed: ret %d\n",
652 dpaa2_eventdev_eth_queue_del(const struct rte_eventdev *dev,
653 const struct rte_eth_dev *eth_dev,
658 EVENTDEV_INIT_FUNC_TRACE();
660 if (rx_queue_id == -1)
661 return dpaa2_eventdev_eth_queue_del_all(dev, eth_dev);
663 ret = dpaa2_eth_eventq_detach(eth_dev, rx_queue_id);
665 DPAA2_EVENTDEV_ERR("dpaa2_eth_eventq_detach failed: ret: %d\n", ret);
673 dpaa2_eventdev_eth_start(const struct rte_eventdev *dev,
674 const struct rte_eth_dev *eth_dev)
676 EVENTDEV_INIT_FUNC_TRACE();
679 RTE_SET_USED(eth_dev);
685 dpaa2_eventdev_eth_stop(const struct rte_eventdev *dev,
686 const struct rte_eth_dev *eth_dev)
688 EVENTDEV_INIT_FUNC_TRACE();
691 RTE_SET_USED(eth_dev);
696 static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
697 .dev_infos_get = dpaa2_eventdev_info_get,
698 .dev_configure = dpaa2_eventdev_configure,
699 .dev_start = dpaa2_eventdev_start,
700 .dev_stop = dpaa2_eventdev_stop,
701 .dev_close = dpaa2_eventdev_close,
702 .queue_def_conf = dpaa2_eventdev_queue_def_conf,
703 .queue_setup = dpaa2_eventdev_queue_setup,
704 .queue_release = dpaa2_eventdev_queue_release,
705 .port_def_conf = dpaa2_eventdev_port_def_conf,
706 .port_setup = dpaa2_eventdev_port_setup,
707 .port_release = dpaa2_eventdev_port_release,
708 .port_link = dpaa2_eventdev_port_link,
709 .port_unlink = dpaa2_eventdev_port_unlink,
710 .timeout_ticks = dpaa2_eventdev_timeout_ticks,
711 .dump = dpaa2_eventdev_dump,
712 .eth_rx_adapter_caps_get = dpaa2_eventdev_eth_caps_get,
713 .eth_rx_adapter_queue_add = dpaa2_eventdev_eth_queue_add,
714 .eth_rx_adapter_queue_del = dpaa2_eventdev_eth_queue_del,
715 .eth_rx_adapter_start = dpaa2_eventdev_eth_start,
716 .eth_rx_adapter_stop = dpaa2_eventdev_eth_stop,
720 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
721 struct dpaa2_dpcon_dev *dpcon_dev)
723 struct dpci_rx_queue_cfg rx_queue_cfg;
726 /*Do settings to get the frame on a DPCON object*/
727 rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
728 DPCI_QUEUE_OPT_USER_CTX;
729 rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
730 rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
731 rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
733 dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
734 dpaa2_eventdev_process_parallel;
735 dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
736 dpaa2_eventdev_process_atomic;
738 for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
739 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
740 ret = dpci_set_rx_queue(&dpci_dev->dpci,
746 "set_rx_q failed with err code: %d", ret);
754 dpaa2_eventdev_create(const char *name)
756 struct rte_eventdev *eventdev;
757 struct dpaa2_eventdev *priv;
758 struct dpaa2_dpcon_dev *dpcon_dev = NULL;
759 struct dpaa2_dpci_dev *dpci_dev = NULL;
762 eventdev = rte_event_pmd_vdev_init(name,
763 sizeof(struct dpaa2_eventdev),
765 if (eventdev == NULL) {
766 DPAA2_EVENTDEV_ERR("Failed to create eventdev vdev %s", name);
770 eventdev->dev_ops = &dpaa2_eventdev_ops;
771 eventdev->enqueue = dpaa2_eventdev_enqueue;
772 eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
773 eventdev->enqueue_new_burst = dpaa2_eventdev_enqueue_burst;
774 eventdev->enqueue_forward_burst = dpaa2_eventdev_enqueue_burst;
775 eventdev->dequeue = dpaa2_eventdev_dequeue;
776 eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
778 /* For secondary processes, the primary has done all the work */
779 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
782 priv = eventdev->data->dev_private;
783 priv->max_event_queues = 0;
786 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
789 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
791 dpci_dev = rte_dpaa2_alloc_dpci_dev();
793 rte_dpaa2_free_dpcon_dev(dpcon_dev);
796 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
798 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
801 "dpci setup failed with err code: %d", ret);
804 priv->max_event_queues++;
805 } while (dpcon_dev && dpci_dev);
813 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
817 name = rte_vdev_device_name(vdev);
818 DPAA2_EVENTDEV_INFO("Initializing %s", name);
819 return dpaa2_eventdev_create(name);
823 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
827 name = rte_vdev_device_name(vdev);
828 DPAA2_EVENTDEV_INFO("Closing %s", name);
830 return rte_event_pmd_vdev_uninit(name);
833 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
834 .probe = dpaa2_eventdev_probe,
835 .remove = dpaa2_eventdev_remove
838 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);