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39 #include <sys/epoll.h>
41 #include <rte_atomic.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_debug.h>
47 #include <rte_fslmc.h>
48 #include <rte_lcore.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
56 #include <rte_ethdev.h>
57 #include <rte_event_eth_rx_adapter.h>
59 #include <fslmc_vfio.h>
60 #include <dpaa2_hw_pvt.h>
61 #include <dpaa2_hw_mempool.h>
62 #include <dpaa2_hw_dpio.h>
63 #include <dpaa2_ethdev.h>
64 #include "dpaa2_eventdev.h"
65 #include <portal/dpaa2_hw_pvt.h>
66 #include <mc/fsl_dpci.h>
69 * Evendev = SoC Instance
70 * Eventport = DPIO Instance
71 * Eventqueue = DPCON Instance
72 * 1 Eventdev can have N Eventqueue
73 * Soft Event Flow is DPCI Instance
77 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
80 struct rte_eventdev *ev_dev =
81 ((struct dpaa2_io_portal_t *)port)->eventdev;
82 struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
83 uint32_t queue_id = ev[0].queue_id;
84 struct evq_info_t *evq_info = &priv->evq_info[queue_id];
86 struct qbman_swp *swp;
87 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
88 uint32_t loop, frames_to_send;
89 struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
95 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
96 ret = dpaa2_affine_qbman_swp();
98 PMD_DRV_LOG(ERR, "Failure in affining portal\n");
103 swp = DPAA2_PER_LCORE_PORTAL;
106 frames_to_send = (nb_events >> 3) ?
107 MAX_TX_RING_SLOTS : nb_events;
109 for (loop = 0; loop < frames_to_send; loop++) {
110 const struct rte_event *event = &ev[num_tx + loop];
112 if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
113 fqid = evq_info->dpci->queue[
114 DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
116 fqid = evq_info->dpci->queue[
117 DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
119 /* Prepare enqueue descriptor */
120 qbman_eq_desc_clear(&eqdesc[loop]);
121 qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
122 qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
123 qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
125 if (event->impl_opaque) {
126 uint8_t dqrr_index = event->impl_opaque - 1;
128 qbman_eq_desc_set_dca(&eqdesc[loop], 1,
130 DPAA2_PER_LCORE_DPIO->dqrr_size--;
131 DPAA2_PER_LCORE_DPIO->dqrr_held &=
135 memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
138 * todo - need to align with hw context data
141 struct rte_event *ev_temp = rte_malloc(NULL,
142 sizeof(struct rte_event), 0);
147 frames_to_send = loop;
148 PMD_DRV_LOG(ERR, "Unable to allocate memory");
151 rte_memcpy(ev_temp, event, sizeof(struct rte_event));
152 DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
153 DPAA2_SET_FD_LEN((&fd_arr[loop]),
154 sizeof(struct rte_event));
158 while (loop < frames_to_send) {
159 loop += qbman_swp_enqueue_multiple_desc(swp,
160 &eqdesc[loop], &fd_arr[loop],
161 frames_to_send - loop);
163 num_tx += frames_to_send;
164 nb_events -= frames_to_send;
171 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
173 return dpaa2_eventdev_enqueue_burst(port, ev, 1);
176 static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
178 struct epoll_event epoll_ev;
181 qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
182 QBMAN_SWP_INTERRUPT_DQRI);
185 ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
186 &epoll_ev, 1, timeout_ticks);
188 /* sometimes due to some spurious interrupts epoll_wait fails
189 * with errno EINTR. so here we are retrying epoll_wait in such
190 * case to avoid the problem.
192 if (errno == EINTR) {
193 PMD_DRV_LOG(DEBUG, "epoll_wait fails\n");
195 PMD_DRV_LOG(DEBUG, "Dequeue burst Failed\n");
201 static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
202 const struct qbman_fd *fd,
203 const struct qbman_result *dq,
204 struct dpaa2_queue *rxq,
205 struct rte_event *ev)
207 struct rte_event *ev_temp =
208 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
212 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
215 qbman_swp_dqrr_consume(swp, dq);
218 static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
219 const struct qbman_fd *fd,
220 const struct qbman_result *dq,
221 struct dpaa2_queue *rxq,
222 struct rte_event *ev)
224 struct rte_event *ev_temp =
225 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
226 uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
231 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
233 ev->impl_opaque = dqrr_index + 1;
234 DPAA2_PER_LCORE_DPIO->dqrr_size++;
235 DPAA2_PER_LCORE_DPIO->dqrr_held |= 1 << dqrr_index;
239 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
240 uint16_t nb_events, uint64_t timeout_ticks)
242 const struct qbman_result *dq;
243 struct qbman_swp *swp;
244 const struct qbman_fd *fd;
245 struct dpaa2_queue *rxq;
246 int num_pkts = 0, ret, i = 0;
250 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
251 ret = dpaa2_affine_qbman_swp();
253 PMD_DRV_LOG(ERR, "Failure in affining portal\n");
258 swp = DPAA2_PER_LCORE_PORTAL;
260 /* Check if there are atomic contexts to be released */
261 while (DPAA2_PER_LCORE_DPIO->dqrr_size) {
262 if (DPAA2_PER_LCORE_DPIO->dqrr_held & (1 << i)) {
263 dq = qbman_get_dqrr_from_idx(swp, i);
264 qbman_swp_dqrr_consume(swp, dq);
265 DPAA2_PER_LCORE_DPIO->dqrr_size--;
269 DPAA2_PER_LCORE_DPIO->dqrr_held = 0;
272 dq = qbman_swp_dqrr_next(swp);
274 if (!num_pkts && timeout_ticks) {
275 dpaa2_eventdev_dequeue_wait(timeout_ticks);
282 fd = qbman_result_DQ_fd(dq);
284 rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
286 rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
288 qbman_swp_dqrr_consume(swp, dq);
289 PMD_DRV_LOG(ERR, "Null Return VQ received\n");
294 } while (num_pkts < nb_events);
300 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
301 uint64_t timeout_ticks)
303 return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
307 dpaa2_eventdev_info_get(struct rte_eventdev *dev,
308 struct rte_event_dev_info *dev_info)
310 struct dpaa2_eventdev *priv = dev->data->dev_private;
312 PMD_DRV_FUNC_TRACE();
316 memset(dev_info, 0, sizeof(struct rte_event_dev_info));
317 dev_info->min_dequeue_timeout_ns =
318 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
319 dev_info->max_dequeue_timeout_ns =
320 DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
321 dev_info->dequeue_timeout_ns =
322 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
323 dev_info->max_event_queues = priv->max_event_queues;
324 dev_info->max_event_queue_flows =
325 DPAA2_EVENT_MAX_QUEUE_FLOWS;
326 dev_info->max_event_queue_priority_levels =
327 DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
328 dev_info->max_event_priority_levels =
329 DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
330 dev_info->max_event_ports = RTE_MAX_LCORE;
331 dev_info->max_event_port_dequeue_depth =
332 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
333 dev_info->max_event_port_enqueue_depth =
334 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
335 dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
336 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
337 RTE_EVENT_DEV_CAP_BURST_MODE;
341 dpaa2_eventdev_configure(const struct rte_eventdev *dev)
343 struct dpaa2_eventdev *priv = dev->data->dev_private;
344 struct rte_event_dev_config *conf = &dev->data->dev_conf;
346 PMD_DRV_FUNC_TRACE();
348 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
349 priv->nb_event_queues = conf->nb_event_queues;
350 priv->nb_event_ports = conf->nb_event_ports;
351 priv->nb_event_queue_flows = conf->nb_event_queue_flows;
352 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
353 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
354 priv->event_dev_cfg = conf->event_dev_cfg;
356 PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id);
361 dpaa2_eventdev_start(struct rte_eventdev *dev)
363 PMD_DRV_FUNC_TRACE();
371 dpaa2_eventdev_stop(struct rte_eventdev *dev)
373 PMD_DRV_FUNC_TRACE();
379 dpaa2_eventdev_close(struct rte_eventdev *dev)
381 PMD_DRV_FUNC_TRACE();
389 dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
390 struct rte_event_queue_conf *queue_conf)
392 PMD_DRV_FUNC_TRACE();
395 RTE_SET_USED(queue_id);
396 RTE_SET_USED(queue_conf);
398 queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
399 queue_conf->schedule_type = RTE_SCHED_TYPE_ATOMIC |
400 RTE_SCHED_TYPE_PARALLEL;
401 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
405 dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
407 PMD_DRV_FUNC_TRACE();
410 RTE_SET_USED(queue_id);
414 dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
415 const struct rte_event_queue_conf *queue_conf)
417 struct dpaa2_eventdev *priv = dev->data->dev_private;
418 struct evq_info_t *evq_info =
419 &priv->evq_info[queue_id];
421 PMD_DRV_FUNC_TRACE();
423 evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
429 dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
430 struct rte_event_port_conf *port_conf)
432 PMD_DRV_FUNC_TRACE();
435 RTE_SET_USED(port_id);
436 RTE_SET_USED(port_conf);
438 port_conf->new_event_threshold =
439 DPAA2_EVENT_MAX_NUM_EVENTS;
440 port_conf->dequeue_depth =
441 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
442 port_conf->enqueue_depth =
443 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
447 dpaa2_eventdev_port_release(void *port)
449 PMD_DRV_FUNC_TRACE();
455 dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
456 const struct rte_event_port_conf *port_conf)
458 PMD_DRV_FUNC_TRACE();
460 RTE_SET_USED(port_conf);
462 if (!dpaa2_io_portal[port_id].dpio_dev) {
463 dpaa2_io_portal[port_id].dpio_dev =
464 dpaa2_get_qbman_swp(port_id);
465 rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
466 if (!dpaa2_io_portal[port_id].dpio_dev)
470 dpaa2_io_portal[port_id].eventdev = dev;
471 dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
476 dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
477 uint8_t queues[], uint16_t nb_unlinks)
479 struct dpaa2_eventdev *priv = dev->data->dev_private;
480 struct dpaa2_io_portal_t *dpaa2_portal = port;
481 struct evq_info_t *evq_info;
484 PMD_DRV_FUNC_TRACE();
486 for (i = 0; i < nb_unlinks; i++) {
487 evq_info = &priv->evq_info[queues[i]];
488 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
489 evq_info->dpcon->channel_index, 0);
490 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
491 0, dpaa2_portal->dpio_dev->token,
492 evq_info->dpcon->dpcon_id);
496 return (int)nb_unlinks;
500 dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
501 const uint8_t queues[], const uint8_t priorities[],
504 struct dpaa2_eventdev *priv = dev->data->dev_private;
505 struct dpaa2_io_portal_t *dpaa2_portal = port;
506 struct evq_info_t *evq_info;
507 uint8_t channel_index;
510 PMD_DRV_FUNC_TRACE();
512 for (i = 0; i < nb_links; i++) {
513 evq_info = &priv->evq_info[queues[i]];
517 ret = dpio_add_static_dequeue_channel(
518 dpaa2_portal->dpio_dev->dpio,
519 CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
520 evq_info->dpcon->dpcon_id, &channel_index);
522 PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n",
527 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
529 evq_info->dpcon->channel_index = channel_index;
533 RTE_SET_USED(priorities);
535 return (int)nb_links;
537 for (n = 0; n < i; n++) {
538 evq_info = &priv->evq_info[queues[n]];
539 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
540 evq_info->dpcon->channel_index, 0);
541 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
542 0, dpaa2_portal->dpio_dev->token,
543 evq_info->dpcon->dpcon_id);
550 dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
551 uint64_t *timeout_ticks)
555 PMD_DRV_FUNC_TRACE();
558 *timeout_ticks = ns * scale;
564 dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
566 PMD_DRV_FUNC_TRACE();
573 dpaa2_eventdev_eth_caps_get(const struct rte_eventdev *dev,
574 const struct rte_eth_dev *eth_dev,
577 const char *ethdev_driver = eth_dev->device->driver->name;
579 PMD_DRV_FUNC_TRACE();
583 if (!strcmp(ethdev_driver, "net_dpaa2"))
584 *caps = RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP;
586 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
592 dpaa2_eventdev_eth_queue_add_all(const struct rte_eventdev *dev,
593 const struct rte_eth_dev *eth_dev,
594 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
596 struct dpaa2_eventdev *priv = dev->data->dev_private;
597 uint8_t ev_qid = queue_conf->ev.queue_id;
598 uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
601 PMD_DRV_FUNC_TRACE();
603 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
604 ret = dpaa2_eth_eventq_attach(eth_dev, i,
605 dpcon_id, queue_conf);
607 PMD_DRV_ERR("dpaa2_eth_eventq_attach failed: ret %d\n",
614 for (i = (i - 1); i >= 0 ; i--)
615 dpaa2_eth_eventq_detach(eth_dev, i);
621 dpaa2_eventdev_eth_queue_add(const struct rte_eventdev *dev,
622 const struct rte_eth_dev *eth_dev,
624 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
626 struct dpaa2_eventdev *priv = dev->data->dev_private;
627 uint8_t ev_qid = queue_conf->ev.queue_id;
628 uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
631 PMD_DRV_FUNC_TRACE();
633 if (rx_queue_id == -1)
634 return dpaa2_eventdev_eth_queue_add_all(dev,
635 eth_dev, queue_conf);
637 ret = dpaa2_eth_eventq_attach(eth_dev, rx_queue_id,
638 dpcon_id, queue_conf);
640 PMD_DRV_ERR("dpaa2_eth_eventq_attach failed: ret: %d\n", ret);
647 dpaa2_eventdev_eth_queue_del_all(const struct rte_eventdev *dev,
648 const struct rte_eth_dev *eth_dev)
652 PMD_DRV_FUNC_TRACE();
656 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
657 ret = dpaa2_eth_eventq_detach(eth_dev, i);
659 PMD_DRV_ERR("dpaa2_eth_eventq_detach failed: ret %d\n",
669 dpaa2_eventdev_eth_queue_del(const struct rte_eventdev *dev,
670 const struct rte_eth_dev *eth_dev,
675 PMD_DRV_FUNC_TRACE();
677 if (rx_queue_id == -1)
678 return dpaa2_eventdev_eth_queue_del_all(dev, eth_dev);
680 ret = dpaa2_eth_eventq_detach(eth_dev, rx_queue_id);
682 PMD_DRV_ERR("dpaa2_eth_eventq_detach failed: ret: %d\n", ret);
690 dpaa2_eventdev_eth_start(const struct rte_eventdev *dev,
691 const struct rte_eth_dev *eth_dev)
693 PMD_DRV_FUNC_TRACE();
696 RTE_SET_USED(eth_dev);
702 dpaa2_eventdev_eth_stop(const struct rte_eventdev *dev,
703 const struct rte_eth_dev *eth_dev)
705 PMD_DRV_FUNC_TRACE();
708 RTE_SET_USED(eth_dev);
713 static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
714 .dev_infos_get = dpaa2_eventdev_info_get,
715 .dev_configure = dpaa2_eventdev_configure,
716 .dev_start = dpaa2_eventdev_start,
717 .dev_stop = dpaa2_eventdev_stop,
718 .dev_close = dpaa2_eventdev_close,
719 .queue_def_conf = dpaa2_eventdev_queue_def_conf,
720 .queue_setup = dpaa2_eventdev_queue_setup,
721 .queue_release = dpaa2_eventdev_queue_release,
722 .port_def_conf = dpaa2_eventdev_port_def_conf,
723 .port_setup = dpaa2_eventdev_port_setup,
724 .port_release = dpaa2_eventdev_port_release,
725 .port_link = dpaa2_eventdev_port_link,
726 .port_unlink = dpaa2_eventdev_port_unlink,
727 .timeout_ticks = dpaa2_eventdev_timeout_ticks,
728 .dump = dpaa2_eventdev_dump,
729 .eth_rx_adapter_caps_get = dpaa2_eventdev_eth_caps_get,
730 .eth_rx_adapter_queue_add = dpaa2_eventdev_eth_queue_add,
731 .eth_rx_adapter_queue_del = dpaa2_eventdev_eth_queue_del,
732 .eth_rx_adapter_start = dpaa2_eventdev_eth_start,
733 .eth_rx_adapter_stop = dpaa2_eventdev_eth_stop,
737 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
738 struct dpaa2_dpcon_dev *dpcon_dev)
740 struct dpci_rx_queue_cfg rx_queue_cfg;
743 /*Do settings to get the frame on a DPCON object*/
744 rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
745 DPCI_QUEUE_OPT_USER_CTX;
746 rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
747 rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
748 rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
750 dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
751 dpaa2_eventdev_process_parallel;
752 dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
753 dpaa2_eventdev_process_atomic;
755 for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
756 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
757 ret = dpci_set_rx_queue(&dpci_dev->dpci,
763 "set_rx_q failed with err code: %d", ret);
771 dpaa2_eventdev_create(const char *name)
773 struct rte_eventdev *eventdev;
774 struct dpaa2_eventdev *priv;
775 struct dpaa2_dpcon_dev *dpcon_dev = NULL;
776 struct dpaa2_dpci_dev *dpci_dev = NULL;
779 eventdev = rte_event_pmd_vdev_init(name,
780 sizeof(struct dpaa2_eventdev),
782 if (eventdev == NULL) {
783 PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
787 eventdev->dev_ops = &dpaa2_eventdev_ops;
788 eventdev->schedule = NULL;
789 eventdev->enqueue = dpaa2_eventdev_enqueue;
790 eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
791 eventdev->enqueue_new_burst = dpaa2_eventdev_enqueue_burst;
792 eventdev->enqueue_forward_burst = dpaa2_eventdev_enqueue_burst;
793 eventdev->dequeue = dpaa2_eventdev_dequeue;
794 eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
796 /* For secondary processes, the primary has done all the work */
797 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
800 priv = eventdev->data->dev_private;
801 priv->max_event_queues = 0;
804 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
807 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
809 dpci_dev = rte_dpaa2_alloc_dpci_dev();
811 rte_dpaa2_free_dpcon_dev(dpcon_dev);
814 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
816 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
819 "dpci setup failed with err code: %d", ret);
822 priv->max_event_queues++;
823 } while (dpcon_dev && dpci_dev);
831 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
835 name = rte_vdev_device_name(vdev);
836 PMD_DRV_LOG(INFO, "Initializing %s", name);
837 return dpaa2_eventdev_create(name);
841 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
845 name = rte_vdev_device_name(vdev);
846 PMD_DRV_LOG(INFO, "Closing %s", name);
848 return rte_event_pmd_vdev_uninit(name);
851 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
852 .probe = dpaa2_eventdev_probe,
853 .remove = dpaa2_eventdev_remove
856 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);