4 * Copyright (C) Cavium networks Ltd. 2017.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <rte_common.h>
34 #include <rte_debug.h>
37 #include <rte_lcore.h>
39 #include <rte_malloc.h>
40 #include <rte_memory.h>
41 #include <rte_memzone.h>
44 #include "ssovf_evdev.h"
46 /* SSOPF Mailbox messages */
48 struct ssovf_mbox_dev_info {
49 uint64_t min_deq_timeout_ns;
50 uint64_t max_deq_timeout_ns;
51 uint32_t max_num_events;
55 ssovf_mbox_dev_info(struct ssovf_mbox_dev_info *info)
57 struct octeontx_mbox_hdr hdr = {0};
58 uint16_t len = sizeof(struct ssovf_mbox_dev_info);
60 hdr.coproc = SSO_COPROC;
61 hdr.msg = SSO_GET_DEV_INFO;
65 return octeontx_ssovf_mbox_send(&hdr, NULL, 0, info, len);
68 struct ssovf_mbox_getwork_wait {
73 ssovf_mbox_getwork_tmo_set(uint32_t timeout_ns)
75 struct octeontx_mbox_hdr hdr = {0};
76 struct ssovf_mbox_getwork_wait tmo_set;
77 uint16_t len = sizeof(struct ssovf_mbox_getwork_wait);
80 hdr.coproc = SSO_COPROC;
81 hdr.msg = SSO_SET_GETWORK_WAIT;
84 tmo_set.wait_ns = timeout_ns;
85 ret = octeontx_ssovf_mbox_send(&hdr, &tmo_set, len, NULL, 0);
87 ssovf_log_err("Failed to set getwork timeout(%d)", ret);
92 struct ssovf_mbox_grp_pri {
93 uint8_t wgt_left; /* Read only */
100 ssovf_mbox_priority_set(uint8_t queue, uint8_t prio)
102 struct octeontx_mbox_hdr hdr = {0};
103 struct ssovf_mbox_grp_pri grp;
104 uint16_t len = sizeof(struct ssovf_mbox_grp_pri);
107 hdr.coproc = SSO_COPROC;
108 hdr.msg = SSO_GRP_SET_PRIORITY;
113 grp.priority = prio / 32; /* Normalize to 0 to 7 */
115 ret = octeontx_ssovf_mbox_send(&hdr, &grp, len, NULL, 0);
117 ssovf_log_err("Failed to set grp=%d prio=%d", queue, prio);
122 struct ssovf_mbox_convert_ns_getworks_iter {
124 uint32_t getwork_iter;/* Get_work iterations for the given wait_ns */
128 ssovf_mbox_timeout_ticks(uint64_t ns, uint64_t *tmo_ticks)
130 struct octeontx_mbox_hdr hdr = {0};
131 struct ssovf_mbox_convert_ns_getworks_iter ns2iter;
132 uint16_t len = sizeof(ns2iter);
135 hdr.coproc = SSO_COPROC;
136 hdr.msg = SSO_CONVERT_NS_GETWORK_ITER;
139 memset(&ns2iter, 0, len);
140 ns2iter.wait_ns = ns;
141 ret = octeontx_ssovf_mbox_send(&hdr, &ns2iter, len, &ns2iter, len);
142 if (ret < 0 || (ret != len)) {
143 ssovf_log_err("Failed to get tmo ticks ns=%"PRId64"", ns);
147 *tmo_ticks = ns2iter.getwork_iter;
152 ssovf_fastpath_fns_set(struct rte_eventdev *dev)
154 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
156 dev->schedule = NULL;
157 dev->enqueue = ssows_enq;
158 dev->enqueue_burst = ssows_enq_burst;
159 dev->dequeue = ssows_deq;
160 dev->dequeue_burst = ssows_deq_burst;
162 if (edev->is_timeout_deq) {
163 dev->dequeue = ssows_deq_timeout;
164 dev->dequeue_burst = ssows_deq_timeout_burst;
169 ssovf_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *dev_info)
171 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
173 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD);
174 dev_info->min_dequeue_timeout_ns = edev->min_deq_timeout_ns;
175 dev_info->max_dequeue_timeout_ns = edev->max_deq_timeout_ns;
176 dev_info->max_event_queues = edev->max_event_queues;
177 dev_info->max_event_queue_flows = (1ULL << 20);
178 dev_info->max_event_queue_priority_levels = 8;
179 dev_info->max_event_priority_levels = 1;
180 dev_info->max_event_ports = edev->max_event_ports;
181 dev_info->max_event_port_dequeue_depth = 1;
182 dev_info->max_event_port_enqueue_depth = 1;
183 dev_info->max_num_events = edev->max_num_events;
184 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
185 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
186 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES;
190 ssovf_configure(const struct rte_eventdev *dev)
192 struct rte_event_dev_config *conf = &dev->data->dev_conf;
193 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
197 deq_tmo_ns = conf->dequeue_timeout_ns;
199 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) {
200 edev->is_timeout_deq = 1;
201 deq_tmo_ns = edev->min_deq_timeout_ns;
203 edev->nb_event_queues = conf->nb_event_queues;
204 edev->nb_event_ports = conf->nb_event_ports;
206 return ssovf_mbox_getwork_tmo_set(deq_tmo_ns);
210 ssovf_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
211 struct rte_event_queue_conf *queue_conf)
214 RTE_SET_USED(queue_id);
216 queue_conf->nb_atomic_flows = (1ULL << 20);
217 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
218 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
219 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
223 ssovf_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
226 RTE_SET_USED(queue_id);
230 ssovf_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
231 const struct rte_event_queue_conf *queue_conf)
234 ssovf_func_trace("queue=%d prio=%d", queue_id, queue_conf->priority);
236 return ssovf_mbox_priority_set(queue_id, queue_conf->priority);
240 ssovf_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
241 struct rte_event_port_conf *port_conf)
243 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
245 RTE_SET_USED(port_id);
246 port_conf->new_event_threshold = edev->max_num_events;
247 port_conf->dequeue_depth = 1;
248 port_conf->enqueue_depth = 1;
252 ssovf_port_release(void *port)
258 ssovf_port_setup(struct rte_eventdev *dev, uint8_t port_id,
259 const struct rte_event_port_conf *port_conf)
264 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
266 ssovf_func_trace("port=%d", port_id);
267 RTE_SET_USED(port_conf);
269 /* Free memory prior to re-allocation if needed */
270 if (dev->data->ports[port_id] != NULL) {
271 ssovf_port_release(dev->data->ports[port_id]);
272 dev->data->ports[port_id] = NULL;
275 /* Allocate event port memory */
276 ws = rte_zmalloc_socket("eventdev ssows",
277 sizeof(struct ssows), RTE_CACHE_LINE_SIZE,
278 dev->data->socket_id);
280 ssovf_log_err("Failed to alloc memory for port=%d", port_id);
284 ws->base = octeontx_ssovf_bar(OCTEONTX_SSO_HWS, port_id, 0);
285 if (ws->base == NULL) {
287 ssovf_log_err("Failed to get hws base addr port=%d", port_id);
291 reg_off = SSOW_VHWS_OP_GET_WORK0;
292 reg_off |= 1 << 4; /* Index_ggrp_mask (Use maskset zero) */
293 reg_off |= 1 << 16; /* Wait */
294 ws->getwork = ws->base + reg_off;
297 for (q = 0; q < edev->nb_event_queues; q++) {
298 ws->grps[q] = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, q, 2);
299 if (ws->grps[q] == NULL) {
301 ssovf_log_err("Failed to get grp%d base addr", q);
306 dev->data->ports[port_id] = ws;
307 ssovf_log_dbg("port=%d ws=%p", port_id, ws);
312 ssovf_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[],
313 const uint8_t priorities[], uint16_t nb_links)
317 struct ssows *ws = port;
319 ssovf_func_trace("port=%d nb_links=%d", ws->port, nb_links);
321 RTE_SET_USED(priorities);
323 for (link = 0; link < nb_links; link++) {
325 val |= (1ULL << 24); /* Set membership */
326 ssovf_write64(val, ws->base + SSOW_VHWS_GRPMSK_CHGX(0));
328 return (int)nb_links;
332 ssovf_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[],
337 struct ssows *ws = port;
339 ssovf_func_trace("port=%d nb_links=%d", ws->port, nb_unlinks);
342 for (unlink = 0; unlink < nb_unlinks; unlink++) {
343 val = queues[unlink];
344 val &= ~(1ULL << 24); /* Clear membership */
345 ssovf_write64(val, ws->base + SSOW_VHWS_GRPMSK_CHGX(0));
347 return (int)nb_unlinks;
351 ssovf_timeout_ticks(struct rte_eventdev *dev, uint64_t ns, uint64_t *tmo_ticks)
355 return ssovf_mbox_timeout_ticks(ns, tmo_ticks);
359 ssows_dump(struct ssows *ws, FILE *f)
361 uint8_t *base = ws->base;
364 fprintf(f, "\t---------------port%d---------------\n", ws->port);
365 val = ssovf_read64(base + SSOW_VHWS_TAG);
366 fprintf(f, "\ttag=0x%x tt=%d head=%d tail=%d grp=%d index=%d tail=%d\n",
367 (uint32_t)(val & 0xffffffff), (int)(val >> 32) & 0x3,
368 (int)(val >> 34) & 0x1, (int)(val >> 35) & 0x1,
369 (int)(val >> 36) & 0x3ff, (int)(val >> 48) & 0x3ff,
370 (int)(val >> 63) & 0x1);
372 val = ssovf_read64(base + SSOW_VHWS_WQP);
373 fprintf(f, "\twqp=0x%"PRIx64"\n", val);
375 val = ssovf_read64(base + SSOW_VHWS_LINKS);
376 fprintf(f, "\tindex=%d valid=%d revlink=%d tail=%d head=%d grp=%d\n",
377 (int)(val & 0x3ff), (int)(val >> 10) & 0x1,
378 (int)(val >> 11) & 0x3ff, (int)(val >> 26) & 0x1,
379 (int)(val >> 27) & 0x1, (int)(val >> 28) & 0x3ff);
381 val = ssovf_read64(base + SSOW_VHWS_PENDTAG);
382 fprintf(f, "\tptag=0x%x ptt=%d pgwi=%d pdesc=%d pgw=%d pgww=%d ps=%d\n",
383 (uint32_t)(val & 0xffffffff), (int)(val >> 32) & 0x3,
384 (int)(val >> 56) & 0x1, (int)(val >> 58) & 0x1,
385 (int)(val >> 61) & 0x1, (int)(val >> 62) & 0x1,
386 (int)(val >> 63) & 0x1);
388 val = ssovf_read64(base + SSOW_VHWS_PENDWQP);
389 fprintf(f, "\tpwqp=0x%"PRIx64"\n", val);
393 ssovf_dump(struct rte_eventdev *dev, FILE *f)
395 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
398 /* Dump SSOWVF debug registers */
399 for (port = 0; port < edev->nb_event_ports; port++)
400 ssows_dump(dev->data->ports[port], f);
404 ssovf_start(struct rte_eventdev *dev)
406 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
412 for (i = 0; i < edev->nb_event_ports; i++) {
413 ws = dev->data->ports[i];
418 for (i = 0; i < edev->nb_event_queues; i++) {
419 /* Consume all the events through HWS0 */
420 ssows_flush_events(dev->data->ports[0], i);
422 base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
423 base += SSO_VHGRP_QCTL;
424 ssovf_write64(1, base); /* Enable SSO group */
427 ssovf_fastpath_fns_set(dev);
432 ssovf_stop(struct rte_eventdev *dev)
434 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
440 for (i = 0; i < edev->nb_event_ports; i++) {
441 ws = dev->data->ports[i];
446 for (i = 0; i < edev->nb_event_queues; i++) {
447 /* Consume all the events through HWS0 */
448 ssows_flush_events(dev->data->ports[0], i);
450 base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
451 base += SSO_VHGRP_QCTL;
452 ssovf_write64(0, base); /* Disable SSO group */
457 ssovf_close(struct rte_eventdev *dev)
459 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
460 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
463 for (i = 0; i < edev->nb_event_queues; i++)
466 for (i = 0; i < edev->nb_event_ports; i++)
467 ssovf_port_unlink(dev, dev->data->ports[i], all_queues,
468 edev->nb_event_queues);
472 /* Initialize and register event driver with DPDK Application */
473 static const struct rte_eventdev_ops ssovf_ops = {
474 .dev_infos_get = ssovf_info_get,
475 .dev_configure = ssovf_configure,
476 .queue_def_conf = ssovf_queue_def_conf,
477 .queue_setup = ssovf_queue_setup,
478 .queue_release = ssovf_queue_release,
479 .port_def_conf = ssovf_port_def_conf,
480 .port_setup = ssovf_port_setup,
481 .port_release = ssovf_port_release,
482 .port_link = ssovf_port_link,
483 .port_unlink = ssovf_port_unlink,
484 .timeout_ticks = ssovf_timeout_ticks,
486 .dev_start = ssovf_start,
487 .dev_stop = ssovf_stop,
488 .dev_close = ssovf_close
492 ssovf_vdev_probe(struct rte_vdev_device *vdev)
494 struct octeontx_ssovf_info oinfo;
495 struct ssovf_mbox_dev_info info;
496 struct ssovf_evdev *edev;
497 struct rte_eventdev *eventdev;
498 static int ssovf_init_once;
502 name = rte_vdev_device_name(vdev);
503 /* More than one instance is not supported */
504 if (ssovf_init_once) {
505 ssovf_log_err("Request to create >1 %s instance", name);
509 eventdev = rte_event_pmd_vdev_init(name, sizeof(struct ssovf_evdev),
511 if (eventdev == NULL) {
512 ssovf_log_err("Failed to create eventdev vdev %s", name);
515 eventdev->dev_ops = &ssovf_ops;
517 /* For secondary processes, the primary has done all the work */
518 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
519 ssovf_fastpath_fns_set(eventdev);
523 ret = octeontx_ssovf_info(&oinfo);
525 ssovf_log_err("Failed to probe and validate ssovfs %d", ret);
529 edev = ssovf_pmd_priv(eventdev);
530 edev->max_event_ports = oinfo.total_ssowvfs;
531 edev->max_event_queues = oinfo.total_ssovfs;
532 edev->is_timeout_deq = 0;
534 ret = ssovf_mbox_dev_info(&info);
535 if (ret < 0 || ret != sizeof(struct ssovf_mbox_dev_info)) {
536 ssovf_log_err("Failed to get mbox devinfo %d", ret);
540 edev->min_deq_timeout_ns = info.min_deq_timeout_ns;
541 edev->max_deq_timeout_ns = info.max_deq_timeout_ns;
542 edev->max_num_events = info.max_num_events;
543 ssovf_log_dbg("min_deq_tmo=%"PRId64" max_deq_tmo=%"PRId64" max_evts=%d",
544 info.min_deq_timeout_ns, info.max_deq_timeout_ns,
545 info.max_num_events);
547 if (!edev->max_event_ports || !edev->max_event_queues) {
548 ssovf_log_err("Not enough eventdev resource queues=%d ports=%d",
549 edev->max_event_queues, edev->max_event_ports);
554 ssovf_log_info("Initializing %s domain=%d max_queues=%d max_ports=%d",
555 name, oinfo.domain, edev->max_event_queues,
556 edev->max_event_ports);
562 rte_event_pmd_vdev_uninit(name);
567 ssovf_vdev_remove(struct rte_vdev_device *vdev)
571 name = rte_vdev_device_name(vdev);
572 ssovf_log_info("Closing %s", name);
573 return rte_event_pmd_vdev_uninit(name);
576 static struct rte_vdev_driver vdev_ssovf_pmd = {
577 .probe = ssovf_vdev_probe,
578 .remove = ssovf_vdev_remove
581 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_OCTEONTX_PMD, vdev_ssovf_pmd);