1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
5 #include <rte_atomic.h>
6 #include <rte_common.h>
10 #include <rte_bus_pci.h>
12 #include "octeontx_mbox.h"
13 #include "ssovf_evdev.h"
15 #define PCI_VENDOR_ID_CAVIUM 0x177D
16 #define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
17 #define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
19 #define SSO_MAX_VHGRP (64)
20 #define SSO_MAX_VHWS (32)
37 struct ssowvf_identify {
44 uint8_t total_ssowvfs;
45 struct ssovf_res grp[SSO_MAX_VHGRP];
46 struct ssowvf_res hws[SSO_MAX_VHWS];
49 static struct ssodev sdev;
51 /* Interface functions */
53 ssovf_info(struct ssovf_info *info)
58 if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
61 if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
64 domain = sdev.grp[0].domain;
65 for (i = 0; i < sdev.total_ssovfs; i++) {
66 /* Check vfid's are contiguous and belong to same domain */
67 if (sdev.grp[i].vfid != i ||
68 sdev.grp[i].bar0 == NULL ||
69 sdev.grp[i].domain != domain) {
70 mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
72 domain, sdev.grp[i].domain,
78 for (i = 0; i < sdev.total_ssowvfs; i++) {
79 /* Check vfid's are contiguous and belong to same domain */
80 if (sdev.hws[i].vfid != i ||
81 sdev.hws[i].bar0 == NULL ||
82 sdev.hws[i].domain != domain) {
83 mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
85 domain, sdev.hws[i].domain,
91 info->domain = domain;
92 info->total_ssovfs = sdev.total_ssovfs;
93 info->total_ssowvfs = sdev.total_ssowvfs;
98 ssovf_bar(enum ssovf_type type, uint8_t id, uint8_t bar)
100 if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
101 type > OCTEONTX_SSO_HWS)
104 if (type == OCTEONTX_SSO_GROUP) {
105 if (id >= sdev.total_ssovfs)
108 if (id >= sdev.total_ssowvfs)
112 if (type == OCTEONTX_SSO_GROUP) {
115 return sdev.grp[id].bar0;
117 return sdev.grp[id].bar2;
124 return sdev.hws[id].bar0;
126 return sdev.hws[id].bar2;
128 return sdev.hws[id].bar4;
135 /* SSOWVF pcie device aka event port probe */
138 ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
141 struct ssowvf_res *res;
142 struct ssowvf_identify *id;
143 uint8_t *ram_mbox_base;
145 RTE_SET_USED(pci_drv);
147 /* For secondary processes, the primary has done all the work */
148 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
151 if (pci_dev->mem_resource[0].addr == NULL ||
152 pci_dev->mem_resource[2].addr == NULL ||
153 pci_dev->mem_resource[4].addr == NULL) {
154 mbox_log_err("Empty bars %p %p %p",
155 pci_dev->mem_resource[0].addr,
156 pci_dev->mem_resource[2].addr,
157 pci_dev->mem_resource[4].addr);
161 if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
162 mbox_log_err("Bar4 len mismatch %d != %d",
163 SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
167 id = pci_dev->mem_resource[4].addr;
169 if (vfid >= SSO_MAX_VHWS) {
170 mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
174 res = &sdev.hws[vfid];
176 res->bar0 = pci_dev->mem_resource[0].addr;
177 res->bar2 = pci_dev->mem_resource[2].addr;
178 res->bar4 = pci_dev->mem_resource[4].addr;
179 res->domain = id->domain;
181 sdev.total_ssowvfs++;
183 ram_mbox_base = ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);
184 if (octeontx_mbox_set_ram_mbox_base(ram_mbox_base,
186 mbox_log_err("Invalid Failed to set ram mbox base");
192 mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
193 res->vfid, sdev.total_ssowvfs);
197 static const struct rte_pci_id pci_ssowvf_map[] = {
199 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
200 PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
207 static struct rte_pci_driver pci_ssowvf = {
208 .id_table = pci_ssowvf_map,
209 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
210 .probe = ssowvf_probe,
213 RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
215 /* SSOVF pcie device aka event queue probe */
218 ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
223 struct ssovf_res *res;
226 RTE_SET_USED(pci_drv);
228 /* For secondary processes, the primary has done all the work */
229 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
232 if (pci_dev->mem_resource[0].addr == NULL ||
233 pci_dev->mem_resource[2].addr == NULL) {
234 mbox_log_err("Empty bars %p %p",
235 pci_dev->mem_resource[0].addr,
236 pci_dev->mem_resource[2].addr);
239 idreg = pci_dev->mem_resource[0].addr;
240 idreg += SSO_VHGRP_AQ_THR;
241 val = rte_read64(idreg);
243 /* Write back the default value of aq_thr */
244 rte_write64((1ULL << 33) - 1, idreg);
245 vfid = (val >> 16) & 0xffff;
246 if (vfid >= SSO_MAX_VHGRP) {
247 mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
251 res = &sdev.grp[vfid];
253 res->bar0 = pci_dev->mem_resource[0].addr;
254 res->bar2 = pci_dev->mem_resource[2].addr;
255 res->domain = val & 0xffff;
259 reg = ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);
260 reg += SSO_VHGRP_PF_MBOX(1);
261 if (octeontx_mbox_set_reg(reg, res->domain)) {
262 mbox_log_err("Invalid Failed to set mbox_reg");
268 mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
269 res->vfid, sdev.total_ssovfs);
273 static const struct rte_pci_id pci_ssovf_map[] = {
275 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
276 PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
283 static struct rte_pci_driver pci_ssovf = {
284 .id_table = pci_ssovf_map,
285 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
286 .probe = ssovf_probe,
289 RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);