4 * Copyright (C) Cavium networks Ltd. 2017.
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33 #include <rte_atomic.h>
34 #include <rte_common.h>
39 #include "ssovf_evdev.h"
50 struct ssovf_res grp[SSO_MAX_VHGRP];
52 static struct ssodev sdev;
54 /* SSOVF pcie device aka event queue probe */
57 ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
62 struct ssovf_res *res;
64 RTE_SET_USED(pci_drv);
66 /* For secondary processes, the primary has done all the work */
67 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
70 if (pci_dev->mem_resource[0].addr == NULL ||
71 pci_dev->mem_resource[2].addr == NULL) {
72 ssovf_log_err("Empty bars %p %p",
73 pci_dev->mem_resource[0].addr,
74 pci_dev->mem_resource[2].addr);
77 idreg = pci_dev->mem_resource[0].addr;
78 idreg += SSO_VHGRP_AQ_THR;
79 val = rte_read64(idreg);
81 /* Write back the default value of aq_thr */
82 rte_write64((1ULL << 33) - 1, idreg);
83 vfid = (val >> 16) & 0xffff;
84 if (vfid >= SSO_MAX_VHGRP) {
85 ssovf_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
89 res = &sdev.grp[vfid];
91 res->bar0 = pci_dev->mem_resource[0].addr;
92 res->bar2 = pci_dev->mem_resource[2].addr;
93 res->domain = val & 0xffff;
97 ssovf_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
98 res->vfid, sdev.total_ssovfs);
102 static const struct rte_pci_id pci_ssovf_map[] = {
104 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
105 PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
112 static struct rte_pci_driver pci_ssovf = {
113 .id_table = pci_ssovf_map,
114 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
115 .probe = ssovf_probe,
118 RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);