4 * Copyright (C) Cavium networks Ltd. 2017.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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18 * from this software without specific prior written permission.
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <rte_atomic.h>
34 #include <rte_common.h>
39 #include "ssovf_evdev.h"
56 struct ssowvf_identify {
63 uint8_t total_ssowvfs;
64 struct ssovf_res grp[SSO_MAX_VHGRP];
65 struct ssowvf_res hws[SSO_MAX_VHWS];
68 static struct ssodev sdev;
70 /* SSOWVF pcie device aka event port probe */
73 ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
76 struct ssowvf_res *res;
77 struct ssowvf_identify *id;
79 RTE_SET_USED(pci_drv);
81 /* For secondary processes, the primary has done all the work */
82 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
85 if (pci_dev->mem_resource[0].addr == NULL ||
86 pci_dev->mem_resource[2].addr == NULL ||
87 pci_dev->mem_resource[4].addr == NULL) {
88 ssovf_log_err("Empty bars %p %p %p",
89 pci_dev->mem_resource[0].addr,
90 pci_dev->mem_resource[2].addr,
91 pci_dev->mem_resource[4].addr);
95 if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
96 ssovf_log_err("Bar4 len mismatch %d != %d",
97 SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
101 id = pci_dev->mem_resource[4].addr;
103 if (vfid >= SSO_MAX_VHWS) {
104 ssovf_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
108 res = &sdev.hws[vfid];
110 res->bar0 = pci_dev->mem_resource[0].addr;
111 res->bar2 = pci_dev->mem_resource[2].addr;
112 res->bar4 = pci_dev->mem_resource[4].addr;
113 res->domain = id->domain;
115 sdev.total_ssowvfs++;
117 ssovf_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
118 res->vfid, sdev.total_ssowvfs);
122 static const struct rte_pci_id pci_ssowvf_map[] = {
124 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
125 PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
132 static struct rte_pci_driver pci_ssowvf = {
133 .id_table = pci_ssowvf_map,
134 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
135 .probe = ssowvf_probe,
138 RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
140 /* SSOVF pcie device aka event queue probe */
143 ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
148 struct ssovf_res *res;
150 RTE_SET_USED(pci_drv);
152 /* For secondary processes, the primary has done all the work */
153 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
156 if (pci_dev->mem_resource[0].addr == NULL ||
157 pci_dev->mem_resource[2].addr == NULL) {
158 ssovf_log_err("Empty bars %p %p",
159 pci_dev->mem_resource[0].addr,
160 pci_dev->mem_resource[2].addr);
163 idreg = pci_dev->mem_resource[0].addr;
164 idreg += SSO_VHGRP_AQ_THR;
165 val = rte_read64(idreg);
167 /* Write back the default value of aq_thr */
168 rte_write64((1ULL << 33) - 1, idreg);
169 vfid = (val >> 16) & 0xffff;
170 if (vfid >= SSO_MAX_VHGRP) {
171 ssovf_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
175 res = &sdev.grp[vfid];
177 res->bar0 = pci_dev->mem_resource[0].addr;
178 res->bar2 = pci_dev->mem_resource[2].addr;
179 res->domain = val & 0xffff;
183 ssovf_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
184 res->vfid, sdev.total_ssovfs);
188 static const struct rte_pci_id pci_ssovf_map[] = {
190 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
191 PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
198 static struct rte_pci_driver pci_ssovf = {
199 .id_table = pci_ssovf_map,
200 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
201 .probe = ssovf_probe,
204 RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);